From 9fe199f7c78d66e5a36b568996901b955717c8ab Mon Sep 17 00:00:00 2001
From: dam1n19 <dam1n19@soton.ac.uk>
Date: Fri, 30 Jun 2023 11:12:00 +0100
Subject: [PATCH] Moved filelist into this repo

---
 flist/generic_lib_ip.flist | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)
 create mode 100644 flist/generic_lib_ip.flist

diff --git a/flist/generic_lib_ip.flist b/flist/generic_lib_ip.flist
new file mode 100644
index 0000000..3995db3
--- /dev/null
+++ b/flist/generic_lib_ip.flist
@@ -0,0 +1,25 @@
+//-----------------------------------------------------------------------------
+// Generic Library Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for Generic Library
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// =============    Accelerator Module search path    =============
+$(SOCLABS_GENERIC_LIB_TECH_DIR)/pads/verilog/PAD_INOUT8MA_NOE.v
+$(SOCLABS_GENERIC_LIB_TECH_DIR)/pads/verilog/PAD_VDDIO.v
+$(SOCLABS_GENERIC_LIB_TECH_DIR)/pads/verilog/PAD_VSSIO.v
+$(SOCLABS_GENERIC_LIB_TECH_DIR)/pads/verilog/PAD_VDDSOC.v
+$(SOCLABS_GENERIC_LIB_TECH_DIR)/pads/verilog/PAD_VSS.v
+$(SOCLABS_GENERIC_LIB_TECH_DIR)/mem/verilog/SROM_Ax32.v
+$(SOCLABS_GENERIC_LIB_TECH_DIR)/sync/verilog/SYNCHRONIZER_EDGES.v
\ No newline at end of file
-- 
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