//----------------------------------------------------------------------------- // FPGA Library Memory Filelist // A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. // // Contributors // // David Mapstone (d.a.mapstone@soton.ac.uk) // // Copyright � 2021-3, SoC Labs (www.soclabs.org) //----------------------------------------------------------------------------- //----------------------------------------------------------------------------- // Abstract : Verilog Command File for NanoSoC Testbench //----------------------------------------------------------------------------- // ============= Verilog library extensions =========== +libext+.v+.vlib // ============= NanoSoC Testbench search path ============= // +incdir+$(SOCLABS_FPGA_LIB_TECH_DIR)/sram/verilog/ // - Top-level testbench $(SOCLABS_FPGA_LIB_TECH_DIR)/sram/verilog/sl_ahb_sram.v $(SOCLABS_FPGA_LIB_TECH_DIR)/rom/verilog/sl_ahb_rom.v