From ab5ecd8c76ce4ce98954c1549555ca88faad973e Mon Sep 17 00:00:00 2001 From: dam1n19 <dam1n19@soton.ac.uk> Date: Fri, 30 Jun 2023 11:12:14 +0100 Subject: [PATCH] Moved filelist into repo --- flist/fpga_lib_mem_ip.flist | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 flist/fpga_lib_mem_ip.flist diff --git a/flist/fpga_lib_mem_ip.flist b/flist/fpga_lib_mem_ip.flist new file mode 100644 index 0000000..4315755 --- /dev/null +++ b/flist/fpga_lib_mem_ip.flist @@ -0,0 +1,23 @@ +//----------------------------------------------------------------------------- +// FPGA Library Memory Filelist +// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. +// +// Contributors +// +// David Mapstone (d.a.mapstone@soton.ac.uk) +// +// Copyright � 2021-3, SoC Labs (www.soclabs.org) +//----------------------------------------------------------------------------- +//----------------------------------------------------------------------------- +// Abstract : Verilog Command File for NanoSoC Testbench +//----------------------------------------------------------------------------- + +// ============= Verilog library extensions =========== ++libext+.v+.vlib + +// ============= NanoSoC Testbench search path ============= +// +incdir+$(SOCLABS_FPGA_LIB_TECH_DIR)/sram/verilog/ + +// - Top-level testbench +$(SOCLABS_FPGA_LIB_TECH_DIR)/sram/verilog/sl_ahb_sram.v +$(SOCLABS_FPGA_LIB_TECH_DIR)/rom/verilog/sl_ahb_rom.v \ No newline at end of file -- GitLab