diff --git a/sram/verilog/sl_ahb_sram.v b/sram/verilog/sl_ahb_sram.v
index 7d86adf65293b47bb1b6e581068719486b46980f..ca625b68d7ce59bfa8ce370ead1123aa1eca3713 100644
--- a/sram/verilog/sl_ahb_sram.v
+++ b/sram/verilog/sl_ahb_sram.v
@@ -14,8 +14,7 @@ module sl_ahb_sram #(
     // System Parameters
     parameter SYS_DATA_W = 32,  // System Data Width
     parameter RAM_ADDR_W = 14,  // Size of SRAM
-    parameter RAM_DATA_W = 32,  // Data Width of RAM
-    parameter FILENAME   = "image.hex" // Initial Image to Populate Memory with
+    parameter RAM_DATA_W = 32   // Data Width of RAM
 )(
     // --------------------------------------------------------------------------
     // Port Definitions