From 3e6eea8f70104378841ddb7032399cebcf43686f Mon Sep 17 00:00:00 2001
From: dam1n19 <dam1n19@soton.ac.uk>
Date: Thu, 22 Jun 2023 09:12:22 +0100
Subject: [PATCH] Changed Path for SRAM file wrapper
---
sram/{ => verilog}/sl_ahb_sram.v | 17 ++++++++++-------
1 file changed, 10 insertions(+), 7 deletions(-)
rename sram/{ => verilog}/sl_ahb_sram.v (86%)
diff --git a/sram/sl_ahb_sram.v b/sram/verilog/sl_ahb_sram.v
similarity index 86%
rename from sram/sl_ahb_sram.v
rename to sram/verilog/sl_ahb_sram.v
index 3c0fe76..d9c3e54 100644
--- a/sram/sl_ahb_sram.v
+++ b/sram/verilog/sl_ahb_sram.v
@@ -11,7 +11,11 @@
//-----------------------------------------------------------------------------
module sl_ahb_sram #(
- parameter RAM_ADDR_W = 14, // Size of SRAM
+ // System Parameters
+ parameter SYS_ADDR_W = 32, // System Address Width
+ parameter SYS_DATA_W = 32, // System Data Width
+ parameter RAM_ADDR_W = 14, // Size of SRAM
+ parameter RAM_DATA_W = 32, // Data Width of RAM
parameter FILENAME = "image.hex" // Initial Image to Populate Memory with
)(
// --------------------------------------------------------------------------
@@ -28,13 +32,13 @@ module sl_ahb_sram #(
input wire [31:0] HWDATA, // AHB write data bus
output wire HREADYOUT, // AHB ready output to S->M mux
output wire HRESP, // AHB response
- output wire [31:0] HRDATA // AHB read data bus
+ output wire [SYS_DATA_W-1:0] HRDATA // AHB read data bus
);
// Internal Wiring
wire [RAM_ADDR_W-3:0] addr;
- wire [RAM_ADDR_W-1:0] wdata;
- wire [RAM_ADDR_W-1:0] rdata;
+ wire [RAM_DATA_W-1:0] wdata;
+ wire [RAM_DATA_W-1:0] rdata;
wire [3:0] wen;
wire cs;
@@ -51,7 +55,7 @@ module sl_ahb_sram #(
.HSIZE (HSIZE),
.HWRITE (HWRITE),
.HWDATA (HWDATA),
- .HREADY (HREADYMUX),
+ .HREADY (HREADY),
// AHB Outputs
.HREADYOUT (HREADYOUT),
@@ -70,8 +74,7 @@ module sl_ahb_sram #(
// FPGA SRAM model
cmsdk_fpga_sram #(
- .AW (RAM_ADDR_W),
- .filename (FILENAME)
+ .AW (RAM_ADDR_W)
) u_sram (
// SRAM Inputs
.CLK (HCLK),
--
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