From 4a6433e57dde06b2c03e379d3ad99d0f4aeffa4b Mon Sep 17 00:00:00 2001
From: dwn1c21 <d.newbrook@soton.ac.uk>
Date: Sat, 20 Apr 2024 17:26:17 +0000
Subject: [PATCH] Update README

---
 README.md | 22 +++++++++++++++++++---
 1 file changed, 19 insertions(+), 3 deletions(-)

diff --git a/README.md b/README.md
index e8537f0..99d5661 100644
--- a/README.md
+++ b/README.md
@@ -15,14 +15,30 @@ You will need the following IP from Arm, all available through Arm Academic Acce
 -   NIC400
 
 You will also need installed
--   Socrates
+-   Socrates (with NIC400 IP and license)
 -   CocoTB
 -   A simulator (e.g. QuestaSim, VCS, xelium)
 
 For FPGA development you will need a Vivado installation
 
-## Usage
-
+## Setup
+1. Setup make config
+You will first need to add the path to the DMA-350 and BP301 (SIE300) logical directories. Edit the make.cfg file at the top level of this repository to point to the logical directories of each IP
+2. Build configured IP
+If this is a fresh version of the repository, you can run:
+```make first_time_setup```
+This will generate the RTL for the DMA-350 and BP301, it will also create a socrates project for the generation of the NIC400 RTL. You may see a lot of warnings during the building of the NIC400, these are expected. Once run you can check the logical/ directory of the local repository which should contain - DMA350, SMC, and nic400_expansion_subsystem
+
+If you have already run ```make first_time_setup``` or ```make make_project``` you can run:
+```make build_ip```
+which will build all of the necessary IP.
+3. Setup environment variables
+You can run ```source set_exp_env.sh``` which will setup the relevant environment variables
+
+## Simulation
+Currently cocoTB is the only supported method of simulation, although a verilog testbench is under developement.
+To run the current cocoTB verification go to verif/cocotb and run ```make```
+This will run the default tests for the expansion subsystem. You can edit the expansion_subsystem_tests.py file to include further tests
 
 ## Accelerator integration
 The subsystem has an expansion region where you can integrate your accelerator. This includes a full AXI slave port with 128-bit data width, an APB port for register interfacing with your accelerator, as well as clock and power control (Q and P-channel).
-- 
GitLab