diff --git a/.gitignore b/.gitignore
index f52fead7504373dcc70f55233e18457449d65c51..0f1ba16fa86744ee44916b736f669acf2852c7f2 100644
--- a/.gitignore
+++ b/.gitignore
@@ -3,7 +3,7 @@
 
 logical/dma350
 logical/SMC
-logical/nic400_millisoc_expansion
+logical/nic400_expansion_subsystem
 logical/shared
 
 verif/cocotb/sim_build
diff --git a/README.md b/README.md
index ca324d100a27e23fad6b312e52e390b23eea31e1..e8537f0c6129d54feaae1c7b9ca800a0a306b5dc 100644
--- a/README.md
+++ b/README.md
@@ -1,8 +1,8 @@
-# MilliSoC Expansion Tech
+# Expansion Subsystem Tech
 
 
 
-Part of the milliSoC SoC reference design. This expansion sub-system is where you will integrate your accelerator IP into.
+Part of the milliSoC and megaSoC SoC reference design. This expansion sub-system is where you will integrate your accelerator IP into.
 This subsystem includes a DMA-350, 2x 128 bit SRAMs, and an adress region for your accelerator.
 The purpose of this subsystem is deliver high bandwidth data to and from your hardware accelerator. The NIC400 bus with DMA-350 as master can reach bandwidths of 106 Gbps at a clock speed of 1 GHz
 
diff --git a/flist/millisoc_expansion.vc b/flist/expansion_subsystem.vc
similarity index 100%
rename from flist/millisoc_expansion.vc
rename to flist/expansion_subsystem.vc
diff --git a/flist/expansion_subsystem_cocotb.flist b/flist/expansion_subsystem_cocotb.flist
new file mode 100644
index 0000000000000000000000000000000000000000..2a1f8902c6bbb14b3b9f2155d7971da09040a08d
--- /dev/null
+++ b/flist/expansion_subsystem_cocotb.flist
@@ -0,0 +1,445 @@
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/expansion_region/verilog/expansion_region.v
+
+#SRAM files
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/SRAM/verilog/SRAM_wrapper.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/SRAM/verilog/SRAM.v
+#BP301 SRAM controller files
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/SMC/logical/models/cells/generic/sie300_arm_and2.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/SMC/logical/models/cells/generic/sie300_arm_or2.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/SMC/logical/models/cells/generic/sie300_arm_sdff2yrpq.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/SMC/logical/models/cells/generic/sie300_arm_xor2.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/SMC/logical/shared/verilog/sie300_or_tree/verilog/sie300_or_tree.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/SMC/logical/shared/verilog/sie300_sync/verilog/sie300_sync.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_expansion_subsystem/verilog/sie300_axi5_sram_ctrl_expansion_subsystem.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_expansion_subsystem/verilog/sie300_axi5_sram_ctrl_expansion_subsystem_addr_dec.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_expansion_subsystem/verilog/sie300_axi5_sram_ctrl_expansion_subsystem_arb.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_expansion_subsystem/verilog/sie300_axi5_sram_ctrl_expansion_subsystem_arq.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_expansion_subsystem/verilog/sie300_axi5_sram_ctrl_expansion_subsystem_awq.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_expansion_subsystem/verilog/sie300_axi5_sram_ctrl_expansion_subsystem_axi_mux.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_expansion_subsystem/verilog/sie300_axi5_sram_ctrl_expansion_subsystem_bq.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_expansion_subsystem/verilog/sie300_axi5_sram_ctrl_expansion_subsystem_clamp.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_expansion_subsystem/verilog/sie300_axi5_sram_ctrl_expansion_subsystem_eam.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_expansion_subsystem/verilog/sie300_axi5_sram_ctrl_expansion_subsystem_fifo.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_expansion_subsystem/verilog/sie300_axi5_sram_ctrl_expansion_subsystem_fifo_core.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_expansion_subsystem/verilog/sie300_axi5_sram_ctrl_expansion_subsystem_lpi_ctrl.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_expansion_subsystem/verilog/sie300_axi5_sram_ctrl_expansion_subsystem_one_hot.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_expansion_subsystem/verilog/sie300_axi5_sram_ctrl_expansion_subsystem_rbeat.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_expansion_subsystem/verilog/sie300_axi5_sram_ctrl_expansion_subsystem_resp_gen.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_expansion_subsystem/verilog/sie300_axi5_sram_ctrl_expansion_subsystem_rq.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_expansion_subsystem/verilog/sie300_axi5_sram_ctrl_expansion_subsystem_wbeat.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_expansion_subsystem/verilog/sie300_axi5_sram_ctrl_expansion_subsystem_wq.sv
+
+#DMA350 files
+
+EXTRA_ARGS += +incdir+$(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/shared/verilog
+
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_gen_regmap_sldma350_pkg.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_apb_regmap_conv_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_reg_field_ro_ro_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_reg_field_rw_ro_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_reg_field_rw_w1c_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_reg_field_rw_w1s_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_reg_field_rw_rw_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_gen_coreif_dmach_sldma350_pkg.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_gen_addrmap_dmach_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_interface_sldma350_pkg.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_flop_en/verilog/ada_flop_en.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_or_tree/verilog/ada_or_tree.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_gen_regif_dmainfo_sldma350_pkg.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/models/cells/generic/ada_arm_flop.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/models/cells/generic/ada_arm_sync.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/models/cells/generic/ada_arm_mux2.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/models/cells/generic/ada_arm_or.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/models/cells/generic/ada_arm_idbit_v1.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_ecorevnum.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_top_sldma350/verilog/ada_top_sldma350.sv
+
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_gen_regif_dmach_0_sldma350_pkg.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_gen_regif_dmach_0_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_gen_regmap_dmach_0_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_gen_fields_coreif_dmach_0_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_gen_coreif_res_dmach_0_sldma350_pkg.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_sldma350_pkg.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_ctrl_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_1d_wr_ctrl_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_2d_wr_ctrl_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_1d_rd_ctrl_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_2d_rd_ctrl_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_fifo_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_cmdlink_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_axi_rd_if_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_axi_wr_if_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_axi_stop_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_reg_bank_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_inc_gen_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_stream_wrapper_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_stream_slave_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_stream_master_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_stream_bypass_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_trig_in_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_trig_out_sldma350.sv
+
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_gen_regif_dmach_1_sldma350_pkg.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_gen_regif_dmach_1_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_gen_regmap_dmach_1_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_gen_fields_coreif_dmach_1_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_gen_coreif_res_dmach_1_sldma350_pkg.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_sldma350_pkg.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_ctrl_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_1d_wr_ctrl_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_2d_wr_ctrl_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_1d_rd_ctrl_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_2d_rd_ctrl_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_fifo_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_cmdlink_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_axi_rd_if_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_axi_wr_if_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_axi_stop_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_reg_bank_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_inc_gen_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_stream_wrapper_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_stream_slave_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_stream_master_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_stream_bypass_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_trig_in_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_trig_out_sldma350.sv
+
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_gen_regif_dmach_2_sldma350_pkg.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_gen_regif_dmach_2_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_gen_regmap_dmach_2_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_gen_fields_coreif_dmach_2_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_gen_coreif_res_dmach_2_sldma350_pkg.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_sldma350_pkg.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_ctrl_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_1d_wr_ctrl_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_1d_rd_ctrl_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_fifo_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_cmdlink_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_axi_rd_if_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_axi_wr_if_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_axi_stop_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_reg_bank_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_trig_in_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_trig_out_sldma350.sv
+
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_gen_regif_dmach_3_sldma350_pkg.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_gen_regif_dmach_3_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_gen_regmap_dmach_3_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_gen_fields_coreif_dmach_3_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_gen_coreif_res_dmach_3_sldma350_pkg.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_sldma350_pkg.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_ctrl_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_1d_wr_ctrl_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_1d_rd_ctrl_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_fifo_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_cmdlink_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_axi_rd_if_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_axi_wr_if_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_axi_stop_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_reg_bank_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_trig_in_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_trig_out_sldma350.sv
+
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_read_switch_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_read_switch_wrapper_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_write_switch_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_write_switch_wrapper_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_arbiter_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_qv_cmp_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_lrg_arb_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_grant_queue_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_full_f2s_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_reverse_s2f_sldma350.sv
+
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_regif_dmainfo_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_regmap_dmainfo_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_fields_coreif_dmainfo_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_addrmap_dmainfo_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_coreif_dmansecctrl_sldma350_pkg.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_regif_dmansecctrl_sldma350_pkg.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_regif_dmansecctrl_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_regmap_dmansecctrl_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_fields_coreif_dmansecctrl_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_addrmap_dmansecctrl_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_ctrl_apb_slave_mux_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_ctrl_dmainfo_reg_bank_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_ctrl_dmansecctrl_reg_bank_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_ctrl_trigmask_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_ctrl_trigin_used_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_ctrl_trigout_used_sldma350.sv
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_ctrl_sldma350.sv
+
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_trigmtx_sldma350/verilog/ada_trigmtx_sldma350.sv
+
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/dma350/logical/ada_qctrl_sldma350/verilog/ada_qctrl_sldma350.sv
+
+#NIC400 files
+EXTRA_ARGS += +incdir+$(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/amib_AXI_EXPANSION/verilog
+EXTRA_ARGS += +incdir+$(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/amib_AXI_EXP_SRAM_0/verilog
+EXTRA_ARGS += +incdir+$(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/amib_AXI_EXP_SRAM_1/verilog
+EXTRA_ARGS += +incdir+$(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/amib_AXI_SYS/verilog
+EXTRA_ARGS += +incdir+$(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/amib_apb_group0/verilog
+EXTRA_ARGS += +incdir+$(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/asib_AXI_DMA_0/verilog
+EXTRA_ARGS += +incdir+$(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/asib_AXI_DMA_1/verilog
+EXTRA_ARGS += +incdir+$(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/asib_AXI_EXP_SS/verilog
+EXTRA_ARGS += +incdir+$(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm0/verilog
+EXTRA_ARGS += +incdir+$(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm1/verilog
+EXTRA_ARGS += +incdir+$(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/cdc_blocks/verilog
+EXTRA_ARGS += +incdir+$(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/default_slave_ds_3/verilog
+EXTRA_ARGS += +incdir+$(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/default_slave_ds_4/verilog
+EXTRA_ARGS += +incdir+$(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/dmu_exp/verilog
+EXTRA_ARGS += +incdir+$(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/dmu_sys/verilog
+EXTRA_ARGS += +incdir+$(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_AXI_SYS_ib/verilog
+EXTRA_ARGS += +incdir+$(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_apb_group0_ib/verilog
+EXTRA_ARGS += +incdir+$(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_ib2/verilog
+EXTRA_ARGS += +incdir+$(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/reg_slice/verilog
+
+EXTRA_ARGS += +incdir+$(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/nic400/verilog
+EXTRA_ARGS += +incdir+$(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/reg_slice/verilog
+EXTRA_ARGS += +incdir+$(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/shared/validation/tb_components/Axi4Frm
+EXTRA_ARGS += +incdir+$(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/shared/validation/tb_components
+EXTRA_ARGS += +incdir+$(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/shared/validation/tb_components/AxiFrm
+EXTRA_ARGS += +incdir+$(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/shared/validation/tb_components/AxiFrs
+EXTRA_ARGS += +incdir+$(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/nic400/verilog/Axi
+EXTRA_ARGS += +incdir+$(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/nic400/verilog/ApbPC
+EXTRA_ARGS += +incdir+$(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/nic400/verilog/Apb4PC
+EXTRA_ARGS += +incdir+$(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/nic400/verilog/AxiPC
+EXTRA_ARGS += +incdir+$(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/nic400/verilog/Axi4PC
+
+
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/nic400/verilog/nic400_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/amib_AXI_EXPANSION/verilog/nic400_amib_AXI_EXPANSION_chan_slice_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/amib_AXI_EXPANSION/verilog/nic400_amib_AXI_EXPANSION_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/amib_AXI_EXP_SRAM_0/verilog/nic400_amib_AXI_EXP_SRAM_0_chan_slice_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/amib_AXI_EXP_SRAM_0/verilog/nic400_amib_AXI_EXP_SRAM_0_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/amib_AXI_EXP_SRAM_1/verilog/nic400_amib_AXI_EXP_SRAM_1_chan_slice_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/amib_AXI_EXP_SRAM_1/verilog/nic400_amib_AXI_EXP_SRAM_1_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/amib_AXI_SYS/verilog/nic400_amib_AXI_SYS_chan_slice_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/amib_AXI_SYS/verilog/nic400_amib_AXI_SYS_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/amib_apb_group0/verilog/nic400_amib_apb_group0_a_gen_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/amib_apb_group0/verilog/nic400_amib_apb_group0_apb_m_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/amib_apb_group0/verilog/nic400_amib_apb_group0_chan_slice_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/amib_apb_group0/verilog/nic400_amib_apb_group0_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/asib_AXI_DMA_0/verilog/nic400_asib_AXI_DMA_0_chan_slice_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/asib_AXI_DMA_0/verilog/nic400_asib_AXI_DMA_0_decode_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/asib_AXI_DMA_0/verilog/nic400_asib_AXI_DMA_0_maskcntl_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/asib_AXI_DMA_0/verilog/nic400_asib_AXI_DMA_0_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/asib_AXI_DMA_0/verilog/nic400_asib_AXI_DMA_0_rd_ss_cdas_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/asib_AXI_DMA_0/verilog/nic400_asib_AXI_DMA_0_wr_ss_cdas_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/asib_AXI_DMA_1/verilog/nic400_asib_AXI_DMA_1_chan_slice_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/asib_AXI_DMA_1/verilog/nic400_asib_AXI_DMA_1_decode_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/asib_AXI_DMA_1/verilog/nic400_asib_AXI_DMA_1_maskcntl_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/asib_AXI_DMA_1/verilog/nic400_asib_AXI_DMA_1_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/asib_AXI_DMA_1/verilog/nic400_asib_AXI_DMA_1_rd_ss_cdas_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/asib_AXI_DMA_1/verilog/nic400_asib_AXI_DMA_1_wr_ss_cdas_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/asib_AXI_EXP_SS/verilog/nic400_asib_AXI_EXP_SS_chan_slice_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/asib_AXI_EXP_SS/verilog/nic400_asib_AXI_EXP_SS_decode_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/asib_AXI_EXP_SS/verilog/nic400_asib_AXI_EXP_SS_maskcntl_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/asib_AXI_EXP_SS/verilog/nic400_asib_AXI_EXP_SS_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/asib_AXI_EXP_SS/verilog/nic400_asib_AXI_EXP_SS_rd_ss_cdas_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/asib_AXI_EXP_SS/verilog/nic400_asib_AXI_EXP_SS_wr_ss_cdas_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml0_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml1_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml2_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml0_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml1_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml2_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm0/verilog/nic400_bm0_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm0/verilog/nic400_bm0_ml_blayer_0_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm0/verilog/nic400_bm0_ml_build_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm0/verilog/nic400_bm0_ml_map_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_0_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_1_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_2_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm0/verilog/nic400_bm0_rd_ss_tt_s0_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml0_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml1_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml2_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml0_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml1_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml2_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm0/verilog/nic400_bm0_wr_ss_tt_s0_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm1/verilog/nic400_bm1_add_arb_ml0_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm1/verilog/nic400_bm1_add_arb_ml1_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm1/verilog/nic400_bm1_add_arb_ml2_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm1/verilog/nic400_bm1_add_arb_ml3_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm1/verilog/nic400_bm1_add_arb_ml4_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm1/verilog/nic400_bm1_add_sel_ml0_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm1/verilog/nic400_bm1_add_sel_ml1_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm1/verilog/nic400_bm1_add_sel_ml2_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm1/verilog/nic400_bm1_add_sel_ml3_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm1/verilog/nic400_bm1_add_sel_ml4_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm1/verilog/nic400_bm1_lrg_arb_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm1/verilog/nic400_bm1_maskcntl_ml0_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm1/verilog/nic400_bm1_maskcntl_ml1_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm1/verilog/nic400_bm1_maskcntl_ml2_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm1/verilog/nic400_bm1_maskcntl_ml3_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm1/verilog/nic400_bm1_maskcntl_ml4_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm1/verilog/nic400_bm1_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm1/verilog/nic400_bm1_ml_blayer_0_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm1/verilog/nic400_bm1_ml_blayer_1_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm1/verilog/nic400_bm1_ml_blayer_2_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm1/verilog/nic400_bm1_ml_build_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm1/verilog/nic400_bm1_ml_map_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm1/verilog/nic400_bm1_ml_mlayer_0_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm1/verilog/nic400_bm1_ml_mlayer_1_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm1/verilog/nic400_bm1_ml_mlayer_2_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm1/verilog/nic400_bm1_ml_mlayer_3_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm1/verilog/nic400_bm1_ml_mlayer_4_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm1/verilog/nic400_bm1_qv_cmp_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm1/verilog/nic400_bm1_rd_spi_tt_s2_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm1/verilog/nic400_bm1_rd_ss_tt_s0_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm1/verilog/nic400_bm1_rd_ss_tt_s1_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm1/verilog/nic400_bm1_rd_wr_arb_0_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm1/verilog/nic400_bm1_rd_wr_arb_1_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm1/verilog/nic400_bm1_rd_wr_arb_2_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm1/verilog/nic400_bm1_ret_sel_ml0_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm1/verilog/nic400_bm1_ret_sel_ml1_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm1/verilog/nic400_bm1_ret_sel_ml2_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm1/verilog/nic400_bm1_ret_sel_ml3_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm1/verilog/nic400_bm1_ret_sel_ml4_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm1/verilog/nic400_bm1_wr_sel_ml0_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm1/verilog/nic400_bm1_wr_sel_ml1_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm1/verilog/nic400_bm1_wr_sel_ml2_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm1/verilog/nic400_bm1_wr_sel_ml3_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm1/verilog/nic400_bm1_wr_sel_ml4_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm1/verilog/nic400_bm1_wr_spi_tt_s2_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm1/verilog/nic400_bm1_wr_ss_tt_s0_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/busmatrix_bm1/verilog/nic400_bm1_wr_ss_tt_s1_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/cdc_blocks/verilog/nic400_cd_exp_cdc_comb_or_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/cdc_blocks/verilog/nic400_cd_sys_cdc_comb_or_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/cdc_blocks/verilog/nic400_cdc_bypass_sync_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/cdc_blocks/verilog/nic400_cdc_capt_nosync_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/cdc_blocks/verilog/nic400_cdc_capt_sync_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/cdc_blocks/verilog/nic400_cdc_comb_and2_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/cdc_blocks/verilog/nic400_cdc_comb_mux2_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/cdc_blocks/verilog/nic400_cdc_comb_or2_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/cdc_blocks/verilog/nic400_cdc_comb_or3_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/cdc_blocks/verilog/nic400_cdc_corrupt_gry_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/cdc_blocks/verilog/nic400_cdc_launch_gry_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/cdc_blocks/verilog/nic400_cdc_random_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/default_slave_ds_3/verilog/nic400_default_slave_ds_3_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/default_slave_ds_4/verilog/nic400_default_slave_ds_4_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/dmu_exp/verilog/nic400_dmu_exp_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/dmu_sys/verilog/nic400_dmu_sys_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_ar_fifo_rd_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_ar_fifo_sync_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_ar_fifo_wr_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_ar_fifo_wr_mux2_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_ar_fifo_wr_mux_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_aw_fifo_rd_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_aw_fifo_sync_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_aw_fifo_wr_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_aw_fifo_wr_mux2_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_aw_fifo_wr_mux_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_b_fifo_rd_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_b_fifo_sync_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_b_fifo_wr_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_b_fifo_wr_mux2_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_b_fifo_wr_mux_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_chan_slice_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_downsize_rd_addr_fmt_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_downsize_rd_cam_slice_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_downsize_rd_chan_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_downsize_rd_cntrl_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_downsize_resp_cam_slice_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_downsize_wr_addr_fmt_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_downsize_wr_cntrl_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_downsize_wr_merge_buffer_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_downsize_wr_mux_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_downsize_wr_resp_block_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_maskcntl_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_master_domain_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_r_fifo_rd_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_r_fifo_sync_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_r_fifo_wr_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_r_fifo_wr_mux2_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_r_fifo_wr_mux_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_slave_domain_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_w_fifo_rd_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_w_fifo_sync_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_w_fifo_wr_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_w_fifo_wr_mux2_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_w_fifo_wr_mux_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_a_fifo_rd_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_a_fifo_sync_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_a_fifo_wr_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_a_fifo_wr_mux2_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_a_fifo_wr_mux_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_axi_to_itb_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_chan_slice_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_d_fifo_rd_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_d_fifo_sync_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_d_fifo_wr_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_d_fifo_wr_mux2_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_d_fifo_wr_mux_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_downsize_itb_addr_fmt_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_downsize_rd_cam_slice_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_downsize_rd_chan_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_downsize_rd_cntrl_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_downsize_resp_cam_slice_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_downsize_wr_cntrl_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_downsize_wr_merge_buffer_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_downsize_wr_mux_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_downsize_wr_resp_block_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_itb_to_axi_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_itb_trans_counter_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_master_domain_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_slave_domain_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_w_fifo_rd_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_w_fifo_sync_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_w_fifo_wr_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_w_fifo_wr_mux2_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_w_fifo_wr_mux_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_ib2/verilog/nic400_ib_ib2_ar_fifo_rd_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_ib2/verilog/nic400_ib_ib2_ar_fifo_sync_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_ib2/verilog/nic400_ib_ib2_ar_fifo_wr_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_ib2/verilog/nic400_ib_ib2_ar_fifo_wr_mux2_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_ib2/verilog/nic400_ib_ib2_ar_fifo_wr_mux_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_ib2/verilog/nic400_ib_ib2_aw_fifo_rd_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_ib2/verilog/nic400_ib_ib2_aw_fifo_sync_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_ib2/verilog/nic400_ib_ib2_aw_fifo_wr_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_ib2/verilog/nic400_ib_ib2_aw_fifo_wr_mux2_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_ib2/verilog/nic400_ib_ib2_aw_fifo_wr_mux_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_ib2/verilog/nic400_ib_ib2_b_fifo_rd_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_ib2/verilog/nic400_ib_ib2_b_fifo_sync_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_ib2/verilog/nic400_ib_ib2_b_fifo_wr_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_ib2/verilog/nic400_ib_ib2_b_fifo_wr_mux2_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_ib2/verilog/nic400_ib_ib2_b_fifo_wr_mux_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_ib2/verilog/nic400_ib_ib2_chan_slice_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_ib2/verilog/nic400_ib_ib2_maskcntl_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_ib2/verilog/nic400_ib_ib2_master_domain_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_ib2/verilog/nic400_ib_ib2_r_fifo_rd_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_ib2/verilog/nic400_ib_ib2_r_fifo_sync_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_ib2/verilog/nic400_ib_ib2_r_fifo_wr_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_ib2/verilog/nic400_ib_ib2_r_fifo_wr_mux2_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_ib2/verilog/nic400_ib_ib2_r_fifo_wr_mux_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_ib2/verilog/nic400_ib_ib2_slave_domain_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_ib2/verilog/nic400_ib_ib2_upsize_rd_addr_fmt_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_ib2/verilog/nic400_ib_ib2_upsize_rd_cam_slice_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_ib2/verilog/nic400_ib_ib2_upsize_rd_chan_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_ib2/verilog/nic400_ib_ib2_upsize_resp_cam_slice_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_ib2/verilog/nic400_ib_ib2_upsize_wr_addr_fmt_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_ib2/verilog/nic400_ib_ib2_upsize_wr_cntrl_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_ib2/verilog/nic400_ib_ib2_upsize_wr_merge_buffer_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_ib2/verilog/nic400_ib_ib2_upsize_wr_resp_block_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_ib2/verilog/nic400_ib_ib2_w_fifo_rd_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_ib2/verilog/nic400_ib_ib2_w_fifo_sync_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_ib2/verilog/nic400_ib_ib2_w_fifo_wr_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_ib2/verilog/nic400_ib_ib2_w_fifo_wr_mux2_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/ib_ib2/verilog/nic400_ib_ib2_w_fifo_wr_mux_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/nic400/verilog/nic400_cd_exp_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/nic400/verilog/nic400_cd_sys_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/reg_slice/verilog/nic400_ax4_reg_slice_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/reg_slice/verilog/nic400_buf_reg_slice_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/reg_slice/verilog/nic400_ful_regd_slice_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/reg_slice/verilog/nic400_fwd_regd_slice_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/reg_slice/verilog/nic400_rd_reg_slice_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/reg_slice/verilog/nic400_reg_slice_axi_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/reg_slice/verilog/nic400_rev_regd_slice_expansion_subsystem.v
+VERILOG_SOURCES += $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/logical/nic400_expansion_subsystem/logical/nic400_expansion_subsystem/reg_slice/verilog/nic400_wr_reg_slice_expansion_subsystem.v
diff --git a/flist/millisoc_expansion_cocotb.flist b/flist/millisoc_expansion_cocotb.flist
deleted file mode 100644
index 91e66c0e43df80591515581342964d84eff6983e..0000000000000000000000000000000000000000
--- a/flist/millisoc_expansion_cocotb.flist
+++ /dev/null
@@ -1,445 +0,0 @@
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/expansion_region/verilog/expansion_region.v
-
-#SRAM files
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SRAM/verilog/SRAM_wrapper.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SRAM/verilog/SRAM.v
-#BP301 SRAM controller files
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SMC/logical/models/cells/generic/sie300_arm_and2.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SMC/logical/models/cells/generic/sie300_arm_or2.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SMC/logical/models/cells/generic/sie300_arm_sdff2yrpq.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SMC/logical/models/cells/generic/sie300_arm_xor2.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SMC/logical/shared/verilog/sie300_or_tree/verilog/sie300_or_tree.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SMC/logical/shared/verilog/sie300_sync/verilog/sie300_sync.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_addr_dec.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_arb.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_arq.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_awq.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_axi_mux.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_bq.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_clamp.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_eam.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_fifo.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_fifo_core.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_lpi_ctrl.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_one_hot.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_rbeat.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_resp_gen.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_rq.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_wbeat.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_wq.sv
-
-#DMA350 files
-
-EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/shared/verilog
-
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_gen_regmap_sldma350_pkg.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_apb_regmap_conv_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_reg_field_ro_ro_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_reg_field_rw_ro_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_reg_field_rw_w1c_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_reg_field_rw_w1s_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_reg_field_rw_rw_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_gen_coreif_dmach_sldma350_pkg.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_gen_addrmap_dmach_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_interface_sldma350_pkg.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_flop_en/verilog/ada_flop_en.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_or_tree/verilog/ada_or_tree.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_gen_regif_dmainfo_sldma350_pkg.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/models/cells/generic/ada_arm_flop.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/models/cells/generic/ada_arm_sync.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/models/cells/generic/ada_arm_mux2.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/models/cells/generic/ada_arm_or.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/models/cells/generic/ada_arm_idbit_v1.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_ecorevnum.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_top_sldma350/verilog/ada_top_sldma350.sv
-
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_gen_regif_dmach_0_sldma350_pkg.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_gen_regif_dmach_0_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_gen_regmap_dmach_0_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_gen_fields_coreif_dmach_0_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_gen_coreif_res_dmach_0_sldma350_pkg.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_sldma350_pkg.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_ctrl_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_1d_wr_ctrl_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_2d_wr_ctrl_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_1d_rd_ctrl_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_2d_rd_ctrl_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_fifo_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_cmdlink_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_axi_rd_if_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_axi_wr_if_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_axi_stop_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_reg_bank_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_inc_gen_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_stream_wrapper_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_stream_slave_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_stream_master_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_stream_bypass_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_trig_in_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_trig_out_sldma350.sv
-
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_gen_regif_dmach_1_sldma350_pkg.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_gen_regif_dmach_1_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_gen_regmap_dmach_1_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_gen_fields_coreif_dmach_1_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_gen_coreif_res_dmach_1_sldma350_pkg.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_sldma350_pkg.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_ctrl_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_1d_wr_ctrl_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_2d_wr_ctrl_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_1d_rd_ctrl_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_2d_rd_ctrl_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_fifo_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_cmdlink_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_axi_rd_if_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_axi_wr_if_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_axi_stop_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_reg_bank_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_inc_gen_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_stream_wrapper_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_stream_slave_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_stream_master_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_stream_bypass_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_trig_in_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_trig_out_sldma350.sv
-
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_gen_regif_dmach_2_sldma350_pkg.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_gen_regif_dmach_2_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_gen_regmap_dmach_2_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_gen_fields_coreif_dmach_2_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_gen_coreif_res_dmach_2_sldma350_pkg.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_sldma350_pkg.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_ctrl_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_1d_wr_ctrl_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_1d_rd_ctrl_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_fifo_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_cmdlink_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_axi_rd_if_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_axi_wr_if_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_axi_stop_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_reg_bank_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_trig_in_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_trig_out_sldma350.sv
-
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_gen_regif_dmach_3_sldma350_pkg.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_gen_regif_dmach_3_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_gen_regmap_dmach_3_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_gen_fields_coreif_dmach_3_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_gen_coreif_res_dmach_3_sldma350_pkg.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_sldma350_pkg.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_ctrl_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_1d_wr_ctrl_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_1d_rd_ctrl_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_fifo_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_cmdlink_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_axi_rd_if_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_axi_wr_if_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_axi_stop_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_reg_bank_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_trig_in_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_trig_out_sldma350.sv
-
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_read_switch_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_read_switch_wrapper_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_write_switch_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_write_switch_wrapper_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_arbiter_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_qv_cmp_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_lrg_arb_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_grant_queue_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_full_f2s_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_reverse_s2f_sldma350.sv
-
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_regif_dmainfo_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_regmap_dmainfo_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_fields_coreif_dmainfo_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_addrmap_dmainfo_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_coreif_dmansecctrl_sldma350_pkg.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_regif_dmansecctrl_sldma350_pkg.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_regif_dmansecctrl_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_regmap_dmansecctrl_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_fields_coreif_dmansecctrl_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_addrmap_dmansecctrl_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_ctrl_apb_slave_mux_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_ctrl_dmainfo_reg_bank_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_ctrl_dmansecctrl_reg_bank_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_ctrl_trigmask_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_ctrl_trigin_used_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_ctrl_trigout_used_sldma350.sv
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_ctrl_sldma350.sv
-
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_trigmtx_sldma350/verilog/ada_trigmtx_sldma350.sv
-
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_qctrl_sldma350/verilog/ada_qctrl_sldma350.sv
-
-#NIC400 files
-EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_AXI_EXPANSION/verilog
-EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_AXI_EXP_SRAM_0/verilog
-EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_AXI_EXP_SRAM_1/verilog
-EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_AXI_SYS/verilog
-EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_apb_group0/verilog
-EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_DMA_0/verilog
-EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_DMA_1/verilog
-EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_EXP_SS/verilog
-EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog
-EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog
-EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/cdc_blocks/verilog
-EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/default_slave_ds_3/verilog
-EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/default_slave_ds_4/verilog
-EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/dmu_exp/verilog
-EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/dmu_sys/verilog
-EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog
-EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog
-EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog
-EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/reg_slice/verilog
-
-EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/nic400/verilog
-EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/reg_slice/verilog
-EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/shared/validation/tb_components/Axi4Frm
-EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/shared/validation/tb_components
-EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/shared/validation/tb_components/AxiFrm
-EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/shared/validation/tb_components/AxiFrs
-EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/nic400/verilog/Axi
-EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/nic400/verilog/ApbPC
-EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/nic400/verilog/Apb4PC
-EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/nic400/verilog/AxiPC
-EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/nic400/verilog/Axi4PC
-
-
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/nic400/verilog/nic400_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_AXI_EXPANSION/verilog/nic400_amib_AXI_EXPANSION_chan_slice_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_AXI_EXPANSION/verilog/nic400_amib_AXI_EXPANSION_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_AXI_EXP_SRAM_0/verilog/nic400_amib_AXI_EXP_SRAM_0_chan_slice_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_AXI_EXP_SRAM_0/verilog/nic400_amib_AXI_EXP_SRAM_0_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_AXI_EXP_SRAM_1/verilog/nic400_amib_AXI_EXP_SRAM_1_chan_slice_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_AXI_EXP_SRAM_1/verilog/nic400_amib_AXI_EXP_SRAM_1_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_AXI_SYS/verilog/nic400_amib_AXI_SYS_chan_slice_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_AXI_SYS/verilog/nic400_amib_AXI_SYS_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_apb_group0/verilog/nic400_amib_apb_group0_a_gen_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_apb_group0/verilog/nic400_amib_apb_group0_apb_m_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_apb_group0/verilog/nic400_amib_apb_group0_chan_slice_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_apb_group0/verilog/nic400_amib_apb_group0_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_DMA_0/verilog/nic400_asib_AXI_DMA_0_chan_slice_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_DMA_0/verilog/nic400_asib_AXI_DMA_0_decode_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_DMA_0/verilog/nic400_asib_AXI_DMA_0_maskcntl_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_DMA_0/verilog/nic400_asib_AXI_DMA_0_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_DMA_0/verilog/nic400_asib_AXI_DMA_0_rd_ss_cdas_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_DMA_0/verilog/nic400_asib_AXI_DMA_0_wr_ss_cdas_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_DMA_1/verilog/nic400_asib_AXI_DMA_1_chan_slice_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_DMA_1/verilog/nic400_asib_AXI_DMA_1_decode_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_DMA_1/verilog/nic400_asib_AXI_DMA_1_maskcntl_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_DMA_1/verilog/nic400_asib_AXI_DMA_1_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_DMA_1/verilog/nic400_asib_AXI_DMA_1_rd_ss_cdas_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_DMA_1/verilog/nic400_asib_AXI_DMA_1_wr_ss_cdas_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_EXP_SS/verilog/nic400_asib_AXI_EXP_SS_chan_slice_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_EXP_SS/verilog/nic400_asib_AXI_EXP_SS_decode_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_EXP_SS/verilog/nic400_asib_AXI_EXP_SS_maskcntl_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_EXP_SS/verilog/nic400_asib_AXI_EXP_SS_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_EXP_SS/verilog/nic400_asib_AXI_EXP_SS_rd_ss_cdas_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_EXP_SS/verilog/nic400_asib_AXI_EXP_SS_wr_ss_cdas_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml0_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml1_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml2_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml0_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml1_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml2_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_ml_blayer_0_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_ml_build_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_ml_map_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_0_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_1_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_2_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_rd_ss_tt_s0_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml0_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml1_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml2_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml0_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml1_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml2_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_wr_ss_tt_s0_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_add_arb_ml0_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_add_arb_ml1_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_add_arb_ml2_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_add_arb_ml3_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_add_arb_ml4_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_add_sel_ml0_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_add_sel_ml1_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_add_sel_ml2_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_add_sel_ml3_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_add_sel_ml4_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_lrg_arb_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_maskcntl_ml0_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_maskcntl_ml1_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_maskcntl_ml2_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_maskcntl_ml3_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_maskcntl_ml4_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_ml_blayer_0_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_ml_blayer_1_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_ml_blayer_2_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_ml_build_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_ml_map_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_ml_mlayer_0_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_ml_mlayer_1_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_ml_mlayer_2_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_ml_mlayer_3_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_ml_mlayer_4_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_qv_cmp_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_rd_spi_tt_s2_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_rd_ss_tt_s0_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_rd_ss_tt_s1_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_rd_wr_arb_0_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_rd_wr_arb_1_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_rd_wr_arb_2_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_ret_sel_ml0_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_ret_sel_ml1_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_ret_sel_ml2_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_ret_sel_ml3_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_ret_sel_ml4_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_wr_sel_ml0_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_wr_sel_ml1_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_wr_sel_ml2_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_wr_sel_ml3_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_wr_sel_ml4_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_wr_spi_tt_s2_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_wr_ss_tt_s0_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_wr_ss_tt_s1_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/cdc_blocks/verilog/nic400_cd_exp_cdc_comb_or_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/cdc_blocks/verilog/nic400_cd_sys_cdc_comb_or_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/cdc_blocks/verilog/nic400_cdc_bypass_sync_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/cdc_blocks/verilog/nic400_cdc_capt_nosync_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/cdc_blocks/verilog/nic400_cdc_capt_sync_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/cdc_blocks/verilog/nic400_cdc_comb_and2_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/cdc_blocks/verilog/nic400_cdc_comb_mux2_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/cdc_blocks/verilog/nic400_cdc_comb_or2_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/cdc_blocks/verilog/nic400_cdc_comb_or3_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/cdc_blocks/verilog/nic400_cdc_corrupt_gry_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/cdc_blocks/verilog/nic400_cdc_launch_gry_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/cdc_blocks/verilog/nic400_cdc_random_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/default_slave_ds_3/verilog/nic400_default_slave_ds_3_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/default_slave_ds_4/verilog/nic400_default_slave_ds_4_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/dmu_exp/verilog/nic400_dmu_exp_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/dmu_sys/verilog/nic400_dmu_sys_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_ar_fifo_rd_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_ar_fifo_sync_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_ar_fifo_wr_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_ar_fifo_wr_mux2_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_ar_fifo_wr_mux_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_aw_fifo_rd_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_aw_fifo_sync_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_aw_fifo_wr_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_aw_fifo_wr_mux2_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_aw_fifo_wr_mux_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_b_fifo_rd_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_b_fifo_sync_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_b_fifo_wr_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_b_fifo_wr_mux2_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_b_fifo_wr_mux_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_chan_slice_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_downsize_rd_addr_fmt_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_downsize_rd_cam_slice_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_downsize_rd_chan_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_downsize_rd_cntrl_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_downsize_resp_cam_slice_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_downsize_wr_addr_fmt_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_downsize_wr_cntrl_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_downsize_wr_merge_buffer_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_downsize_wr_mux_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_downsize_wr_resp_block_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_maskcntl_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_master_domain_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_r_fifo_rd_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_r_fifo_sync_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_r_fifo_wr_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_r_fifo_wr_mux2_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_r_fifo_wr_mux_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_slave_domain_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_w_fifo_rd_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_w_fifo_sync_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_w_fifo_wr_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_w_fifo_wr_mux2_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_w_fifo_wr_mux_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_a_fifo_rd_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_a_fifo_sync_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_a_fifo_wr_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_a_fifo_wr_mux2_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_a_fifo_wr_mux_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_axi_to_itb_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_chan_slice_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_d_fifo_rd_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_d_fifo_sync_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_d_fifo_wr_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_d_fifo_wr_mux2_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_d_fifo_wr_mux_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_downsize_itb_addr_fmt_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_downsize_rd_cam_slice_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_downsize_rd_chan_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_downsize_rd_cntrl_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_downsize_resp_cam_slice_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_downsize_wr_cntrl_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_downsize_wr_merge_buffer_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_downsize_wr_mux_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_downsize_wr_resp_block_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_itb_to_axi_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_itb_trans_counter_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_master_domain_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_slave_domain_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_w_fifo_rd_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_w_fifo_sync_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_w_fifo_wr_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_w_fifo_wr_mux2_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_w_fifo_wr_mux_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_ar_fifo_rd_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_ar_fifo_sync_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_ar_fifo_wr_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_ar_fifo_wr_mux2_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_ar_fifo_wr_mux_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_aw_fifo_rd_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_aw_fifo_sync_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_aw_fifo_wr_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_aw_fifo_wr_mux2_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_aw_fifo_wr_mux_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_b_fifo_rd_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_b_fifo_sync_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_b_fifo_wr_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_b_fifo_wr_mux2_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_b_fifo_wr_mux_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_chan_slice_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_maskcntl_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_master_domain_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_r_fifo_rd_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_r_fifo_sync_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_r_fifo_wr_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_r_fifo_wr_mux2_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_r_fifo_wr_mux_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_slave_domain_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_upsize_rd_addr_fmt_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_upsize_rd_cam_slice_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_upsize_rd_chan_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_upsize_resp_cam_slice_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_upsize_wr_addr_fmt_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_upsize_wr_cntrl_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_upsize_wr_merge_buffer_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_upsize_wr_resp_block_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_w_fifo_rd_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_w_fifo_sync_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_w_fifo_wr_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_w_fifo_wr_mux2_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_w_fifo_wr_mux_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/nic400/verilog/nic400_cd_exp_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/nic400/verilog/nic400_cd_sys_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/reg_slice/verilog/nic400_ax4_reg_slice_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/reg_slice/verilog/nic400_buf_reg_slice_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/reg_slice/verilog/nic400_ful_regd_slice_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/reg_slice/verilog/nic400_fwd_regd_slice_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/reg_slice/verilog/nic400_rd_reg_slice_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/reg_slice/verilog/nic400_reg_slice_axi_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/reg_slice/verilog/nic400_rev_regd_slice_millisoc_expansion.v
-VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/reg_slice/verilog/nic400_wr_reg_slice_millisoc_expansion.v
diff --git a/flows/makefile.simulate b/flows/makefile.simulate
index fe7c52c87065fa1ab391666444ec8983792a148c..91d57772019f0cd08a20e7ddc176495b8a7353ba 100644
--- a/flows/makefile.simulate
+++ b/flows/makefile.simulate
@@ -1,5 +1,5 @@
 #-----------------------------------------------------------------------------
-# MilliSoC expansion Simulation Makefile 
+# Expansion subsystem Simulation Makefile 
 # A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
 #
 # Contributors
diff --git a/logical/SRAM/verilog/SRAM_wrapper.v b/logical/SRAM/verilog/SRAM_wrapper.v
index d7b400eaf58deb6c804ab72e4f3324016cace59c..fce6c564d2adafb2e3b8316d261cb5203c0ff215 100644
--- a/logical/SRAM/verilog/SRAM_wrapper.v
+++ b/logical/SRAM/verilog/SRAM_wrapper.v
@@ -1,5 +1,5 @@
 //-----------------------------------------------------------------------------
-// MilliSoC SRAM Wrapper
+// Expansion Subsystem SRAM Wrapper
 // A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
 //
 // Contributors
@@ -9,7 +9,7 @@
 // Copyright � 2021-4, SoC Labs (www.soclabs.org)
 //-----------------------------------------------------------------------------
 // Modules instantiated:
-//  sie300_axi5_sram_ctrl_millisoc_exp
+//  sie300_axi5_sram_ctrl_expansion_subsystem
 //  SRAM
 
 module SRAM_wrapper(
@@ -81,7 +81,7 @@ wire [127:0]    memq;
 wire            memcen;
 wire [15:0]     memwen;
 
-sie300_axi5_sram_ctrl_millisoc_exp u_SMC(
+sie300_axi5_sram_ctrl_expansion_subsystem u_SMC(
     .aclk(ACLK),
     .aresetn(ARESETn),
     .awvalid_s(AWVALID),
diff --git a/logical/expansion_region/verilog/expansion_region.v b/logical/expansion_region/verilog/expansion_region.v
index 38991313a5e5b99de5627f91714d2d9f5532b353..67930a5d0fa34e737d181dbf0ed20ddc09873d4a 100644
--- a/logical/expansion_region/verilog/expansion_region.v
+++ b/logical/expansion_region/verilog/expansion_region.v
@@ -1,5 +1,5 @@
 //-----------------------------------------------------------------------------
-// MilliSoC Expansion Region
+// Expansion Subsystem Expansion Region
 // A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
 //
 // Contributors
diff --git a/logical/top_millisoc_expansion/verilog/millisoc_expansion_wrapper.v b/logical/top_expansion_subsystem/verilog/expansion_subsystem_wrapper.v
similarity index 99%
rename from logical/top_millisoc_expansion/verilog/millisoc_expansion_wrapper.v
rename to logical/top_expansion_subsystem/verilog/expansion_subsystem_wrapper.v
index 45bd3d70a6c5d99a962f8ed7b0710b04ea9683ec..e2798869d6fa1c4e281475e645857222f030ab95 100644
--- a/logical/top_millisoc_expansion/verilog/millisoc_expansion_wrapper.v
+++ b/logical/top_expansion_subsystem/verilog/expansion_subsystem_wrapper.v
@@ -1,5 +1,5 @@
 //-----------------------------------------------------------------------------
-// MilliSoC Expansion Wrapper
+// Expansion Subsystem Wrapper
 // A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
 //
 // Contributors
@@ -12,11 +12,11 @@
 //  ada_top_sldma350
 //  expansion_region
 //  SRAM_wrapper
-//  nic400_millisoc_expansion
+//  nic400_expansion_subsystem
 `timescale 1ns/1ps
 
 
-module millisoc_expansion_wrapper(
+module expansion_subsystem_wrapper(
     input wire          sys_clk,
     input wire          resetn,
     input wire          exp_clk,
@@ -649,9 +649,9 @@ SRAM_wrapper u_EXP_SRAM_1(
 );
 
 
-// NIC 400 Bus for millisoc expansion instatiation
+// NIC 400 Bus for expansion subsystem instatiation
 
-nic400_millisoc_expansion u_nic400_millisoc_expansion(
+nic400_expansion_subsystem u_nic400_expansion_subsystem(
   .AWID_AXI_EXPANSION(AWID_AXI_EXPANSION),
   .AWADDR_AXI_EXPANSION(AWADDR_AXI_EXPANSION),
   .AWLEN_AXI_EXPANSION(AWLEN_AXI_EXPANSION),
diff --git a/makefile b/makefile
index 1cf87a854ee24329bfbb0d7d30350681b377e59b..1c76bfcebf512c965e0c8e59e73e8ca45c6be94c 100644
--- a/makefile
+++ b/makefile
@@ -1,5 +1,5 @@
 #-----------------------------------------------------------------------------
-# milliSoC Expansion region Top-Level Makefile 
+# Expansion subsystem  Top-Level Makefile 
 # - Includes other Makefiles in flow directory
 # A joint work commissioned on behalf of SoC Labs, under Arm Academic Access l
 #
@@ -17,11 +17,11 @@ build_dma350:
 build_sie300_sram_ctrl:
 	@$(SIE300_IP_LOGICAL_DIR)/generate --config ./socrates/BP301_SRAM/config/SRAM_ctrl.yaml --output ./logical/SMC
 build_nic400:
-	socrates_cli --project millisoc_expansion_tech -data ../ --flow build.configured.component configuredComponentName=nic400_millisoc_expansion
+	socrates_cli --project expansion_subsystem_tech -data ../ --flow build.configured.component configuredComponentName=nic400_expansion_subsystem
 build_ip: build_dma350 build_sie300_sram_ctrl build_nic400
 
 make_project:
-	socrates_cli --project millisoc_expansion_tech -data ../ --flow AddNewProject
+	socrates_cli --project expansion_subsystem_tech -data ../ --flow AddNewProject
 
 first_time_setup: make_project build_ip
 
@@ -29,6 +29,6 @@ all: first_time_setup
 
 clean:
 	@rm -rf ./logical/dma350
-	@rm -rf ./logical/nic400_millisoc_expansion
+	@rm -rf ./logical/nic400_expansion_subsystem
 	@rm -rf ./logical/shared/ipxact
 	@rm -rf ./logical/SMC
diff --git a/set_exp_env.sh b/set_exp_env.sh
index 5ded36cf09e07df098c81071e6e0ec1a2a39836b..1686e9f0d61f4047448f8e9ebcd3539256a88a2e 100644
--- a/set_exp_env.sh
+++ b/set_exp_env.sh
@@ -9,4 +9,4 @@
 # Copyright � 2021-4, SoC Labs (www.soclabs.org)
 #-----------------------------------------------------------------------------
 
-export SOCLABS_MILLISOC_EXP_TECH_DIR=$(pwd)
\ No newline at end of file
+export SOCLABS_EXP_SUBSYSTEM_TECH_DIR=$(pwd)
\ No newline at end of file
diff --git a/socrates/BP301_SRAM/config/SRAM_ctrl.yaml b/socrates/BP301_SRAM/config/SRAM_ctrl.yaml
index d72c29c6cfe32a2b372cad611a58a5e9b4c1ba50..5ab38ccc944d4cfcd5a33268a780da1e2141764d 100644
--- a/socrates/BP301_SRAM/config/SRAM_ctrl.yaml
+++ b/socrates/BP301_SRAM/config/SRAM_ctrl.yaml
@@ -42,7 +42,7 @@ COMPONENT: sie300_axi5_sram_ctrl
 #     Each unifiqued element and top is suffixed with
 #     _${CONFIG_NAME}
 #
-CONFIG_NAME: millisoc_exp
+CONFIG_NAME: expansion_subsystem
 
 
 #
diff --git a/socrates/nic400_millisoc_expansion/nic400_millisoc_expansion.xml b/socrates/nic400_expansion_subsystem/nic400_expansion_subsystem.xml
similarity index 99%
rename from socrates/nic400_millisoc_expansion/nic400_millisoc_expansion.xml
rename to socrates/nic400_expansion_subsystem/nic400_expansion_subsystem.xml
index 765d1efd7a71fd8181885e71ab2e7629c848557b..aed10fe4217203093f03434c71bf7220838e369c 100644
--- a/socrates/nic400_millisoc_expansion/nic400_millisoc_expansion.xml
+++ b/socrates/nic400_expansion_subsystem/nic400_expansion_subsystem.xml
@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <ConfiguredComponent>
-  <Name>nic400_millisoc_expansion</Name>
-  <Suffix>millisoc_expansion</Suffix>
+  <Name>nic400_expansion_subsystem</Name>
+  <Suffix>expansion_subsystem</Suffix>
   <ConfigurableComponentRef>
     <Vendor>arm.com</Vendor>
     <Library>CoreLink</Library>
diff --git a/verif/cocotb/millisoc_expansion_tests.py b/verif/cocotb/expansion_subsystem_tests.py
similarity index 99%
rename from verif/cocotb/millisoc_expansion_tests.py
rename to verif/cocotb/expansion_subsystem_tests.py
index c78fbdaf60f057a4db21858ccbcd053bfe63ef9c..d1e25e521ff017b84d5eef7c8d0e3146ec4afce7 100644
--- a/verif/cocotb/millisoc_expansion_tests.py
+++ b/verif/cocotb/expansion_subsystem_tests.py
@@ -1,5 +1,5 @@
 #-----------------------------------------------------------------------------
-# MilliSoC Expansion cocoTB script
+# Expansion Subsystem cocoTB script
 # A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
 #
 # Contributors
diff --git a/verif/cocotb/makefile b/verif/cocotb/makefile
index ff3a8a87629bf0acef664fc26d39fb2b25648bc6..5944378d5bbb6ca12a27d9cf137c0907fa70ac47 100644
--- a/verif/cocotb/makefile
+++ b/verif/cocotb/makefile
@@ -27,11 +27,11 @@ GUI ?= 0
 COCOTB_HDL_TIMEUNIT = 1ns
 COCOTB_HDL_TIMEPRECISION = 1ns
 
-DUT      = millisoc_expansion_wrapper
-TOPLEVEL = millisoc_expansion_wrapper
-MODULE   = millisoc_expansion_tests
+DUT      = expansion_subsystem_wrapper
+TOPLEVEL = expansion_subsystem_wrapper
+MODULE   = expansion_subsystem_tests
 
-VERILOG_SOURCES += ../../logical/top_millisoc_expansion/verilog/millisoc_expansion_wrapper.v
+VERILOG_SOURCES += ../../logical/top_expansion_subsystem/verilog/expansion_subsystem_wrapper.v
 
 
 ifeq ($(SIM), icarus)
@@ -52,7 +52,7 @@ else ifeq ($(SIM), verilator)
 		COMPILE_ARGS += --trace-fst
 	endif
 endif
-include $(SOCLABS_MILLISOC_EXP_DIR)/flist/millisoc_expansion_cocotb.flist
+include $(SOCLABS_EXP_SUBSYSTEM_TECH_DIR)/flist/expansion_subsystem_cocotb.flist
 include $(shell cocotb-config --makefiles)/Makefile.sim
 
 iverilog_dump.v:
diff --git a/verif/testbench/logical/expansion_subsystem_tb.v b/verif/testbench/logical/expansion_subsystem_tb.v
new file mode 100644
index 0000000000000000000000000000000000000000..edc0204c8bae38f31c7a553ad2f3a589f66e3d65
--- /dev/null
+++ b/verif/testbench/logical/expansion_subsystem_tb.v
@@ -0,0 +1,11 @@
+
+module expansion_subsystem_tb;
+
+
+
+
+
+
+
+
+endmodule
\ No newline at end of file
diff --git a/verif/testbench/logical/millisoc_expansion_tb.v b/verif/testbench/logical/millisoc_expansion_tb.v
deleted file mode 100644
index 6f3cb9778946555cf26ca50816e59e3c5e06e195..0000000000000000000000000000000000000000
--- a/verif/testbench/logical/millisoc_expansion_tb.v
+++ /dev/null
@@ -1,11 +0,0 @@
-
-module millisoc_expansion_tb;
-
-
-
-
-
-
-
-
-endmodule
\ No newline at end of file