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clk_ctrl.v 2.44 KiB
module clk_ctrl (
input wire SYSCLK,
input wire NRST,
input wire EXPCLK,
input wire EXP_NRST,
output wire CSYSREQ_CD_sys,
input wire CSYSACK_CD_sys,
input wire CACTIVE_CD_sys,
output wire CSYSREQ_CD_exp,
input wire CSYSACK_CD_exp,
input wire CACTIVE_CD_exp
);
parameter IDLE=2'b00, REQ=2'b01, ACK=2'b10, ACT=2'b11;
reg [1:0] state_sys;
reg [1:0] state_sys_next;
reg [1:0] state_exp;
reg [1:0] state_exp_next;
reg CSYSREQ_CD_sys_reg;
reg SYS_ACT;
reg CSYSREQ_CD_exp_reg;
reg EXP_ACT;
always @(posedge SYSCLK or negedge NRST) begin
if (!NRST) begin
state_sys <= IDLE;
CSYSREQ_CD_sys_reg <= 0;
SYS_ACT<=0;
end
else
state_sys <= state_sys_next;
end
always @(*) begin
state_sys_next = state_sys;
case(state_sys)
IDLE : begin
if(!SYS_ACT)
state_sys_next = REQ;
end
REQ: begin
CSYSREQ_CD_sys_reg = 1;
state_sys_next = ACK;
end
ACK: begin
if(CSYSACK_CD_sys) begin
$display("CLK CTRL: System clock enable acknowledged");
state_sys_next = ACT;
end
end
ACT: begin
if(CACTIVE_CD_sys) begin
$display("CLK CTRL: System clock active");
SYS_ACT = 1;
state_sys_next = IDLE;
end
end
endcase
end
assign CSYSREQ_CD_sys = CSYSREQ_CD_sys_reg;
always @(posedge EXPCLK or negedge EXP_NRST) begin
if (!EXP_NRST) begin
state_exp <= IDLE;
CSYSREQ_CD_exp_reg <= 0;
EXP_ACT<=0;
end
else
state_exp <= state_exp_next;
end
always @(*) begin
state_exp_next = state_exp;
case(state_exp)
IDLE : begin
if(!EXP_ACT)
state_exp_next = REQ;
end
REQ: begin
CSYSREQ_CD_exp_reg = 1;
state_exp_next = ACK;
end
ACK: begin
if(CSYSACK_CD_exp) begin
$display("CLK CTRL: Expansion clock enable acknowledged");
state_exp_next = ACT;
end
end
ACT: begin
if(CACTIVE_CD_exp) begin
$display("CLK CTRL: Expansion clock active");
SYS_ACT = 1;
state_exp_next = IDLE;
end
end
endcase
end
assign CSYSREQ_CD_exp = CSYSREQ_CD_exp_reg;
endmodule