From f6160613f2d685f162fb25f60d5f4f95e87aeb17 Mon Sep 17 00:00:00 2001 From: dwf1m12 <d.w.flynn@soton.ac.uk> Date: Tue, 11 Jul 2023 12:47:43 +0100 Subject: [PATCH] repair Arm AAA IP paths for better vesrion independence --- .../cortex_m0_mcu/verilog/tbench_M0.vc | 90 +++++++++---------- 1 file changed, 45 insertions(+), 45 deletions(-) diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/tbench_M0.vc b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/tbench_M0.vc index bdb78cf..832a3aa 100644 --- a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/tbench_M0.vc +++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/tbench_M0.vc @@ -58,43 +58,43 @@ ../../../../../GLIB/mem/verilog/SROM_Ax32.v // ================= Testbench path =================== --y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_debug_tester/verilog -+incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_debug_tester/verilog +-y ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/cmsdk_debug_tester/verilog ++incdir+../../../../../../arm-AAA-ip/latest/Corstone-101/logical/cmsdk_debug_tester/verilog // ============= MCU Module search path ============= -y ../verilog --y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_timer/verilog --y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog --y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_uart/verilog --y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog --y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_slave_mux/verilog --y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_subsystem/verilog --y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_slave_mux/verilog --y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_master_mux/verilog --y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_default_slave/verilog --y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_gpio/verilog --y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_to_apb/verilog --y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_bitband/verilog --y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_iop_gpio/verilog --y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/clkgate --y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/memories/ --y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_to_sram/verilog --y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_to_flash32/verilog --y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_to_extmem16/verilog -+incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog -+incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog -+incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/memories/ +-y ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/cmsdk_apb_timer/verilog +-y ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog +-y ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/cmsdk_apb_uart/verilog +-y ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog +-y ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/cmsdk_apb_slave_mux/verilog +-y ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/cmsdk_apb_subsystem/verilog +-y ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/cmsdk_ahb_slave_mux/verilog +-y ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/cmsdk_ahb_master_mux/verilog +-y ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/cmsdk_ahb_default_slave/verilog +-y ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/cmsdk_ahb_gpio/verilog +-y ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/cmsdk_ahb_to_apb/verilog +-y ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/cmsdk_ahb_bitband/verilog +-y ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/cmsdk_iop_gpio/verilog +-y ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/models/clkgate +-y ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/models/memories/ +-y ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/cmsdk_ahb_to_sram/verilog +-y ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/cmsdk_ahb_to_flash32/verilog +-y ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/cmsdk_ahb_to_extmem16/verilog ++incdir+../../../../../../arm-AAA-ip/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog ++incdir+../../../../../../arm-AAA-ip/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog ++incdir+../../../../../../arm-AAA-ip/latest/Corstone-101/logical/models/memories/ //// Optional PL230 Micro DMA controller - configure in local ../verilog/pl230_defs.v file /// upgrade to AAA 'rel2' version -+incdir+../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog ++incdir+../../../../../../arm-AAA-ip/latest/DMA-230/logical ../verilog/pl230_defs.v -../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_ahb_ctrl.v -../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_apb_regs.v -../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_dma_data.v -../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_udma.v -../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_undefs.v +../../../../../../arm-AAA-ip/latest/DMA-230/logical/pl230_ahb_ctrl.v +../../../../../../arm-AAA-ip/latest/DMA-230/logical/pl230_apb_regs.v +../../../../../../arm-AAA-ip/latest/DMA-230/logical/pl230_dma_data.v +../../../../../../arm-AAA-ip/latest/DMA-230/logical/pl230_udma.v +../../../../../../arm-AAA-ip/latest/DMA-230/logical/pl230_undefs.v ../../../../../IPLIB/FT1248_streamio_v1_0/ft1248_streamio_v1_0.v ../../../../../IPLIB/ADPcontrol_v1_0/ADPcontrol_v1_0.v @@ -103,22 +103,22 @@ // ============= Cortex-M0 Module search path ============= --y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/cortexm0/verilog --y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/cortexm0_dap/verilog --y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/cortexm0_integration/verilog --y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/models/cells --y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/models/wrappers --y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/ualdis/verilog +-y ../../../../../../arm-AAA-ip/latest/Cortex-M0/logical/cortexm0/verilog +-y ../../../../../../arm-AAA-ip/latest/Cortex-M0/logical/cortexm0_dap/verilog +-y ../../../../../../arm-AAA-ip/latest/Cortex-M0/logical/cortexm0_integration/verilog +-y ../../../../../../arm-AAA-ip/latest/Cortex-M0/logical/models/cells +-y ../../../../../../arm-AAA-ip/latest/Cortex-M0/logical/models/wrappers +-y ../../../../../../arm-AAA-ip/latest/Cortex-M0/logical/ualdis/verilog // ============= Cortex-M0 Include file search path ============= -+incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/cortexm0/verilog -+incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/cortexm0_dap/verilog -+incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/cortexm0_integration/verilog -+incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/models/cells -+incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/models/wrappers -+incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/ualdis/verilog ++incdir+../../../../../../arm-AAA-ip/latest/Cortex-M0/logical/cortexm0/verilog ++incdir+../../../../../../arm-AAA-ip/latest/Cortex-M0/logical/cortexm0_dap/verilog ++incdir+../../../../../../arm-AAA-ip/latest/Cortex-M0/logical/cortexm0_integration/verilog ++incdir+../../../../../../arm-AAA-ip/latest/Cortex-M0/logical/models/cells ++incdir+../../../../../../arm-AAA-ip/latest/Cortex-M0/logical/models/wrappers ++incdir+../../../../../../arm-AAA-ip/latest/Cortex-M0/logical/ualdis/verilog @@ -134,10 +134,10 @@ //+define+ARM_CMSDK_ASSERT_ON // ============= Verification components ============= --y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/protocol_checkers/AhbLitePC/verilog/ -+incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/protocol_checkers/AhbLitePC/verilog/ --y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/protocol_checkers/ApbPC/verilog/ -+incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/protocol_checkers/ApbPC/verilog/ +-y ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/models/protocol_checkers/AhbLitePC/verilog/ ++incdir+../../../../../../arm-AAA-ip/latest/Corstone-101/logical/models/protocol_checkers/AhbLitePC/verilog/ +-y ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/models/protocol_checkers/ApbPC/verilog/ ++incdir+../../../../../../arm-AAA-ip/latest/Corstone-101/logical/models/protocol_checkers/ApbPC/verilog/ ///+incdir+/arm/tools/accellera/ovl/releases/ovl_v2p6_Oct2011/std_ovl ///-y /arm/tools/accellera/ovl/releases/ovl_v2p6_Oct2011/std_ovl -- GitLab