diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/v2html_doc.tgz b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/v2html_doc.tgz
index e7236d68eb0ca524c0b8a7156ea6aac89a0b7efb..9b98f23963cb8beedac84ac3ad9be6606127eca9 100644
Binary files a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/v2html_doc.tgz and b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/v2html_doc.tgz differ
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_chip.v b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_chip.v
index 33e1385c3bb79e7acfb20706b40252d1f4cd70bc..f41f313871770d3d1ef120995ef55a9547f92774 100644
--- a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_chip.v
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_chip.v
@@ -287,20 +287,20 @@ module cmsdk_mcu_chip #(
wire HREADY;
// DMA controller master interface
- wire [31:0] dmac_haddr;
- wire [1:0] dmac_htrans;
- wire [2:0] dmac_hsize;
- wire [2:0] dmac_hburst;
- wire [3:0] dmac_hprot;
- wire dmac_hmastlock;
- wire dmac_hwrite;
- wire [31:0] dmac_hwdata;
- wire [31:0] dmac_hrdata;
- wire dmac_hready;
- wire dmac_hresp;
-
- wire dmac_done;
- wire dmac_err;
+ wire [31:0] ahbx_haddr;
+ wire [1:0] ahbx_htrans;
+ wire [2:0] ahbx_hsize;
+ wire [2:0] ahbx_hburst;
+ wire [3:0] ahbx_hprot;
+ wire ahbx_hmastlock;
+ wire ahbx_hwrite;
+ wire [31:0] ahbx_hwdata;
+ wire [31:0] ahbx_hrdata;
+ wire ahbx_hready;
+ wire ahbx_hresp;
+
+ wire ahbx_done;
+ wire ahbx_err;
wire exp_penable;
wire exp_pwrite;
wire [11:0] exp_paddr;
@@ -637,17 +637,17 @@ assign ADPRESETREQ = adp_gpo8[0];
.gpo8 (adp_gpo8),
.gpi8 (adp_gpi8),
// AHB-Lite Master Interface
- .ahb_hready (dmac_hready),
- .ahb_hresp (dmac_hresp),
- .ahb_hrdata (dmac_hrdata),
- .ahb_htrans (dmac_htrans),
- .ahb_hwrite (dmac_hwrite),
- .ahb_haddr (dmac_haddr),
- .ahb_hsize (dmac_hsize),
- .ahb_hburst (dmac_hburst),
- .ahb_hmastlock (dmac_hmastlock),
- .ahb_hprot (dmac_hprot),
- .ahb_hwdata (dmac_hwdata)
+ .ahb_hready (ahbx_hready),
+ .ahb_hresp (ahbx_hresp),
+ .ahb_hrdata (ahbx_hrdata),
+ .ahb_htrans (ahbx_htrans),
+ .ahb_hwrite (ahbx_hwrite),
+ .ahb_haddr (ahbx_haddr),
+ .ahb_hsize (ahbx_hsize),
+ .ahb_hburst (ahbx_hburst),
+ .ahb_hmastlock (ahbx_hmastlock),
+ .ahb_hprot (ahbx_hprot),
+ .ahb_hwdata (ahbx_hwdata)
);
cmsdk_apb_usrt u_apb_usrt_com (
@@ -728,6 +728,7 @@ assign ADPRESETREQ = adp_gpo8[0];
.RESET_ALL_REGS (RESET_ALL_REGS), // Do not reset all registers
.BOOT_MEM_TYPE (BOOT_MEM_TYPE), // Boot loader memory type
.INCLUDE_DMA (INCLUDE_DMA), // Include DMA feature
+ .DMA_CHANNEL_NUM (DMA_CHANNEL_NUM), // and number of channels
.INCLUDE_BITBAND (INCLUDE_BITBAND), // Include bit band wrapper
.INCLUDE_JTAG (INCLUDE_JTAG), // Include JTAG feature
.BASEADDR_SYSROMTABLE (BASEADDR_SYSROMTABLE) // System ROM Table base address
@@ -837,32 +838,22 @@ assign ADPRESETREQ = adp_gpo8[0];
.p1_outen (p1_out_en),
.p1_altfunc (p1_altfunc),
-
- // DMA Control
- // .dma_req (dma230_tie0),
- // .dma_sreq (dma230_tie0),
- // .dma_waitonreq (dma230_tie0),
- // .dma_stall (1'b0),
- // .dma_active (),
- .dma_done (dmac_done),
- .dma_err (dmac_err),
// AHB-Lite Master Interface
- .dmac_hready (dmac_hready),
- .dmac_hresp (dmac_hresp),
- .dmac_hrdata (dmac_hrdata),
- .dmac_htrans (dmac_htrans),
- .dmac_hwrite (dmac_hwrite),
- .dmac_haddr (dmac_haddr),
- .dmac_hsize (dmac_hsize),
- .dmac_hburst (dmac_hburst),
- .dmac_hmastlock (dmac_hmastlock),
- .dmac_hprot (dmac_hprot),
- .dmac_hwdata (dmac_hwdata),
+ .ahbx_hready (ahbx_hready),
+ .ahbx_hresp (ahbx_hresp),
+ .ahbx_hrdata (ahbx_hrdata),
+ .ahbx_htrans (ahbx_htrans),
+ .ahbx_hwrite (ahbx_hwrite),
+ .ahbx_haddr (ahbx_haddr),
+ .ahbx_hsize (ahbx_hsize),
+ .ahbx_hburst (ahbx_hburst),
+ .ahbx_hmastlock (ahbx_hmastlock),
+ .ahbx_hprot (ahbx_hprot),
+ .ahbx_hwdata (ahbx_hwdata),
// APB Slave Interface
.exp12_psel ( ),
.exp13_psel ( ),
.exp14_psel (exp14_psel),
- .exp15_psel ( ),
.exp_penable (exp_penable),
.exp_pwrite (exp_pwrite),
.exp_paddr (exp_paddr[11:0]),
@@ -876,9 +867,6 @@ assign ADPRESETREQ = adp_gpo8[0];
.exp14_prdata (exp14_prdata),
.exp14_pready (exp14_pready),
.exp14_pslverr (exp14_pslverr),
- .exp15_prdata (32'h00000000),
- .exp15_pready (1'b1),
- .exp15_pslverr (1'b0),
.DFTSE (1'b0)
);
@@ -889,8 +877,8 @@ assign ADPRESETREQ = adp_gpo8[0];
// Otherwise there is only one master (cpu), so AHB system
// clock can be stopped when DMA take place.
-// assign HCLKSYS = (INCLUDE_DMA!=0) ? SCLK : HCLK;
- assign HCLKSYS = SCLK;
+ assign HCLKSYS = (INCLUDE_DMA!=0) ? SCLK : HCLK;
+// assign HCLKSYS = SCLK;
//----------------------------------------
// Flash memory
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_chip_pads.v b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_chip_pads.v
index e9e6cce720b5930d5640c7e630477009d133090e..6ef8930534c7832eeb154bc841934f6bf4d3e2f1 100644
--- a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_chip_pads.v
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_chip_pads.v
@@ -223,6 +223,7 @@ module cmsdk_mcu_chip_pads (
.RAM_MEM_TYPE (RAM_MEM_TYPE), // RAM loader memory type
.INCLUDE_BITBAND (INCLUDE_BITBAND), // Include bit band wrapper
.INCLUDE_DMA (INCLUDE_DMA), // Include DMA feature
+ .DMA_CHANNEL_NUM (DMA_CHANNEL_NUM), // and number of channels
.INCLUDE_JTAG (INCLUDE_JTAG) // Include JTAG feature
)
u_cmsdk_mcu (
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_system.v b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_system.v
index 16f7f9a6e4d37261ef961cbeff9e341bf967d135..67a88f6af72a082c49a91ec644b1c299f1a94066 100644
--- a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_system.v
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_system.v
@@ -174,25 +174,22 @@ module cmsdk_mcu_system #(
output wire [15:0] p1_outen, // GPIO 1 output enables
output wire [15:0] p1_altfunc, // GPIO 1 alternate function (pin mux)
- input wire dma_done,
- input wire dma_err,
// AHB-Lite Master Interface
- output wire dmac_hready,
- output wire dmac_hresp,
- output wire [31:0] dmac_hrdata,
- input wire [ 1:0] dmac_htrans,
- output wire dmac_hwrite,
- input wire [31:0] dmac_haddr,
- input wire [2 :0] dmac_hsize,
- input wire [2 :0] dmac_hburst,
- input wire dmac_hmastlock,
- input wire [3 :0] dmac_hprot,
- input wire [31:0] dmac_hwdata,
+ output wire ahbx_hready,
+ output wire ahbx_hresp,
+ output wire [31:0] ahbx_hrdata,
+ input wire [ 1:0] ahbx_htrans,
+ output wire ahbx_hwrite,
+ input wire [31:0] ahbx_haddr,
+ input wire [2 :0] ahbx_hsize,
+ input wire [2 :0] ahbx_hburst,
+ input wire ahbx_hmastlock,
+ input wire [3 :0] ahbx_hprot,
+ input wire [31:0] ahbx_hwdata,
// APB Slave Interface
output wire exp12_psel,
output wire exp13_psel,
output wire exp14_psel,
- output wire exp15_psel,
output wire exp_penable,
output wire exp_pwrite,
output wire [11:0] exp_paddr,
@@ -206,9 +203,6 @@ module cmsdk_mcu_system #(
input wire [31:0] exp14_prdata,
input wire exp14_pready,
input wire exp14_pslverr,
- input wire [31:0] exp15_prdata,
- input wire exp15_pready,
- input wire exp15_pslverr,
input wire DFTSE); // dummy scan enable port for synthesis
@@ -246,6 +240,27 @@ module cmsdk_mcu_system #(
wire cm_hreadyout;
wire cm_hresp;
+// DMA controller master interface
+ wire [31:0] dmac_haddr;
+ wire [1:0] dmac_htrans;
+ wire [2:0] dmac_hsize;
+ wire [2:0] dmac_hburst;
+ wire [3:0] dmac_hprot;
+ wire dmac_hmastlock;
+ wire dmac_hwrite;
+ wire [31:0] dmac_hwdata;
+ wire [31:0] dmac_hrdata;
+ wire dmac_hready;
+ wire dmac_hreadyout;
+ wire dmac_hresp;
+
+ wire dmac_done;
+ wire dmac_err;
+ wire dmac_psel;
+ wire dmac_pready;
+ wire dmac_pslverr;
+ wire [31:0] dmac_prdata;
+
// System bus
wire sys_hselm; // Note: the sys_hselm signal is for protocol checking only.
wire [31:0] sys_haddr;
@@ -377,8 +392,8 @@ module cmsdk_mcu_system #(
// Otherwise there is only one master (cpu), so AHB system
// clock can be stopped when DMA take place.
-// assign HCLKSYS = (INCLUDE_DMA!=0) ? SCLK : HCLK;
- assign HCLKSYS = SCLK;
+ assign HCLKSYS = (INCLUDE_DMA!=0) ? SCLK : HCLK;
+// assign HCLKSYS = SCLK;
`ifdef CORTEX_M0DESIGNSTART
@@ -428,7 +443,7 @@ u_cortexm0_ds
assign DBGRESTART = 1'b0; // multi-core synchronous restart from halt
assign EDBGRQ = 1'b0; // multi-core synchronous halt request
- assign RXEV = dma_done; // Generate event when a DMA operation completed.
+ assign RXEV = dmac_done; // Generate event when a DMA operation completed.
// No MTB in Cortex-M0
assign HRDATAMTB = {32{1'b0}};
@@ -538,7 +553,7 @@ u_cortexm0_ds
assign DBGRESTART = 1'b0; // multi-core synchronous restart from halt
assign EDBGRQ = 1'b0; // multi-core synchronous halt request
- assign RXEV = dma_done; // Generate event when a DMA operation completed.
+ assign RXEV = dmac_done; // Generate event when a DMA operation completed.
// No MTB in Cortex-M0
assign HRDATAMTB = {32{1'b0}};
@@ -609,12 +624,83 @@ u_cortexm0_ds
end endgenerate
- /// generate if (INCLUDE_DMA != 0) begin : gen_ahb_master_mux
+ // -------------------------------
+ // DMA Controller
+ // -------------------------------
+
+ // DMA interface not used in this example system
+ wire [DMA_CHANNEL_NUM-1:0] dma230_tie0; // tie off signal.
+
+ assign dma230_tie0 = {DMA_CHANNEL_NUM{1'b0}};
+
+ // DMA done per channel
+ wire [DMA_CHANNEL_NUM-1:0] dma230_done_ch;
+
+ generate if (INCLUDE_DMA != 0) begin : gen_pl230_udma
+ // DMA controller present
+ pl230_udma u_pl230_udma (
+ // Clock and Reset
+ .hclk (HCLKSYS),
+ .hresetn (HRESETn),
+ // DMA Control
+ .dma_req (dma230_tie0),
+ .dma_sreq (dma230_tie0),
+ .dma_waitonreq (dma230_tie0),
+ .dma_stall (1'b0),
+ .dma_active (),
+ .dma_done (dma230_done_ch),
+ .dma_err (dmac_err),
+ // AHB-Lite Master Interface
+ .hready (dmac_hready),
+ .hresp (dmac_hresp),
+ .hrdata (dmac_hrdata),
+ .htrans (dmac_htrans),
+ .hwrite (dmac_hwrite),
+ .haddr (dmac_haddr),
+ .hsize (dmac_hsize),
+ .hburst (dmac_hburst),
+ .hmastlock (dmac_hmastlock),
+ .hprot (dmac_hprot),
+ .hwdata (dmac_hwdata),
+ // APB Slave Interface
+ .pclken (PCLKEN),
+ .psel (dmac_psel),
+ .pen (exp_penable),
+ .pwrite (exp_pwrite),
+ .paddr (exp_paddr[11:0]),
+ .pwdata (exp_pwdata[31:0]),
+ .prdata (dmac_prdata)
+ );
+
+ assign dmac_hready = dmac_hreadyout;
+ assign dmac_pready = 1'b1;
+ assign dmac_pslverr = 1'b0;
+ assign dmac_done = |dma230_done_ch; // OR all the DMA done together
+
+ end else begin : gen_no_pl230_udma
+ // DMA controller not present
+ assign dmac_htrans = 2'b00;
+ assign dmac_hwrite = 1'b0;
+ assign dmac_haddr = 32'h00000000;
+ assign dmac_hsize = 3'b000;
+ assign dmac_hburst = 3'b000;
+ assign dmac_hmastlock = 1'b0;
+ assign dmac_hprot = 4'b0000;
+ assign dmac_hwdata = 32'h00000000;
+
+ assign dmac_done = 1'b0;
+ assign dmac_err = 1'b0;
+ assign dmac_pready = 1'b1;
+ assign dmac_pslverr = 1'b0;
+ assign dmac_prdata = 32'h00000000;
+ assign dma230_done_ch = {DMA_CHANNEL_NUM{1'b0}};
+
+ end endgenerate
cmsdk_ahb_master_mux #(
.PORT0_ENABLE (1),
- .PORT1_ENABLE (0),
+ .PORT1_ENABLE (1),
.PORT2_ENABLE (1),
.DW (32)
)
@@ -637,35 +723,35 @@ u_cortexm0_ds
.HRESPS0 (cm_hresp),
.HRDATAS0 (cm_hrdata[31:0]),
- .HSELS1 (1'b0),
- .HADDRS1 ({32{1'b0}}),
- .HTRANSS1 ({2{1'b0}}),
- .HSIZES1 ({3{1'b0}}),
- .HWRITES1 (1'b0),
- .HREADYS1 (1'b1),
- .HPROTS1 ({4{1'b0}}),
- .HBURSTS1 ({3{1'b0}}),
- .HMASTLOCKS1 (1'b0),
- .HWDATAS1 ({32{1'b0}}),
-
- .HREADYOUTS1 (),
- .HRESPS1 (),
- .HRDATAS1 (),
+ .HSELS1 (1'b1),
+ .HADDRS1 (dmac_haddr[31:0]),
+ .HTRANSS1 (dmac_htrans[1:0]),
+ .HSIZES1 (dmac_hsize[2:0]),
+ .HWRITES1 (dmac_hwrite),
+ .HREADYS1 (dmac_hready),
+ .HPROTS1 (dmac_hprot[3:0]),
+ .HBURSTS1 (dmac_hburst[2:0]),
+ .HMASTLOCKS1 (dmac_hmastlock),
+ .HWDATAS1 (dmac_hwdata[31:0]),
+
+ .HREADYOUTS1 (dmac_hreadyout),
+ .HRESPS1 (dmac_hresp),
+ .HRDATAS1 (dmac_hrdata[31:0]),
.HSELS2 (1'b1),
- .HADDRS2 (dmac_haddr[31:0]),
- .HTRANSS2 (dmac_htrans[1:0]),
- .HSIZES2 (dmac_hsize[2:0]),
- .HWRITES2 (dmac_hwrite),
- .HREADYS2 (dmac_hready),
- .HPROTS2 (dmac_hprot[3:0]),
- .HBURSTS2 (dmac_hburst[2:0]),
- .HMASTLOCKS2 (dmac_hmastlock),
- .HWDATAS2 (dmac_hwdata[31:0]),
-
- .HREADYOUTS2 (dmac_hready),
- .HRESPS2 (dmac_hresp),
- .HRDATAS2 (dmac_hrdata[31:0]),
+ .HADDRS2 (ahbx_haddr[31:0]),
+ .HTRANSS2 (ahbx_htrans[1:0]),
+ .HSIZES2 (ahbx_hsize[2:0]),
+ .HWRITES2 (ahbx_hwrite),
+ .HREADYS2 (ahbx_hready),
+ .HPROTS2 (ahbx_hprot[3:0]),
+ .HBURSTS2 (ahbx_hburst[2:0]),
+ .HMASTLOCKS2 (ahbx_hmastlock),
+ .HWDATAS2 (ahbx_hwdata[31:0]),
+
+ .HREADYOUTS2 (ahbx_hready),
+ .HRESPS2 (ahbx_hresp),
+ .HRDATAS2 (ahbx_hrdata[31:0]),
// Output master port
.HSELM (sys_hselm), // Note: sys_hselm is not required for this particular example system.
@@ -985,7 +1071,7 @@ u_cortexm0_ds
.ext12_psel (exp12_psel),
.ext13_psel (exp13_psel),
.ext14_psel (exp14_psel),
- .ext15_psel (exp15_psel),
+ .ext15_psel (dmac_psel),
// Input from APB devices on APB expansion ports
.ext12_prdata (exp12_prdata),
@@ -997,9 +1083,9 @@ u_cortexm0_ds
.ext14_prdata (exp14_prdata),
.ext14_pready (exp14_pready),
.ext14_pslverr (exp14_pslverr),
- .ext15_prdata (exp15_prdata),
- .ext15_pready (exp15_pready),
- .ext15_pslverr (exp15_pslverr),
+ .ext15_prdata (dmac_prdata),
+ .ext15_pready (dmac_pready),
+ .ext15_pslverr (dmac_pslverr),
.APBACTIVE (APBACTIVE), // Status Output for clock gating
@@ -1051,7 +1137,7 @@ u_cortexm0_ds
assign intisr_cm0[ 6] = apbsubsys_interrupt[ 6] | gpio0_combintr;
assign intisr_cm0[ 7] = apbsubsys_interrupt[ 7] | gpio1_combintr;
assign intisr_cm0[14: 8] = apbsubsys_interrupt[14: 8];
- assign intisr_cm0[15] = apbsubsys_interrupt[15] | dma_done | dma_err;
+ assign intisr_cm0[15] = apbsubsys_interrupt[15] | dmac_done | dmac_err;
assign intisr_cm0[31:16] = apbsubsys_interrupt[31:16]| gpio0_intr;
// -------------------------------
@@ -1146,24 +1232,24 @@ u_cortexm0_ds
.HRESETn (HRESETn),
// Main Master signals
- .HADDR (dmac_haddr),
- .HTRANS (dmac_htrans),
- .HWRITE (dmac_hwrite),
- .HSIZE (dmac_hsize),
- .HBURST (dmac_hburst),
- .HPROT (dmac_hprot),
- .HWDATA (dmac_hwdata),
+ .HADDR (ahbx_haddr),
+ .HTRANS (ahbx_htrans),
+ .HWRITE (ahbx_hwrite),
+ .HSIZE (ahbx_hsize),
+ .HBURST (ahbx_hburst),
+ .HPROT (ahbx_hprot),
+ .HWDATA (ahbx_hwdata),
// Main Decoder signals
.HSELx (1'bx), // Ignored for this instance
// Main Slave signals
- .HRDATA (dmac_hrdata),
- .HREADY (dmac_hready),
+ .HRDATA (ahbx_hrdata),
+ .HREADY (ahbx_hready),
.HREADYOUT (1'bx), // Ignored for this instance
- .HRESP (dmac_hresp),
+ .HRESP (ahbx_hresp),
- .HMASTLOCK (dmac_hmastlock)
+ .HMASTLOCK (ahbx_hmastlock)
);
// AHB protocol checker for the out bus from bus multiplexer
@@ -1210,7 +1296,7 @@ u_cortexm0_ds
.HREADYOUT (1'bx), // Ignored for this instance
.HRESP (sys_hresp),
- .HMASTLOCK (dmac_hmastlock)
+ .HMASTLOCK (ahbx_hmastlock)
);
end endgenerate