From dd8399c1205ce864b087cc4264583948ac2906e1 Mon Sep 17 00:00:00 2001
From: dwf1m12 <d.w.flynn@soton.ac.uk>
Date: Mon, 14 Mar 2022 13:14:12 +0000
Subject: [PATCH] Add binary text output file to ROM file generator
---
GLIB/mem/verilog/SROM_Ax32.v | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/GLIB/mem/verilog/SROM_Ax32.v b/GLIB/mem/verilog/SROM_Ax32.v
index cece5ad..bbbfcd2 100644
--- a/GLIB/mem/verilog/SROM_Ax32.v
+++ b/GLIB/mem/verilog/SROM_Ax32.v
@@ -10,7 +10,7 @@
//
// David Flynn (d.w.flynn@soton.ac.uk)
//
-// Copyright © 2021, SoC Labs (www.soclabs.org)
+// Copyright © 2021-2, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
module SROM_Ax32
@@ -25,6 +25,7 @@ module SROM_Ax32
localparam MEMDEPTH = (1 << (ADDRWIDTH)-1)-1;
localparam romgenfile = "bootrom.v";
+ localparam bingenfile = "bootrom.bintxt";
// Reg declarations
reg [7:0] rombyte0 [0:MEMDEPTH];
@@ -39,6 +40,7 @@ module SROM_Ax32
reg [7:0] fileimage [((4<<ADDRWIDTH)-1):0];
function [31:0] NoX32; input [31:0] n; NoX32 = (((^n) === 1'bx) ? 32'h0 : n); endfunction
integer fd; // file descriptor for file output
+ integer fd2; // file descriptor for file 2 output
integer i;
reg [39:0] today [0:1];
@@ -66,7 +68,8 @@ initial
if (romgen != 0)
begin
fd = $fopen(romgenfile);
- if(fd == 0) begin
+ fd2 = $fopen(bingenfile);
+ if ((fd == 0) || (fd2 == 0)) begin
$display("rom32gen: Error, zero returned in response to $fopen\n");
end
else begin
@@ -90,12 +93,15 @@ initial
$fwrite(fd,"always @(posedge CLK) if (EN) addr_r <= ADDR;\n");
$fwrite(fd,"always @(addr_r)");
$fwrite(fd," case(addr_r[%0d:2]) \n", ADDRWIDTH+1);
- for (i = 0; i < 4 << (ADDRWIDTH); i=i+4)
+ for (i = 0; i < 4 << (ADDRWIDTH); i=i+4) begin
$fwrite(fd," %2d'h%2x : RDATA <= 32'h%8x; // 0x%04x\n", ADDRWIDTH, i>>2, NoX32({fileimage[i+3],fileimage[i+2],fileimage[i+1],fileimage[i+0]}), i );
+ $fwrite(fd2,"%32b\n",NoX32({fileimage[i+3],fileimage[i+2],fileimage[i+1],fileimage[i+0]}));
+ end
$fwrite(fd," default : RDATA <=32'h0;\n");
$fwrite(fd," endcase\n");
$fwrite(fd,"endmodule\n");
$fclose(fd);
+ $fclose(fd2);
end
end
end
--
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