diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/testcodes/hello/makefile b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/testcodes/hello/makefile
index 805ba5be59ec3707fe4eae467163f5da53f236c5..63ee0c929bf02c0ffb9fb3ff9f58c63afee43b84 100644
--- a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/testcodes/hello/makefile
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/testcodes/hello/makefile
@@ -103,11 +103,17 @@ COMPILE_MICROLIB = 0
# Small Multiply (Cortex-M0/M0+ has small multiplier option)
COMPILE_SMALLMUL = 0
-ARM_CC_OPTIONS = -c -O3 -g -Otime -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
+#ARM_CC_OPTIONS = -c -O3 -g -Otime -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
+# -I $(SOFTWARE_DIR)/common/retarget $(USER_DEFINE)
+#ARM_ASM_OPTIONS = -g
+#ARM_LINK_OPTIONS = "--keep=$(STARTUP_FILE).o(RESET)" "--first=$(STARTUP_FILE).o(RESET)" \
+# --rw_base 0x20000000 --ro_base 0x00000000 --map --info sizes
+
+ARM_CC_OPTIONS = -c -O3 -Ospace -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
-I $(SOFTWARE_DIR)/common/retarget $(USER_DEFINE)
-ARM_ASM_OPTIONS = -g
+ARM_ASM_OPTIONS =
ARM_LINK_OPTIONS = "--keep=$(STARTUP_FILE).o(RESET)" "--first=$(STARTUP_FILE).o(RESET)" \
- --rw_base 0x20000000 --ro_base 0x00000000 --map
+ --no_debug --rw_base 0x20000000 --ro_base 0x00000000 --map --info sizes
ifeq ($(COMPILE_BIGEND),1)
# Big Endian
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu.v b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu.v
index e64768d672682e4c545db394e66324024e646ca1..2df06e50a28ff85804f49cdce634fc6320d4abd7 100644
--- a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu.v
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu.v
@@ -36,6 +36,8 @@
//-----------------------------------------------------------------------------
//
+// `define SYNTHBOOT 1
+
`include "cmsdk_mcu_defs.v"
module cmsdk_mcu #(
@@ -743,7 +745,9 @@ module cmsdk_mcu #(
//----------------------------------------
cmsdk_ahb_rom
#(.MEM_TYPE(ROM_MEM_TYPE),
- .AW(16), // 64K bytes flash ROM
+/// .AW(16), // 64K bytes flash ROM
+// .AW(13), // 8K bytes flash ROM -Dhry
+ .AW(10), // 1K bytes flash ROM - Hello
.filename("image.hex"),
.WS_N(`ARM_CMSDK_ROM_MEM_WS_N),
.WS_S(`ARM_CMSDK_ROM_MEM_WS_S),
@@ -752,7 +756,9 @@ cmsdk_ahb_rom
.HCLK (HCLKSYS),
.HRESETn (HRESETn),
.HSEL (flash_hsel), // AHB inputs
- .HADDR (HADDR[15:0]),
+/// .HADDR (HADDR[15:0]),
+// .HADDR (HADDR[12:0]),
+ .HADDR (HADDR[ 9:0]),
.HTRANS (HTRANS),
.HSIZE (HSIZE),
.HWRITE (HWRITE),
@@ -768,9 +774,31 @@ cmsdk_ahb_rom
// Boot loader / Firmware
//----------------------------------------
// Only use if BOOT_MEM_TYPE is not zero
+`ifdef SYNTHBOOTROM
+//ahb_bootrom
+ahb_bootrom__mangled
+// #(.AW(10) ) // 1K bytes ROM
+ u_ahb_bootloader (
+ .HCLK (HCLKSYS),
+ .HRESETn (HRESETn),
+ .HSEL (boot_hsel), // AHB inputs
+ .HADDR (HADDR[ 9:0]),
+ .HTRANS (HTRANS),
+ .HSIZE (HSIZE),
+ .HWRITE (HWRITE),
+ .HWDATA (HWDATA),
+ .HREADY (HREADY),
+
+ .HREADYOUT (boot_hreadyout), // Outputs
+ .HRDATA (boot_hrdata),
+ .HRESP (boot_hresp)
+ );
+`else
+// Only use if BOOT_MEM_TYPE is not zero
cmsdk_ahb_rom
#(.MEM_TYPE(BOOT_MEM_TYPE),
- .AW(12), // 4K bytes ROM
+// .AW(12), // 4K bytes ROM
+ .AW(10), // 1K bytes ROM
.filename("bootloader.hex"),
.WS_N(`ARM_CMSDK_BOOT_MEM_WS_N),
.WS_S(`ARM_CMSDK_BOOT_MEM_WS_S),
@@ -779,7 +807,8 @@ cmsdk_ahb_rom
.HCLK (HCLKSYS),
.HRESETn (HRESETn),
.HSEL (boot_hsel), // AHB inputs
- .HADDR (HADDR[11:0]),
+// .HADDR (HADDR[11:0]),
+ .HADDR (HADDR[ 9:0]),
.HTRANS (HTRANS),
.HSIZE (HSIZE),
.HWRITE (HWRITE),
@@ -790,20 +819,23 @@ cmsdk_ahb_rom
.HRDATA (boot_hrdata),
.HRESP (boot_hresp)
);
+`endif
//----------------------------------------
// SRAM
//----------------------------------------
cmsdk_ahb_ram
#(.MEM_TYPE(RAM_MEM_TYPE),
- .AW(16), // 64K bytes SRAM
+/// .AW(16), // 64K bytes SRAM
+ .AW( 9), // 1K bytes SRAM
.WS_N(`ARM_CMSDK_RAM_MEM_WS_N),
.WS_S(`ARM_CMSDK_RAM_MEM_WS_S))
u_ahb_ram (
.HCLK (HCLKSYS),
.HRESETn (HRESETn),
.HSEL (sram_hsel), // AHB inputs
- .HADDR (HADDR[15:0]),
+/// .HADDR (HADDR[15:0]),
+ .HADDR (HADDR[ 8:0]),
.HTRANS (HTRANS),
.HSIZE (HSIZE),
.HWRITE (HWRITE),
@@ -891,6 +923,8 @@ cmsdk_ahb_ram
// IO pads
.P0 (P0),
.P1 (P1),
+ .p1_out_mux ( ),
+ .p1_out_en_mux ( ),
.nTRST (nTRST), // Not needed if serial-wire debug is used
.TDI (TDI), // Not needed if serial-wire debug is used
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_defs.v b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_defs.v
index 9a89cebd5fceaec5f02ea7642c50e69fe3160cd0..dfb573e84482f04c08a8d1a0185de3ac889bd600 100644
--- a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_defs.v
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_defs.v
@@ -211,7 +211,7 @@
// Force the system to select the 16-bit Flash when this option is enabled.
`ifndef ARM_CMSDK_INCLUDE_F16
// Boot loader memory type
-`define ARM_CMSDK_BOOT_MEM_TYPE `AHB_ROM_NONE
+`define ARM_CMSDK_BOOT_MEM_TYPE `AHB_ROM_BEH_MODEL
// Based on the definition constants in logical/models/memories/cmsdk_ahb_memory_model_defs.v
// 0) AHB_ROM_NONE - memory not present
// 1) AHB_ROM_BEH_MODEL - behavioral ROM memory
@@ -220,7 +220,7 @@
// 4) AHB_ROM_FLASH16_MODEL - behavioral 16-bit flash memory
// ROM memory type
-`define ARM_CMSDK_ROM_MEM_TYPE `AHB_ROM_BEH_MODEL
+`define ARM_CMSDK_ROM_MEM_TYPE `AHB_ROM_FPGA_SRAM_MODEL
// Based on the definition constants in logical/models/memories/cmsdk_ahb_memory_model_defs.v
// 0) AHB_ROM_NONE - memory not present (Invalid for a Cortex-M0 system))
// 1) AHB_ROM_BEH_MODEL - behavioral ROM memory
@@ -244,7 +244,7 @@
`endif
// RAM memory type
-`define ARM_CMSDK_RAM_MEM_TYPE `AHB_RAM_BEH_MODEL
+`define ARM_CMSDK_RAM_MEM_TYPE `AHB_RAM_FPGA_SRAM_MODEL
// Based on the definition constants in logical/models/memories/cmsdk_ahb_memory_model_defs.v
// 0) AHB_RAM_NONE - memory not present (Invalid for a Cortex-M0 system)
// 1) AHB_RAM_BEH_MODEL - behavioral RAM memory
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_pin_mux.v b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_pin_mux.v
index 3e13294a7d91e6aba050c5afffe13042ddff70ed..82d0ae5d32d2233ac83213d5d1c1b94ebd6dd671 100644
--- a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_pin_mux.v
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_pin_mux.v
@@ -75,8 +75,11 @@ module cmsdk_mcu_pin_mux (
input wire i_swdoen,
// IO pads
- inout wire [15:0] P0,
- inout wire [15:0] P1,
+ inout wire [15:0] P0, // legacy
+ inout wire [15:0] P1, // legacy
+
+ output wire [15:0] p1_out_mux, //alt-function mux
+ output wire [15:0] p1_out_en_mux, //alt-function mux
input wire nTRST, // Not needed if serial-wire debug is used
input wire TDI, // Not needed if serial-wire debug is used
@@ -88,10 +91,9 @@ module cmsdk_mcu_pin_mux (
// Internal wires
//-------------------------------------------
wire [15:0] p0_out_mux;
- wire [15:0] p1_out_mux;
-
wire [15:0] p0_out_en_mux;
- wire [15:0] p1_out_en_mux;
+// wire [15:0] p1_out_mux; // promoted to block output
+// wire [15:0] p1_out_en_mux; // promoted to block output
//-------------------------------------------
// Beginning of main code
@@ -139,6 +141,7 @@ module cmsdk_mcu_pin_mux (
assign p1_out_en_mux[5] = (p1_altfunc[5]) ? uart2_txen : p1_outen[5];
assign p1_out_en_mux[15:6] = p1_outen[15:6];
+
// Output tristate
assign P0[ 0] = p0_out_en_mux[ 0] ? p0_out_mux[ 0] : 1'bz;
assign P0[ 1] = p0_out_en_mux[ 1] ? p0_out_mux[ 1] : 1'bz;
@@ -174,6 +177,7 @@ module cmsdk_mcu_pin_mux (
assign P1[14] = p1_out_en_mux[14] ? p1_out_mux[14] : 1'bz;
assign P1[15] = p1_out_en_mux[15] ? p1_out_mux[15] : 1'bz;
+/*
// synopsys translate_off
// Pullup
@@ -212,7 +216,7 @@ module cmsdk_mcu_pin_mux (
pullup(P1[15]);
// synopsys translate_on
-
+*/
//-------------------------------------------
// Debug connections
//-------------------------------------------
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/tb_cmsdk_mcu.v b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/tb_cmsdk_mcu.v
index 4cd7146d5b07063c11177e55a8f92b2b6ea23bd1..95e2aa6a67fe4b8ca04df4290ed82f66dc39edd7 100644
--- a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/tb_cmsdk_mcu.v
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/tb_cmsdk_mcu.v
@@ -168,11 +168,25 @@ module tb_cmsdk_mcu;
parameter INCLUDE_JTAG = 0; // Do not Include JTAG feature
`endif
+`define MEM_INIT 1;
+SROM_Ax32
+ #(.ADDRWIDTH (8),
+ .filename ("bootloader.hex"),
+ .romgen (1)
+ )
+ u_BOOTROM (
+ .CLK(XTAL1),
+ .ADDR(8'h0),
+ .SEL(1'b0),
+ .RDATA( )
+ );
+
// --------------------------------------------------------------------------------
// Cortex-M0/Cortex-M0+ Microcontroller
// --------------------------------------------------------------------------------
+// cmsdk_mcu_chip
cmsdk_mcu
#(.CLKGATE_PRESENT (CLKGATE_PRESENT),
.BE (BE),
@@ -204,6 +218,12 @@ module tb_cmsdk_mcu;
.INCLUDE_JTAG (INCLUDE_JTAG) // Include JTAG feature
)
u_cmsdk_mcu (
+`ifdef POWER_PINS
+ .VDDIO (VDDIO),
+ .VSSIO (VSSIO),
+ .VDD (VDD),
+ .VSS (VSS),
+`endif
.XTAL1 (XTAL1), // input
.XTAL2 (XTAL2), // output
.NRST (NRST), // active low reset
@@ -226,6 +246,41 @@ module tb_cmsdk_mcu;
.NRST (NRST)
);
+ // Pullup to suppress X-inputs
+ pullup(P0[ 0]);
+ pullup(P0[ 1]);
+ pullup(P0[ 2]);
+ pullup(P0[ 3]);
+ pullup(P0[ 4]);
+ pullup(P0[ 5]);
+ pullup(P0[ 6]);
+ pullup(P0[ 7]);
+ pullup(P0[ 8]);
+ pullup(P0[ 9]);
+ pullup(P0[10]);
+ pullup(P0[11]);
+ pullup(P0[12]);
+ pullup(P0[13]);
+ pullup(P0[14]);
+ pullup(P0[15]);
+
+ pullup(P1[ 0]);
+ pullup(P1[ 1]);
+ pullup(P1[ 2]);
+ pullup(P1[ 3]);
+ pullup(P1[ 4]);
+ pullup(P1[ 5]);
+ pullup(P1[ 6]);
+ pullup(P1[ 7]);
+ pullup(P1[ 8]);
+ pullup(P1[ 9]);
+ pullup(P1[10]);
+ pullup(P1[11]);
+ pullup(P1[12]);
+ pullup(P1[13]);
+ pullup(P1[14]);
+ pullup(P1[15]);
+
// --------------------------------------------------------------------------------
// UART output capture
// --------------------------------------------------------------------------------
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/tbench_M0.vc b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/tbench_M0.vc
index 5b3ebb122ed685b2fc0461d3c8f5dda8d7dabb22..364812d3e78b56c5340ae57b375f02d1bd3975e9 100644
--- a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/tbench_M0.vc
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/tbench_M0.vc
@@ -49,6 +49,8 @@
../verilog/tb_cmsdk_mcu.v
+incdir+../verilog
+../../../../../GLIB/pads/verilog/GLIB_PADLIB.v
+../../../../../GLIB/mem/verilog/SROM_Ax32.v
// ================= Testbench path ===================
-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_debug_tester/verilog