From 980b8fab2d8c61e4a3a9a75edd35c3c9b0c1a41f Mon Sep 17 00:00:00 2001
From: dwf1m12 <d.w.flynn@soton.ac.uk>
Date: Wed, 13 Jul 2022 11:14:56 +0100
Subject: [PATCH] upgrade FPGA support for Xilinx PYNQ platform (vivado 2021.1
environment)
---
.../software/common/bootloader/bootloader.c | 5 +-
.../fpga_imp/build_fpga_pynq_z2.scr | 1 +
.../fpga_imp/build_fpga_pynq_zcu104.scr | 1 +
.../soclabs/driver/uartlite.py | 88 ++
.../soclabs/soclabs_cm0sdk_mcu.ipynb | 372 ++++++
.../soclabs/driver/uartlite.py | 88 ++
.../soclabs/soclabs_cm0sdk_mcu.ipynb | 372 ++++++
.../fpga_imp/scripts/build_mcu_fpga_ip.tcl | 113 ++
.../scripts/build_mcu_fpga_pynq_z2.tcl | 117 ++
.../scripts/build_mcu_fpga_pynq_zcu104.tcl | 117 ++
.../fpga_imp/target_fpga_pynq_z2/design_1.tcl | 508 ++++++++
.../target_fpga_pynq_z2/design_1_wrapper.v | 107 ++
.../target_fpga_pynq_z2/fpga_pinmap.xdc | 246 +---
.../fpga_imp/target_fpga_zcu104/design_1.tcl | 1017 +++++++++++++++++
.../target_fpga_zcu104/design_1_wrapper.v | 107 ++
.../target_fpga_zcu104/fpga_pinmap.xdc | 178 ++-
.../target_fpga_zcu104/fpga_timing.xdc | 132 +--
.../systems/cortex_m0_mcu/verilog/bootrom.v | 96 +-
.../cortex_m0_mcu/verilog/tb_cmsdk_mcu.v | 2 +-
19 files changed, 3216 insertions(+), 451 deletions(-)
create mode 100755 Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/build_fpga_pynq_z2.scr
create mode 100755 Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/build_fpga_pynq_zcu104.scr
create mode 100755 Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/pynq_export/pz104/jupyter_notebooks/soclabs/driver/uartlite.py
create mode 100755 Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/pynq_export/pz104/jupyter_notebooks/soclabs/soclabs_cm0sdk_mcu.ipynb
create mode 100755 Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/pynq_export/pz2/jupyter_notebooks/soclabs/driver/uartlite.py
create mode 100755 Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/pynq_export/pz2/jupyter_notebooks/soclabs/soclabs_cm0sdk_mcu.ipynb
create mode 100644 Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/build_mcu_fpga_ip.tcl
create mode 100644 Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/build_mcu_fpga_pynq_z2.tcl
create mode 100644 Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/build_mcu_fpga_pynq_zcu104.tcl
create mode 100644 Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_pynq_z2/design_1.tcl
create mode 100644 Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_pynq_z2/design_1_wrapper.v
create mode 100644 Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_zcu104/design_1.tcl
create mode 100644 Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_zcu104/design_1_wrapper.v
diff --git a/Cortex-M0/soclabs_demo/software/common/bootloader/bootloader.c b/Cortex-M0/soclabs_demo/software/common/bootloader/bootloader.c
index 22c16f2..59a41cc 100644
--- a/Cortex-M0/soclabs_demo/software/common/bootloader/bootloader.c
+++ b/Cortex-M0/soclabs_demo/software/common/bootloader/bootloader.c
@@ -57,8 +57,9 @@ unsigned char UartPutc(unsigned char my_ch)
{
while ((CMSDK_UART2->STATE & 1)); // Wait if Transmit Holding register is full
CMSDK_UART2->DATA = my_ch; // write to transmit holding register
- while ((CMSDK_USRT2->STATE & 1)); // Wait if Transmit Holding register is full
- CMSDK_USRT2->DATA = my_ch; // write to transmit holding register
+// while ((CMSDK_USRT2->STATE & 1)); // Wait if Transmit Holding register is full
+ if ((CMSDK_USRT2->STATE & 1) == 0)
+ CMSDK_USRT2->DATA = my_ch; // write to transmit holding register
return (my_ch);
}
// Uart string output
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/build_fpga_pynq_z2.scr b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/build_fpga_pynq_z2.scr
new file mode 100755
index 0000000..781e2c3
--- /dev/null
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/build_fpga_pynq_z2.scr
@@ -0,0 +1 @@
+vivado -mode tcl -source scripts/build_mcu_fpga_pynq_z2.tcl
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/build_fpga_pynq_zcu104.scr b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/build_fpga_pynq_zcu104.scr
new file mode 100755
index 0000000..8d883a1
--- /dev/null
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/build_fpga_pynq_zcu104.scr
@@ -0,0 +1 @@
+vivado -mode batch -source scripts/build_mcu_fpga_pynq_zcu104.tcl
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/pynq_export/pz104/jupyter_notebooks/soclabs/driver/uartlite.py b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/pynq_export/pz104/jupyter_notebooks/soclabs/driver/uartlite.py
new file mode 100755
index 0000000..4da3b33
--- /dev/null
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/pynq_export/pz104/jupyter_notebooks/soclabs/driver/uartlite.py
@@ -0,0 +1,88 @@
+from time import sleep, time
+from pynq import MMIO
+
+RX_FIFO = 0x00
+TX_FIFO = 0x04
+
+#Status Reg
+STAT_REG = 0x08
+RX_VALID = 0
+RX_FULL = 1
+TX_EMPTY = 2
+TX_FULL = 3
+IS_INTR = 4
+OVERRUN_ERR = 5
+FRAME_ERR = 6
+PARITY_ERR =7
+
+#Ctrl Reg
+CTRL_REG = 0x0C
+RST_TX = 0
+RST_RX = 1
+INTR_EN = 4
+
+class UartLite:
+ def __init__(self, address):
+ # Setup axi core
+ self.uart = MMIO(address,0x10000, debug=False)
+ self.address = address
+
+ def getBit(self,num,pos):
+ return (num&1<<pos)>>pos
+
+ def setupCtrlReg(self):
+ # Reset FIFOs, disable interrupts
+ self.uart.write(CTRL_REG, 1<<RST_TX | 1<<RST_RX)
+ sleep(0.0)
+ self.uart.write(CTRL_REG,0)
+ sleep(0.0)
+
+ def currentStatus(self):
+ """Returns object that specifies current status of axi core"""
+ status = self.uart.read(STAT_REG)
+ return {'RX_VALID':self.getBit(status,RX_VALID),
+ 'RX_FULL':self.getBit(status, RX_FULL),
+ 'TX_EMPTY':self.getBit(status, TX_EMPTY),
+ 'TX_FULL':self.getBit(status, TX_FULL),
+ 'IS_INTR':self.getBit(status, IS_INTR),
+ 'OVERRUN_ERR':self.getBit(status, OVERRUN_ERR),
+ 'FRAME_ERR':self.getBit(status, FRAME_ERR),
+ 'PARITY_ERR':self.getBit(status, PARITY_ERR)}
+
+ def read(self, count, timeout = 1):
+ buf = ""
+ stop_time = time() + timeout
+ for i in range(count):
+ # Wait till RX fifo has valid data, skip if timeout exceeded
+ while (not (self.uart.read(STAT_REG) & 1<<RX_VALID)) and (time()<stop_time):
+ pass
+ if time()>=stop_time:
+ break
+ buf += chr(self.uart.read(RX_FIFO))
+ return buf
+
+ def write(self, buf, timeout = 10):
+ """
+ buf: iterable
+
+ """
+ stop_time = time() + timeout
+ wr_count = 0
+ for i in buf:
+ #Wait while TX FIFO is Full, stop waiting if timeout passes
+ while (self.uart.read(STAT_REG) & 1<<TX_FULL) and (time()<stop_time):
+ pass
+ # Check timeout
+ if time()>stop_time:
+ break
+ self.uart.write(TX_FIFO, ord(i))
+ wr_count += 1
+ return wr_count
+
+ def readLine(self):
+ buf = self.read(1)
+ if len(buf) ==0:
+ return ""
+ while '\n' not in buf:
+ buf += self.read(1)
+ return buf
\ No newline at end of file
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/pynq_export/pz104/jupyter_notebooks/soclabs/soclabs_cm0sdk_mcu.ipynb b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/pynq_export/pz104/jupyter_notebooks/soclabs/soclabs_cm0sdk_mcu.ipynb
new file mode 100755
index 0000000..093b39f
--- /dev/null
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/pynq_export/pz104/jupyter_notebooks/soclabs/soclabs_cm0sdk_mcu.ipynb
@@ -0,0 +1,372 @@
+{
+ "cells": [
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "# SoCLabs cm0sdk mcu overlay\n",
+ "This notebook demonstrates how to download the FPGA overlay and communicate with programmable logic state. \n",
+ "\n",
+ "## 1. Instantiating an overlay\n",
+ "With the following overlay bundle present in the `overlays` folder, users can instantiate the overlay easily.\n",
+ "\n",
+ "* A bitstream file (\\*.bit).\n",
+ "* An hwh file (\\*.hwh).\n",
+ "* A python class (\\*.py).\n",
+ "\n",
+ "For example, a `soclabs` overlay called `design_1` can be loaded by:\n",
+ "```python\n",
+ "from pynq.overlays.base import BaseOverlay\n",
+ "overlay = BaseOverlay(\"soclabs/design_1.bit\")\n",
+ "```\n",
+ "A `drivers` directory is provided for device driver templates for comms channels. (uartlite example).\n",
+ "\n",
+ "Users can also use the absolute file path of the bitstream to instantiate the overlay.\n",
+ "\n",
+ "In this notebook, we get the current bitstream loaded on PL, and try to download it multiple times."
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 1,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "application/javascript": [
+ "\n",
+ "try {\n",
+ "require(['notebook/js/codecell'], function(codecell) {\n",
+ " codecell.CodeCell.options_default.highlight_modes[\n",
+ " 'magic_text/x-csrc'] = {'reg':[/^%%microblaze/]};\n",
+ " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n",
+ " Jupyter.notebook.get_cells().map(function(cell){\n",
+ " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n",
+ " });\n",
+ "});\n",
+ "} catch (e) {};\n"
+ ]
+ },
+ "metadata": {},
+ "output_type": "display_data"
+ },
+ {
+ "data": {
+ "application/javascript": [
+ "\n",
+ "try {\n",
+ "require(['notebook/js/codecell'], function(codecell) {\n",
+ " codecell.CodeCell.options_default.highlight_modes[\n",
+ " 'magic_text/x-csrc'] = {'reg':[/^%%pybind11/]};\n",
+ " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n",
+ " Jupyter.notebook.get_cells().map(function(cell){\n",
+ " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n",
+ " });\n",
+ "});\n",
+ "} catch (e) {};\n"
+ ]
+ },
+ "metadata": {},
+ "output_type": "display_data"
+ }
+ ],
+ "source": [
+ "import os, warnings\n",
+ "from pynq import PL\n",
+ "from pynq import Overlay\n",
+ "\n",
+ "from pynq import MMIO\n",
+ "\n",
+ "import sys\n",
+ "sys.path.insert(1, './driver')\n",
+ "from uartlite import *\n",
+ "\n",
+ "ol = Overlay(\"/home/xilinx/pynq/overlays/soclabs/design_1.bit\")\n",
+ "\n",
+ "if not os.path.exists(PL.bitfile_name):\n",
+ " warnings.warn('There is no overlay loaded after boot.', UserWarning)"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "**Note**: If you see a warning message in the above cell, it means that no overlay\n",
+ "has been loaded after boot, hence the PL server is not aware of the \n",
+ "current status of the PL. In that case you won't be able to run this notebook\n",
+ "until you manually load an overlay at least once using:\n",
+ "\n",
+ "```python\n",
+ "from pynq import Overlay\n",
+ "ol = Overlay('your_overlay.bit')\n",
+ "```\n",
+ "\n",
+ "If you do not see any warning message, you can safely proceed.\n",
+ "\n",
+ "Next try relative path:"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 2,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "from pynq import Overlay\n",
+ "ol = Overlay(\"soclabs/design_1.bit\")"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Now we can check the download timestamp for this overlay."
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 3,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "text/plain": [
+ "'2022/7/12 13:24:34 +609181'"
+ ]
+ },
+ "execution_count": 3,
+ "metadata": {},
+ "output_type": "execute_result"
+ }
+ ],
+ "source": [
+ "ol.download()\n",
+ "ol.timestamp"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "## 2. Examining the PL state\n",
+ "\n",
+ "While there can be multiple overlay instances in Python, there is only one bitstream that is currently loaded onto the programmable logic (PL). \n",
+ "\n",
+ "This bitstream state is held in the singleton class, PL, and is available for user queries."
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 4,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "text/plain": [
+ "'/usr/local/lib/python3.6/dist-packages/pynq/overlays/soclabs/design_1.bit'"
+ ]
+ },
+ "execution_count": 4,
+ "metadata": {},
+ "output_type": "execute_result"
+ }
+ ],
+ "source": [
+ "PL.bitfile_name"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 5,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "text/plain": [
+ "'2022/7/12 13:24:34 +609181'"
+ ]
+ },
+ "execution_count": 5,
+ "metadata": {},
+ "output_type": "execute_result"
+ }
+ ],
+ "source": [
+ "PL.timestamp"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Users can verify whether an overlay instance is currently loaded using the Overlay is_loaded() method"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 6,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "text/plain": [
+ "True"
+ ]
+ },
+ "execution_count": 6,
+ "metadata": {},
+ "output_type": "execute_result"
+ }
+ ],
+ "source": [
+ "ol.is_loaded()"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "## 3. Establishing communications \n",
+ "Next set up a serial channel (configured for 9600 baud clocking rate).\n",
+ "Re-download image which also resets the MCU design in PL.\n",
+ "(No explicit to reinitialize the UART after HW reset, as preconfigured baud rate).\n",
+ "Poll for start-up banner from MCU internal boot-ROM.\n",
+ "\n",
+ "Expect a message of the form (sometimes characters are lost as uartlite has no no flow-control support)\n",
+ "\n",
+ "```python\n",
+ " SOCLABS: ARM Cortex-M0 SDK\n",
+ " - load flash\n",
+ "```"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 7,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "\n",
+ "SOCLABS: ARM Cortex-M0 SDK\n",
+ " - load flash\n",
+ "\n",
+ "\n"
+ ]
+ }
+ ],
+ "source": [
+ "# Address of the uart core\n",
+ "ADDRESS = 0x80003000\n",
+ "uart = UartLite(ADDRESS)\n",
+ "ol.download()\n",
+ "# Setup AXI UART register\n",
+ "#uart.setupCtrlReg()\n",
+ "#print(uart.readLine())\n",
+ "#print(uart.readLine())\n",
+ "#print(uart.readLine())\n",
+ "print(uart.read(45,1))"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 8,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "{'RX_VALID': 0, 'RX_FULL': 0, 'TX_EMPTY': 1, 'TX_FULL': 0, 'IS_INTR': 0, 'OVERRUN_ERR': 0, 'FRAME_ERR': 0, 'PARITY_ERR': 0}\n"
+ ]
+ }
+ ],
+ "source": [
+ "print(uart.currentStatus())"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 9,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "#ol.ip_dict"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "## 3. Overlay downloading overhead\n",
+ "\n",
+ "Finally, using Python, we can see the bitstream download time over 50 downloads. "
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 10,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "image/png": 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TuHeA/UuShqTvI4OqemNVLauqg4BTgKur6uXANcDLWrWVwGXt/uVtmbb+6qqqfvcvSRqe7fE9gzcAr0myhu6cwHmt/DxgcSt/DXDGdti3JKkPg0wT/UxVXQtc2+7fChy9lTo/An5vGPuTJA2X30CWJBkGkiTDQJKEYSBJwjCQJGEYSJIwDCRJGAaSJAwDSRKGgSQJw0CShGEgScIwkCRhGEiSMAwkSRgGkiQMA0kShoEkCcNAkoRhIEnCMJAkYRhIkjAMJEkYBpIkDANJEoaBJAnDQJKEYSBJwjCQJGEYSJIwDCRJGAaSJAwDSRKGgSSJAcIgyQFJrklyc5Kbkryqle+d5Mokt7TbvVp5knwgyZok301y5LAehCRpMIMcGTwGvLaqDgeOAV6Z5HDgDOCqqjoUuKotAxwPHNp+Tgc+NMC+JUlD1HcYVNW6qvp2u/8wsBpYCqwAzm/VzgdOavdXABdU55vAoiT79d1zSdLQDOWcQZKDgGcC1wH7VtW6tuoeYN92fylwZ89md7Wyzds6Pcl4kvGNGzcOo3uSpCkMHAZJdgc+A7y6qh7qXVdVBdRM2quqc6tqrKrGlixZMmj3JEnTMFAYJNmJLgguqqrPtuL1E9M/7XZDK18LHNCz+bJWJkmaY4N8mijAecDqqnpfz6rLgZXt/krgsp7yU9unio4BHuyZTpIkzaGFA2z7HOCPgBuSfKeVvQl4F3BJktOA24GT27ovAScAa4AfAq8YYN+SpCHqOwyq6m+ATLL62K3UL+CV/e5PkrT9+A1kSZJhIEkyDCRJGAaSJAwDSRKGgSQJw0CShGEgScIwkCRhGEiSMAwkSYx6GKxaBQcdBBddNL36F13U1X/Sk2a2XT8m29co9KHf/vW7bpj9m82+j3p7O3LfR7292d7XZGbz9WIqVTWyP0dBFVTtumvVhRd2/zDzwgurli+vSrrb3vJdd+3qb77dZNtsq71+9vUnfzJ5HwbZVz+Pd6b966e9bY3tIO3NRt9Hvb0due+j3t6O8Bzp5zWhBzA+09fbGVWe7Z+jegdp4kFPNnjLl/98+cTP4sXD/+VOtq8FC7ZePlXf+/nDnKwPy5f3179+2tvW2PbT3mz2fdTb25H7Purt7QjPkX7fcA4QBum2G01jSY1PLCRw4IFw++1bVly+HO64oxua6Vq+vLudrL1trZvpvqbq+2T7WrAAHn98Zn1Iu6r4TPs32Tb9tNdv/0ah76PS3o7c91FvbxT6PtVzZLLXi229Jtx2W08TWVVVY9PvEDtQGPQ7eJMZ5A+pn1/UsF+8hx0uk22zrXXD7t9s9n3U29uR+z7q7e0Iz5F+3nA+8UTP4szDYEaHEXM2TTTIYdXixcM97Ov3EG7Yh6yjMB+6rbEd9bncUW9vR+77qLe3IzxH+nlNGHCaaEaV5yQMBj3hMuw/ln5P7gz7D3Nb++qnf/2s63eMRqHvO0J7O3LfR7292drXIK8js3zOYM5f8Lf1c9RRR9UWtvXLmMz2+EPqx7D/MEfBqPdPmmv9PkcGeE3oJwxG+5zB2FiNj49PXVGS9DP9nDMY7S+dSZJmhWEgSTIMJEmGgSQJw0CShGEgScIwkCRhGEiSMAwkSRgGkiQMA0kShoEkCcNAkoRhIEnCMJAkMQdhkOS4JP+QZE2SM2Z7/5KkLc1qGCRZAPwP4HjgcOD3kxw+m32QJG1pto8MjgbWVNWtVfUT4JPAilnugyRpMwtneX9LgTt7lu8CntVbIcnpwOlt8cdJbpylvo26fYDvz3UnRoRjsYljsYljscnTZrrBbIfBlKrqXOBcgCTjM/0/nr+oHItNHItNHItNHItNksz4n8fP9jTRWuCAnuVlrUySNIdmOwy+BRya5OAkOwOnAJfPch8kSZuZ1WmiqnosyZ8CVwALgI9W1U3b2OTc2enZDsGx2MSx2MSx2MSx2GTGY5Gq2h4dkSTtQPwGsiTJMJAkjXAYzOfLViT5aJINvd+xSLJ3kiuT3NJu95rLPs6WJAckuSbJzUluSvKqVj7vxiPJLkn+Lsnft7F4eys/OMl17bnyqfbhjF94SRYkuT7JF9vyvBwHgCS3JbkhyXcmPlY60+fISIaBl63g48Bxm5WdAVxVVYcCV7Xl+eAx4LVVdThwDPDK9rcwH8fjx8CLquoZwBHAcUmOAd4NnF1VhwD3A6fNYR9n06uA1T3L83UcJrywqo7o+a7FjJ4jIxkGzPPLVlTV14H7NiteAZzf7p8PnDSrnZojVbWuqr7d7j9M9+Rfyjwcj+o80hZ3aj8FvAi4tJXPi7FIsgx4CfCRthzm4ThMYUbPkVENg61dtmLpHPVlVOxbVeva/XuAfeeyM3MhyUHAM4HrmKfj0aZGvgNsAK4E/h/wQFU91qrMl+fK+4HXA0+05cXMz3GYUMBXk6xql/SBGT5HRu5yFJpaVVWSefWZ4CS7A58BXl1VD3VvBDvzaTyq6nHgiCSLgM8Bh81xl2ZdkpcCG6pqVZIXzHV/RsRzq2ptkl8Crkzyvd6V03mOjOqRgZet2NL6JPsBtNsNc9yfWZNkJ7oguKiqPtuK5+14AFTVA8A1wLOBRUkm3tjNh+fKc4DfTXIb3RTyi4BzmH/j8DNVtbbdbqB7k3A0M3yOjGoYeNmKLV0OrGz3VwKXzWFfZk2bCz4PWF1V7+tZNe/GI8mSdkRAkqcAv0N3DuUa4GWt2i/8WFTVG6tqWVUdRPfacHVVvZx5Ng4TkuyW5KkT94EXAzcyw+fIyH4DOckJdPOCE5etOGuOuzRrklwMvIDukrzrgbcCnwcuAQ4EbgdOrqrNTzL/wknyXOAbwA1smh9+E915g3k1Hkn+Od2JwAV0b+Quqap3JPkVunfIewPXA39YVT+eu57OnjZN9Lqqeul8HYf2uD/XFhcCn6iqs5IsZgbPkZENA0nS7BnVaSJJ0iwyDCRJhoEkyTCQJGEYSJIwDCRJGAaSJOD/Az15XOWF/4x9AAAAAElFTkSuQmCC\n",
+ "text/plain": [
+ "<matplotlib.figure.Figure at 0xaefaa6b0>"
+ ]
+ },
+ "metadata": {},
+ "output_type": "display_data"
+ }
+ ],
+ "source": [
+ "import time\n",
+ "import matplotlib.pyplot as plt\n",
+ "\n",
+ "length = 50\n",
+ "time_log = []\n",
+ "for i in range(length):\n",
+ " start = time.time()\n",
+ " ol.download()\n",
+ " end = time.time()\n",
+ " time_log.append((end-start)*1000)\n",
+ "\n",
+ "%matplotlib inline\n",
+ "plt.plot(range(length), time_log, 'ro')\n",
+ "plt.title('Bitstream loading time (ms)')\n",
+ "plt.axis([0, length, 0, 1000])\n",
+ "plt.show()"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": []
+ }
+ ],
+ "metadata": {
+ "kernelspec": {
+ "display_name": "Python 3",
+ "language": "python",
+ "name": "python3"
+ },
+ "language_info": {
+ "codemirror_mode": {
+ "name": "ipython",
+ "version": 3
+ },
+ "file_extension": ".py",
+ "mimetype": "text/x-python",
+ "name": "python",
+ "nbconvert_exporter": "python",
+ "pygments_lexer": "ipython3",
+ "version": "3.6.5"
+ }
+ },
+ "nbformat": 4,
+ "nbformat_minor": 1
+}
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/pynq_export/pz2/jupyter_notebooks/soclabs/driver/uartlite.py b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/pynq_export/pz2/jupyter_notebooks/soclabs/driver/uartlite.py
new file mode 100755
index 0000000..4da3b33
--- /dev/null
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/pynq_export/pz2/jupyter_notebooks/soclabs/driver/uartlite.py
@@ -0,0 +1,88 @@
+from time import sleep, time
+from pynq import MMIO
+
+RX_FIFO = 0x00
+TX_FIFO = 0x04
+
+#Status Reg
+STAT_REG = 0x08
+RX_VALID = 0
+RX_FULL = 1
+TX_EMPTY = 2
+TX_FULL = 3
+IS_INTR = 4
+OVERRUN_ERR = 5
+FRAME_ERR = 6
+PARITY_ERR =7
+
+#Ctrl Reg
+CTRL_REG = 0x0C
+RST_TX = 0
+RST_RX = 1
+INTR_EN = 4
+
+class UartLite:
+ def __init__(self, address):
+ # Setup axi core
+ self.uart = MMIO(address,0x10000, debug=False)
+ self.address = address
+
+ def getBit(self,num,pos):
+ return (num&1<<pos)>>pos
+
+ def setupCtrlReg(self):
+ # Reset FIFOs, disable interrupts
+ self.uart.write(CTRL_REG, 1<<RST_TX | 1<<RST_RX)
+ sleep(0.0)
+ self.uart.write(CTRL_REG,0)
+ sleep(0.0)
+
+ def currentStatus(self):
+ """Returns object that specifies current status of axi core"""
+ status = self.uart.read(STAT_REG)
+ return {'RX_VALID':self.getBit(status,RX_VALID),
+ 'RX_FULL':self.getBit(status, RX_FULL),
+ 'TX_EMPTY':self.getBit(status, TX_EMPTY),
+ 'TX_FULL':self.getBit(status, TX_FULL),
+ 'IS_INTR':self.getBit(status, IS_INTR),
+ 'OVERRUN_ERR':self.getBit(status, OVERRUN_ERR),
+ 'FRAME_ERR':self.getBit(status, FRAME_ERR),
+ 'PARITY_ERR':self.getBit(status, PARITY_ERR)}
+
+ def read(self, count, timeout = 1):
+ buf = ""
+ stop_time = time() + timeout
+ for i in range(count):
+ # Wait till RX fifo has valid data, skip if timeout exceeded
+ while (not (self.uart.read(STAT_REG) & 1<<RX_VALID)) and (time()<stop_time):
+ pass
+ if time()>=stop_time:
+ break
+ buf += chr(self.uart.read(RX_FIFO))
+ return buf
+
+ def write(self, buf, timeout = 10):
+ """
+ buf: iterable
+
+ """
+ stop_time = time() + timeout
+ wr_count = 0
+ for i in buf:
+ #Wait while TX FIFO is Full, stop waiting if timeout passes
+ while (self.uart.read(STAT_REG) & 1<<TX_FULL) and (time()<stop_time):
+ pass
+ # Check timeout
+ if time()>stop_time:
+ break
+ self.uart.write(TX_FIFO, ord(i))
+ wr_count += 1
+ return wr_count
+
+ def readLine(self):
+ buf = self.read(1)
+ if len(buf) ==0:
+ return ""
+ while '\n' not in buf:
+ buf += self.read(1)
+ return buf
\ No newline at end of file
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/pynq_export/pz2/jupyter_notebooks/soclabs/soclabs_cm0sdk_mcu.ipynb b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/pynq_export/pz2/jupyter_notebooks/soclabs/soclabs_cm0sdk_mcu.ipynb
new file mode 100755
index 0000000..4a2d262
--- /dev/null
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/pynq_export/pz2/jupyter_notebooks/soclabs/soclabs_cm0sdk_mcu.ipynb
@@ -0,0 +1,372 @@
+{
+ "cells": [
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "# SoCLabs cm0sdk mcu overlay\n",
+ "This notebook demonstrates how to download the FPGA overlay and communicate with programmable logic state. \n",
+ "\n",
+ "## 1. Instantiating an overlay\n",
+ "With the following overlay bundle present in the `overlays` folder, users can instantiate the overlay easily.\n",
+ "\n",
+ "* A bitstream file (\\*.bit).\n",
+ "* An hwh file (\\*.hwh).\n",
+ "* A python class (\\*.py).\n",
+ "\n",
+ "For example, a `soclabs` overlay called `design_1` can be loaded by:\n",
+ "```python\n",
+ "from pynq.overlays.base import BaseOverlay\n",
+ "overlay = BaseOverlay(\"soclabs/design_1.bit\")\n",
+ "```\n",
+ "A `drivers` directory is provided for device driver templates for comms channels. (uartlite example).\n",
+ "\n",
+ "Users can also use the absolute file path of the bitstream to instantiate the overlay.\n",
+ "\n",
+ "In this notebook, we get the current bitstream loaded on PL, and try to download it multiple times."
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 1,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "application/javascript": [
+ "\n",
+ "try {\n",
+ "require(['notebook/js/codecell'], function(codecell) {\n",
+ " codecell.CodeCell.options_default.highlight_modes[\n",
+ " 'magic_text/x-csrc'] = {'reg':[/^%%microblaze/]};\n",
+ " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n",
+ " Jupyter.notebook.get_cells().map(function(cell){\n",
+ " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n",
+ " });\n",
+ "});\n",
+ "} catch (e) {};\n"
+ ]
+ },
+ "metadata": {},
+ "output_type": "display_data"
+ },
+ {
+ "data": {
+ "application/javascript": [
+ "\n",
+ "try {\n",
+ "require(['notebook/js/codecell'], function(codecell) {\n",
+ " codecell.CodeCell.options_default.highlight_modes[\n",
+ " 'magic_text/x-csrc'] = {'reg':[/^%%pybind11/]};\n",
+ " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n",
+ " Jupyter.notebook.get_cells().map(function(cell){\n",
+ " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n",
+ " });\n",
+ "});\n",
+ "} catch (e) {};\n"
+ ]
+ },
+ "metadata": {},
+ "output_type": "display_data"
+ }
+ ],
+ "source": [
+ "import os, warnings\n",
+ "from pynq import PL\n",
+ "from pynq import Overlay\n",
+ "\n",
+ "from pynq import MMIO\n",
+ "\n",
+ "import sys\n",
+ "sys.path.insert(1, './driver')\n",
+ "from uartlite import *\n",
+ "\n",
+ "ol = Overlay(\"/home/xilinx/pynq/overlays/soclabs/design_1.bit\")\n",
+ "\n",
+ "if not os.path.exists(PL.bitfile_name):\n",
+ " warnings.warn('There is no overlay loaded after boot.', UserWarning)"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "**Note**: If you see a warning message in the above cell, it means that no overlay\n",
+ "has been loaded after boot, hence the PL server is not aware of the \n",
+ "current status of the PL. In that case you won't be able to run this notebook\n",
+ "until you manually load an overlay at least once using:\n",
+ "\n",
+ "```python\n",
+ "from pynq import Overlay\n",
+ "ol = Overlay('your_overlay.bit')\n",
+ "```\n",
+ "\n",
+ "If you do not see any warning message, you can safely proceed.\n",
+ "\n",
+ "Next try relative path:"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 2,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "from pynq import Overlay\n",
+ "ol = Overlay(\"soclabs/design_1.bit\")"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Now we can check the download timestamp for this overlay."
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 3,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "text/plain": [
+ "'2022/7/12 13:24:34 +609181'"
+ ]
+ },
+ "execution_count": 3,
+ "metadata": {},
+ "output_type": "execute_result"
+ }
+ ],
+ "source": [
+ "ol.download()\n",
+ "ol.timestamp"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "## 2. Examining the PL state\n",
+ "\n",
+ "While there can be multiple overlay instances in Python, there is only one bitstream that is currently loaded onto the programmable logic (PL). \n",
+ "\n",
+ "This bitstream state is held in the singleton class, PL, and is available for user queries."
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 4,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "text/plain": [
+ "'/usr/local/lib/python3.6/dist-packages/pynq/overlays/soclabs/design_1.bit'"
+ ]
+ },
+ "execution_count": 4,
+ "metadata": {},
+ "output_type": "execute_result"
+ }
+ ],
+ "source": [
+ "PL.bitfile_name"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 5,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "text/plain": [
+ "'2022/7/12 13:24:34 +609181'"
+ ]
+ },
+ "execution_count": 5,
+ "metadata": {},
+ "output_type": "execute_result"
+ }
+ ],
+ "source": [
+ "PL.timestamp"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Users can verify whether an overlay instance is currently loaded using the Overlay is_loaded() method"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 6,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "text/plain": [
+ "True"
+ ]
+ },
+ "execution_count": 6,
+ "metadata": {},
+ "output_type": "execute_result"
+ }
+ ],
+ "source": [
+ "ol.is_loaded()"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "## 3. Establishing communications \n",
+ "Next set up a serial channel (configured for 9600 baud clocking rate).\n",
+ "Re-download image which also resets the MCU design in PL.\n",
+ "(No explicit to reinitialize the UART after HW reset, as preconfigured baud rate).\n",
+ "Poll for start-up banner from MCU internal boot-ROM.\n",
+ "\n",
+ "Expect a message of the form (sometimes characters are lost as uartlite has no no flow-control support)\n",
+ "\n",
+ "```python\n",
+ " SOCLABS: ARM Cortex-M0 SDK\n",
+ " - load flash\n",
+ "```"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 7,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "\n",
+ "SOCLABS: ARM Cortex-M0 SDK\n",
+ " - load flash\n",
+ "\n",
+ "\n"
+ ]
+ }
+ ],
+ "source": [
+ "# Address of the uart core\n",
+ "ADDRESS = 0x42C00000\n",
+ "uart = UartLite(ADDRESS)\n",
+ "ol.download()\n",
+ "# Setup AXI UART register\n",
+ "#uart.setupCtrlReg()\n",
+ "#print(uart.readLine())\n",
+ "#print(uart.readLine())\n",
+ "#print(uart.readLine())\n",
+ "print(uart.read(45,1))"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 8,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "{'RX_VALID': 0, 'RX_FULL': 0, 'TX_EMPTY': 1, 'TX_FULL': 0, 'IS_INTR': 0, 'OVERRUN_ERR': 0, 'FRAME_ERR': 0, 'PARITY_ERR': 0}\n"
+ ]
+ }
+ ],
+ "source": [
+ "print(uart.currentStatus())"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 9,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "#ol.ip_dict"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "## 3. Overlay downloading overhead\n",
+ "\n",
+ "Finally, using Python, we can see the bitstream download time over 50 downloads. "
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 10,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "image/png": 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TuHeA/UuShqTvI4OqemNVLauqg4BTgKur6uXANcDLWrWVwGXt/uVtmbb+6qqqfvcvSRqe7fE9gzcAr0myhu6cwHmt/DxgcSt/DXDGdti3JKkPg0wT/UxVXQtc2+7fChy9lTo/An5vGPuTJA2X30CWJBkGkiTDQJKEYSBJwjCQJGEYSJIwDCRJGAaSJAwDSRKGgSQJw0CShGEgScIwkCRhGEiSMAwkSRgGkiQMA0kShoEkCcNAkoRhIEnCMJAkYRhIkjAMJEkYBpIkDANJEoaBJAnDQJKEYSBJwjCQJGEYSJIwDCRJGAaSJAwDSRKGgSSJAcIgyQFJrklyc5Kbkryqle+d5Mokt7TbvVp5knwgyZok301y5LAehCRpMIMcGTwGvLaqDgeOAV6Z5HDgDOCqqjoUuKotAxwPHNp+Tgc+NMC+JUlD1HcYVNW6qvp2u/8wsBpYCqwAzm/VzgdOavdXABdU55vAoiT79d1zSdLQDOWcQZKDgGcC1wH7VtW6tuoeYN92fylwZ89md7Wyzds6Pcl4kvGNGzcOo3uSpCkMHAZJdgc+A7y6qh7qXVdVBdRM2quqc6tqrKrGlixZMmj3JEnTMFAYJNmJLgguqqrPtuL1E9M/7XZDK18LHNCz+bJWJkmaY4N8mijAecDqqnpfz6rLgZXt/krgsp7yU9unio4BHuyZTpIkzaGFA2z7HOCPgBuSfKeVvQl4F3BJktOA24GT27ovAScAa4AfAq8YYN+SpCHqOwyq6m+ATLL62K3UL+CV/e5PkrT9+A1kSZJhIEkyDCRJGAaSJAwDSRKGgSQJw0CShGEgScIwkCRhGEiSMAwkSYx6GKxaBQcdBBddNL36F13U1X/Sk2a2XT8m29co9KHf/vW7bpj9m82+j3p7O3LfR7292d7XZGbz9WIqVTWyP0dBFVTtumvVhRd2/zDzwgurli+vSrrb3vJdd+3qb77dZNtsq71+9vUnfzJ5HwbZVz+Pd6b966e9bY3tIO3NRt9Hvb0due+j3t6O8Bzp5zWhBzA+09fbGVWe7Z+jegdp4kFPNnjLl/98+cTP4sXD/+VOtq8FC7ZePlXf+/nDnKwPy5f3179+2tvW2PbT3mz2fdTb25H7Purt7QjPkX7fcA4QBum2G01jSY1PLCRw4IFw++1bVly+HO64oxua6Vq+vLudrL1trZvpvqbq+2T7WrAAHn98Zn1Iu6r4TPs32Tb9tNdv/0ah76PS3o7c91FvbxT6PtVzZLLXi229Jtx2W08TWVVVY9PvEDtQGPQ7eJMZ5A+pn1/UsF+8hx0uk22zrXXD7t9s9n3U29uR+z7q7e0Iz5F+3nA+8UTP4szDYEaHEXM2TTTIYdXixcM97Ov3EG7Yh6yjMB+6rbEd9bncUW9vR+77qLe3IzxH+nlNGHCaaEaV5yQMBj3hMuw/ln5P7gz7D3Nb++qnf/2s63eMRqHvO0J7O3LfR7292drXIK8js3zOYM5f8Lf1c9RRR9UWtvXLmMz2+EPqx7D/MEfBqPdPmmv9PkcGeE3oJwxG+5zB2FiNj49PXVGS9DP9nDMY7S+dSZJmhWEgSTIMJEmGgSQJw0CShGEgScIwkCRhGEiSMAwkSRgGkiQMA0kShoEkCcNAkoRhIEnCMJAkMQdhkOS4JP+QZE2SM2Z7/5KkLc1qGCRZAPwP4HjgcOD3kxw+m32QJG1pto8MjgbWVNWtVfUT4JPAilnugyRpMwtneX9LgTt7lu8CntVbIcnpwOlt8cdJbpylvo26fYDvz3UnRoRjsYljsYljscnTZrrBbIfBlKrqXOBcgCTjM/0/nr+oHItNHItNHItNHItNksz4n8fP9jTRWuCAnuVlrUySNIdmOwy+BRya5OAkOwOnAJfPch8kSZuZ1WmiqnosyZ8CVwALgI9W1U3b2OTc2enZDsGx2MSx2MSx2MSx2GTGY5Gq2h4dkSTtQPwGsiTJMJAkjXAYzOfLViT5aJINvd+xSLJ3kiuT3NJu95rLPs6WJAckuSbJzUluSvKqVj7vxiPJLkn+Lsnft7F4eys/OMl17bnyqfbhjF94SRYkuT7JF9vyvBwHgCS3JbkhyXcmPlY60+fISIaBl63g48Bxm5WdAVxVVYcCV7Xl+eAx4LVVdThwDPDK9rcwH8fjx8CLquoZwBHAcUmOAd4NnF1VhwD3A6fNYR9n06uA1T3L83UcJrywqo7o+a7FjJ4jIxkGzPPLVlTV14H7NiteAZzf7p8PnDSrnZojVbWuqr7d7j9M9+Rfyjwcj+o80hZ3aj8FvAi4tJXPi7FIsgx4CfCRthzm4ThMYUbPkVENg61dtmLpHPVlVOxbVeva/XuAfeeyM3MhyUHAM4HrmKfj0aZGvgNsAK4E/h/wQFU91qrMl+fK+4HXA0+05cXMz3GYUMBXk6xql/SBGT5HRu5yFJpaVVWSefWZ4CS7A58BXl1VD3VvBDvzaTyq6nHgiCSLgM8Bh81xl2ZdkpcCG6pqVZIXzHV/RsRzq2ptkl8Crkzyvd6V03mOjOqRgZet2NL6JPsBtNsNc9yfWZNkJ7oguKiqPtuK5+14AFTVA8A1wLOBRUkm3tjNh+fKc4DfTXIb3RTyi4BzmH/j8DNVtbbdbqB7k3A0M3yOjGoYeNmKLV0OrGz3VwKXzWFfZk2bCz4PWF1V7+tZNe/GI8mSdkRAkqcAv0N3DuUa4GWt2i/8WFTVG6tqWVUdRPfacHVVvZx5Ng4TkuyW5KkT94EXAzcyw+fIyH4DOckJdPOCE5etOGuOuzRrklwMvIDukrzrgbcCnwcuAQ4EbgdOrqrNTzL/wknyXOAbwA1smh9+E915g3k1Hkn+Od2JwAV0b+Quqap3JPkVunfIewPXA39YVT+eu57OnjZN9Lqqeul8HYf2uD/XFhcCn6iqs5IsZgbPkZENA0nS7BnVaSJJ0iwyDCRJhoEkyTCQJGEYSJIwDCRJGAaSJOD/Az15XOWF/4x9AAAAAElFTkSuQmCC\n",
+ "text/plain": [
+ "<matplotlib.figure.Figure at 0xaefaa6b0>"
+ ]
+ },
+ "metadata": {},
+ "output_type": "display_data"
+ }
+ ],
+ "source": [
+ "import time\n",
+ "import matplotlib.pyplot as plt\n",
+ "\n",
+ "length = 50\n",
+ "time_log = []\n",
+ "for i in range(length):\n",
+ " start = time.time()\n",
+ " ol.download()\n",
+ " end = time.time()\n",
+ " time_log.append((end-start)*1000)\n",
+ "\n",
+ "%matplotlib inline\n",
+ "plt.plot(range(length), time_log, 'ro')\n",
+ "plt.title('Bitstream loading time (ms)')\n",
+ "plt.axis([0, length, 0, 1000])\n",
+ "plt.show()"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": []
+ }
+ ],
+ "metadata": {
+ "kernelspec": {
+ "display_name": "Python 3",
+ "language": "python",
+ "name": "python3"
+ },
+ "language_info": {
+ "codemirror_mode": {
+ "name": "ipython",
+ "version": 3
+ },
+ "file_extension": ".py",
+ "mimetype": "text/x-python",
+ "name": "python",
+ "nbconvert_exporter": "python",
+ "pygments_lexer": "ipython3",
+ "version": "3.6.5"
+ }
+ },
+ "nbformat": 4,
+ "nbformat_minor": 1
+}
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/build_mcu_fpga_ip.tcl b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/build_mcu_fpga_ip.tcl
new file mode 100644
index 0000000..b72943d
--- /dev/null
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/build_mcu_fpga_ip.tcl
@@ -0,0 +1,113 @@
+###-----------------------------------------------------------------------------
+### example: build_mcu_fpga_ip.tcl
+### A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+###
+### Contributors
+###
+### David Flynn (d.w.flynn@soton.ac.uk)
+###
+### Copyright © 2022, SoC Labs (www.soclabs.org)
+###-----------------------------------------------------------------------------
+#
+# developed & tested using vivado_version 2021.1
+#
+# usage:
+# vivado -mode tcl -source scripts/build_mcu_fpga_ip.tcl
+
+#
+# STEP#0: define output directory area.
+#
+
+set outputDir ./vivado/built_mcu_fpga
+file mkdir $outputDir
+#
+# STEP#1: setup design sources and constraints
+#
+
+# local search path for configurations
+set search_path ../verilog
+
+set cortexm0_vlog ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical
+source scripts/rtl_source_cm0.tcl
+
+set search_path [ concat $search_path $cortexm0_vlog/cortexm0_integration/verilog ]
+read_verilog [ glob $cortexm0_vlog/cortexm0_integration/verilog/*.v ]
+read_verilog [ glob $cortexm0_vlog/models/cells/*.v ]
+
+# Arm unmodified CMSDK RTL
+set cmsdk_vlog ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0
+source scripts/rtl_source_cmsdk.tcl
+
+set search_path [ concat $search_path $cmsdk_vlog/logical/models/memories ]
+read_verilog $cmsdk_vlog/logical/models/memories/cmsdk_ahb_memory_models_defs.v
+read_verilog $cmsdk_vlog/logical/models/memories/cmsdk_ahb_rom.v
+read_verilog $cmsdk_vlog/logical/models/memories/cmsdk_fpga_rom.v
+read_verilog $cmsdk_vlog/logical/models/memories/cmsdk_ahb_ram.v
+read_verilog $cmsdk_vlog/logical/models/memories/cmsdk_fpga_sram.v
+
+# ADP, FT1248 and streamio IP
+source scripts/rtl_source_soclabs_ip.tcl
+
+## FPGA-specific pads
+#source scripts/rtl_source_fpga_ip.tcl
+
+# soclabs modified mcu system
+set soc_vlog ../verilog
+read_verilog $soc_vlog/cmsdk_mcu_defs.v
+read_verilog $soc_vlog/ahb_bootrom.v
+read_verilog $soc_vlog/bootrom.v
+read_verilog $soc_vlog/cmsdk_ahb_cs_rom_table.v
+read_verilog $soc_vlog/cmsdk_apb_usrt.v
+read_verilog $soc_vlog/cmsdk_mcu_addr_decode.v
+read_verilog $soc_vlog/cmsdk_mcu_clkctrl.v
+read_verilog $soc_vlog/cmsdk_mcu_pin_mux.v
+read_verilog $soc_vlog/cmsdk_mcu_stclkctrl.v
+read_verilog $soc_vlog/cmsdk_mcu_sysctrl.v
+read_verilog $soc_vlog/cmsdk_mcu_system.v
+read_verilog $soc_vlog/cmsdk_mcu_chip.v
+
+# FPGA specific timing constraints
+#read_xdc target_fpga/fpga_timing.xdc
+
+## FPGA board specific pin constraints
+#read_xdc target_fpga/fpga_pinmap.xdc
+
+#
+# STEP#2: run synthesis, report utilization and timing estimates, write checkpoint design
+#
+
+update_compile_order -fileset sources_1
+
+set mculib_ip ../../../../../MCULIB
+
+ipx::package_project -root_dir $mculib_ip -vendor soclabs.org -library user -taxonomy /UserIP -import_files -set_current false -force
+
+ipx::unload_core $mculib_ip/component.xml
+ipx::edit_ip_in_project -upgrade true -name tmp_edit_project -directory $mculib_ip $mculib_ip/component.xml
+
+update_compile_order -fileset sources_1
+set_property ipi_drc {ignore_freq_hz true} [ipx::current_core]
+ipx::merge_project_changes files [ipx::current_core]
+
+set_property core_revision 2 [ipx::current_core]
+ipx::update_source_project_archive -component [ipx::current_core]
+ipx::create_xgui_files [ipx::current_core]
+ipx::update_checksums [ipx::current_core]
+ipx::check_integrity [ipx::current_core]
+
+ipx::save_core [ipx::current_core]
+ipx::check_integrity -quiet -xrt [ipx::current_core]
+ipx::archive_core $mculib_ip/soclabs.org_user_cmsdk_mcu_chip_1.0.zip [ipx::current_core]
+ipx::move_temp_component_back -component [ipx::current_core]
+close_project -delete
+
+#set_property ip_repo_paths {/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo /home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/MCULIB} [current_project]
+set_property ip_repo_paths {/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo ../../../../../MCULIB} [current_project]
+update_ip_catalog
+close_project
+
+#create_project project_2 /home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/project_2 -part xczu7ev-ffvc1156-2-e
+#set_property board_part xilinx.com:zcu104:part0:1.1 [current_project]
+#set_property coreContainer.enable 1 [current_project]
+#set_property ip_repo_paths /home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo [current_project]
+#update_ip_catalog
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/build_mcu_fpga_pynq_z2.tcl b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/build_mcu_fpga_pynq_z2.tcl
new file mode 100644
index 0000000..1adae9b
--- /dev/null
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/build_mcu_fpga_pynq_z2.tcl
@@ -0,0 +1,117 @@
+###-----------------------------------------------------------------------------
+### example: build_mcu_fpga_pynq_z2.tcl
+### A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+###
+### Contributors
+###
+### David Flynn (d.w.flynn@soton.ac.uk)
+###
+### Copyright © 2022, SoC Labs (www.soclabs.org)
+###-----------------------------------------------------------------------------
+#
+# developed & tested using vivado_version 2021.1
+#
+# usage:
+# vivado -mode tcl -source scripts/build_mcu_fpga_pynq_z2.tcl
+# vivado -mode gui -source scripts/build_mcu_fpga_pynq_z2.tcl
+
+# for TUL PYNQ-Z2 as PYNQ target
+set xilinx_part xc7z020clg400-1
+set project project_pynq_z2
+set importDir target_fpga_pynq_z2
+set pynqDir pynq_export/pz2/pynq/overlays/soclabs
+set exportDir /research/soclabs/pynq_export/pz2/pynq/overlays/soclabs
+#set_property BOARD_PART tul.com:pynq-z2:part0:1.1 [current_project]
+
+#
+# STEP#0: build the cm0sdk design (without pads) as an "IP" library component for the testbench (in MCULIB)
+#
+source scripts/build_mcu_fpga_ip.tcl
+
+#
+# STEP#1: setup design sources and constraints
+#
+set_part $xilinx_part
+set_property TARGET_LANGUAGE Verilog [current_project]
+set_property DEFAULT_LIB work [current_project]
+
+set paths [list \
+ "../../../../../../../soclabs/fpga/vivado/pynq/ip_repo"\
+ "../../../../../MCULIB"\
+ ]
+
+# Set IP repository paths
+set obj [get_filesets sources_1]
+if { $obj != {} } {
+ set_property "ip_repo_paths" "[file normalize "../../../../../../../soclabs/fpga/vivado/pynq/ip_repo"] [file normalize "../../../../../MCULIB"]" $obj
+
+ # Rebuild user ip_repo's index before adding any source files
+ update_ip_catalog -rebuild
+}
+
+report_ip_status
+
+#
+# STEP#2: create Block Diagram and add specific IO wrapper (and import matching pinmap.xdc)
+#
+# using script written out from GUI capture
+
+create_bd_design design_1
+
+read_verilog $importDir/design_1_wrapper.v
+source $importDir/design_1.tcl
+create_root_design ""
+
+add_files -norecurse -scan_for_includes ../verilog/cmsdk_mcu_defs.v
+set_property is_global_include true [get_files ../verilog/cmsdk_mcu_defs.v]
+
+add_files -norecurse -scan_for_includes {../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/memories/cmsdk_ahb_memory_models_defs.v ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v}
+set_property is_global_include true [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/memories/cmsdk_ahb_memory_models_defs.v]
+set_property is_global_include true [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v]
+set_property is_global_include true [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v]
+
+set_property file_type {Verilog Header} [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/memories/cmsdk_ahb_memory_models_defs.v]
+set_property file_type {Verilog Header} [get_files ../../../../../../soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_defs.v]
+set_property file_type {Verilog Header} [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v]
+set_property file_type {Verilog Header} [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v]
+
+add_files $importDir/fpga_pinmap.xdc
+
+#
+# STEP#3: save in Project mode to complete flow
+#
+save_project_as $project ./$project -exclude_run_results -force
+
+update_compile_order -fileset sources_1
+
+#
+# STEP#4: synthesize project
+#
+set_property part $xilinx_part [get_runs synth_1]
+launch_runs synth_1 -jobs 8
+
+wait_on_run synth_1
+
+#
+# STEP#5: place and route project
+#
+set_property part $xilinx_part [get_runs impl_1]
+launch_runs impl_1 -to_step write_bitstream -jobs 8
+
+wait_on_run impl_1
+
+#
+# STEP#6: export design_1.bit and design_1.hwh files for PYNQ
+#
+
+write_hw_platform -fixed -include_bit -force -file $project/design_1.xsa
+
+exec unzip -u -o $project/design_1.xsa -d $project/export
+
+exec mkdir -p $pynqDir
+exec cp -p $project/export/design_1.bit $pynqDir
+exec cp -p $project/export/design_1.hwh $pynqDir
+exec cp -p $project/export/design_1.bit $exportDir
+exec cp -p $project/export/design_1.hwh $exportDir
+
+exit 1
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/build_mcu_fpga_pynq_zcu104.tcl b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/build_mcu_fpga_pynq_zcu104.tcl
new file mode 100644
index 0000000..fd31c73
--- /dev/null
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/build_mcu_fpga_pynq_zcu104.tcl
@@ -0,0 +1,117 @@
+###-----------------------------------------------------------------------------
+### example: build_mcu_fpga_pynq_zcu104.tcl
+### A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+###
+### Contributors
+###
+### David Flynn (d.w.flynn@soton.ac.uk)
+###
+### Copyright © 2022, SoC Labs (www.soclabs.org)
+###-----------------------------------------------------------------------------
+#
+# developed & tested using vivado_version 2021.1
+#
+# usage:
+# vivado -mode tcl -source scripts/build_mcu_fpga_pynq_zcu104.tcl
+# vivado -mode gui -source scripts/build_mcu_fpga_pynq_zcu104.tcl
+
+# for Xilinx ZCU104 as PYNQ target
+set xilinx_part xczu7ev-ffvc1156-2-e
+set project project_pynq_zcu104
+set importDir target_fpga_zcu104
+set exportDir /research/soclabs/pynq_export/pz104/pynq/overlays/soclabs
+set pynqDir pynq_export/pz104/pynq/overlays/soclabs
+#set_property BOARD_PART xilinx.com:zcu104:part0:1.1 [current_project]
+
+#
+# STEP#0: build the cm0sdk design (without pads) as an "IP" library component for the testbench (in MCULIB)
+#
+source scripts/build_mcu_fpga_ip.tcl
+
+#
+# STEP#1: setup design sources and constraints
+#
+set_part $xilinx_part
+set_property TARGET_LANGUAGE Verilog [current_project]
+set_property DEFAULT_LIB work [current_project]
+
+set paths [list \
+ "../../../../../../../soclabs/fpga/vivado/pynq/ip_repo"\
+ "../../../../../MCULIB"\
+ ]
+
+# Set IP repository paths
+set obj [get_filesets sources_1]
+if { $obj != {} } {
+ set_property "ip_repo_paths" "[file normalize "../../../../../../../soclabs/fpga/vivado/pynq/ip_repo"] [file normalize "../../../../../MCULIB"]" $obj
+
+ # Rebuild user ip_repo's index before adding any source files
+ update_ip_catalog -rebuild
+}
+
+report_ip_status
+
+#
+# STEP#2: create Block Diagram and add specific IO wrapper (and import matching pinmap.xdc)
+#
+# using script written out from GUI capture
+
+create_bd_design design_1
+
+read_verilog $importDir/design_1_wrapper.v
+source $importDir/design_1.tcl
+create_root_design ""
+
+add_files -norecurse -scan_for_includes ../verilog/cmsdk_mcu_defs.v
+set_property is_global_include true [get_files ../verilog/cmsdk_mcu_defs.v]
+
+add_files -norecurse -scan_for_includes {../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/memories/cmsdk_ahb_memory_models_defs.v ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v}
+set_property is_global_include true [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/memories/cmsdk_ahb_memory_models_defs.v]
+set_property is_global_include true [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v]
+set_property is_global_include true [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v]
+
+set_property file_type {Verilog Header} [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/memories/cmsdk_ahb_memory_models_defs.v]
+set_property file_type {Verilog Header} [get_files ../../../../../../soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_defs.v]
+set_property file_type {Verilog Header} [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v]
+set_property file_type {Verilog Header} [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v]
+
+add_files $importDir/fpga_pinmap.xdc
+
+#
+# STEP#3: save in Project mode to complete flow
+#
+
+save_project_as $project ./$project -exclude_run_results -force
+
+update_compile_order -fileset sources_1
+
+#
+# STEP#4: synthesize project
+#
+set_property part $xilinx_part [get_runs synth_1]
+launch_runs synth_1 -jobs 8
+
+wait_on_run synth_1
+
+#
+# STEP#5: place and route project
+#
+set_property part $xilinx_part [get_runs impl_1]
+launch_runs impl_1 -to_step write_bitstream -jobs 8
+
+wait_on_run impl_1
+
+#
+# STEP#6: export design_1.bit and design_1.hwh files for PYNQ
+#
+
+write_hw_platform -fixed -include_bit -force -file $project/design_1.xsa
+
+exec unzip -u -o $project/design_1.xsa -d $project/export
+exec mkdir -p $pynqDir
+exec cp -p $project/export/design_1.bit $pynqDir
+exec cp -p $project/export/design_1.hwh $pynqDir
+exec cp -p $project/export/design_1.bit $exportDir
+exec cp -p $project/export/design_1.hwh $exportDir
+
+exit 1
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_pynq_z2/design_1.tcl b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_pynq_z2/design_1.tcl
new file mode 100644
index 0000000..b56045d
--- /dev/null
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_pynq_z2/design_1.tcl
@@ -0,0 +1,508 @@
+
+################################################################
+# This is a generated script based on design: design_1
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+ set script_path [file normalize [info script]]
+ set script_folder [file dirname $script_path]
+ return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2021.1
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+ puts ""
+ catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+ return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source design_1_script.tcl
+
+set bCheckIPsPassed 1
+##################################################################
+# CHECK IPs
+##################################################################
+set bCheckIPs 1
+if { $bCheckIPs == 1 } {
+ set list_check_ips "\
+soclabs.org:user:cmsdk_mcu_chip:1.0\
+xilinx.com:ip:processing_system7:5.5\
+xilinx.com:ip:axi_gpio:2.0\
+xilinx.com:ip:axi_uartlite:2.0\
+xilinx.com:ip:xlslice:1.0\
+xilinx.com:ip:xlconcat:2.1\
+xilinx.com:ip:proc_sys_reset:5.0\
+xilinx.com:ip:smartconnect:1.0\
+xilinx.com:ip:xlconstant:1.1\
+"
+
+ set list_ips_missing ""
+ common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+ foreach ip_vlnv $list_check_ips {
+ set ip_obj [get_ipdefs -all $ip_vlnv]
+ if { $ip_obj eq "" } {
+ lappend list_ips_missing $ip_vlnv
+ }
+ }
+
+ if { $list_ips_missing ne "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+ set bCheckIPsPassed 0
+ }
+
+}
+
+if { $bCheckIPsPassed != 1 } {
+ common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
+ return 3
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+# Hierarchical cell: cmsdk_socket
+proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
+
+ variable script_folder
+
+ if { $parentCell eq "" || $nameHier eq "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_cmsdk_socket() - Empty argument(s)!"}
+ return
+ }
+
+ # Get object for parentCell
+ set parentObj [get_bd_cells $parentCell]
+ if { $parentObj == "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+ return
+ }
+
+ # Make sure parentObj is hier blk
+ set parentType [get_property TYPE $parentObj]
+ if { $parentType ne "hier" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+ return
+ }
+
+ # Save current instance; Restore later
+ set oldCurInst [current_bd_instance .]
+
+ # Set parent object as current
+ current_bd_instance $parentObj
+
+ # Create cell and set as current instance
+ set hier_obj [create_bd_cell -type hier $nameHier]
+ current_bd_instance $hier_obj
+
+ # Create interface pins
+ create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S00_AXI
+
+
+ # Create pins
+ create_bd_pin -dir I -type clk aclk
+ create_bd_pin -dir I -type rst ext_reset_in
+ create_bd_pin -dir O -from 15 -to 0 gpio2_tri_o
+ create_bd_pin -dir I -from 15 -to 0 gpio2_tri_z
+ create_bd_pin -dir O -from 15 -to 0 gpio_tri_i
+ create_bd_pin -dir I -from 15 -to 0 gpio_tri_o
+ create_bd_pin -dir O -from 0 -to 0 -type rst nrst
+ create_bd_pin -dir O -from 15 -to 0 p0_tri_i
+ create_bd_pin -dir I -from 15 -to 0 p0_tri_o
+ create_bd_pin -dir I -from 15 -to 0 p0_tri_z
+ create_bd_pin -dir O -from 15 -to 0 p1_tri_i
+ create_bd_pin -dir I -from 15 -to 0 p1_tri_o
+ create_bd_pin -dir I -from 15 -to 0 p1_tri_z
+ create_bd_pin -dir I -from 7 -to 0 pmoda_tri_i
+ create_bd_pin -dir O -from 7 -to 0 pmoda_tri_o
+ create_bd_pin -dir O -from 7 -to 0 pmoda_tri_z
+
+ # Create instance: axi_gpio_0, and set properties
+ set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ]
+ set_property -dict [ list \
+ CONFIG.C_GPIO2_WIDTH {16} \
+ CONFIG.C_GPIO_WIDTH {16} \
+ CONFIG.C_IS_DUAL {1} \
+ ] $axi_gpio_0
+
+ # Create instance: axi_gpio_1, and set properties
+ set axi_gpio_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_1 ]
+ set_property -dict [ list \
+ CONFIG.C_GPIO2_WIDTH {16} \
+ CONFIG.C_GPIO_WIDTH {16} \
+ CONFIG.C_IS_DUAL {1} \
+ ] $axi_gpio_1
+
+ # Create instance: axi_gpio_2, and set properties
+ set axi_gpio_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_2 ]
+ set_property -dict [ list \
+ CONFIG.C_GPIO2_WIDTH {16} \
+ CONFIG.C_GPIO_WIDTH {16} \
+ CONFIG.C_IS_DUAL {1} \
+ ] $axi_gpio_2
+
+ # Create instance: axi_uartlite_0, and set properties
+ set axi_uartlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_0 ]
+ set_property -dict [ list \
+ CONFIG.C_S_AXI_ACLK_FREQ_HZ {20000000} \
+ ] $axi_uartlite_0
+
+ # Create instance: p1_i_bit15to6, and set properties
+ set p1_i_bit15to6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_i_bit15to6 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {15} \
+ CONFIG.DIN_TO {6} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {10} \
+ ] $p1_i_bit15to6
+
+ # Create instance: p1_i_concat, and set properties
+ set p1_i_concat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 p1_i_concat ]
+ set_property -dict [ list \
+ CONFIG.IN0_WIDTH {1} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {1} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.IN5_WIDTH {1} \
+ CONFIG.IN6_WIDTH {10} \
+ CONFIG.NUM_PORTS {7} \
+ ] $p1_i_concat
+
+ # Create instance: p1_o_bit1, and set properties
+ set p1_o_bit1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit1 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {1} \
+ CONFIG.DIN_TO {1} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_o_bit1
+
+ # Create instance: p1_o_bit15to6, and set properties
+ set p1_o_bit15to6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit15to6 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {15} \
+ CONFIG.DIN_TO {6} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {10} \
+ ] $p1_o_bit15to6
+
+ # Create instance: p1_o_bit2, and set properties
+ set p1_o_bit2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit2 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {2} \
+ CONFIG.DIN_TO {2} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_o_bit2
+
+ # Create instance: p1_o_bit3, and set properties
+ set p1_o_bit3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit3 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {3} \
+ CONFIG.DIN_TO {3} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_o_bit3
+
+ # Create instance: p1_o_bit5, and set properties
+ set p1_o_bit5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit5 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {5} \
+ CONFIG.DIN_TO {5} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_o_bit5
+
+ # Create instance: p1_z_bit2, and set properties
+ set p1_z_bit2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_z_bit2 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {2} \
+ CONFIG.DIN_TO {2} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_z_bit2
+
+ # Create instance: pmoda_i_bit2, and set properties
+ set pmoda_i_bit2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit2 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {2} \
+ CONFIG.DIN_TO {2} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $pmoda_i_bit2
+
+ # Create instance: pmoda_i_bit3, and set properties
+ set pmoda_i_bit3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit3 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {3} \
+ CONFIG.DIN_TO {3} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $pmoda_i_bit3
+
+ # Create instance: pmoda_o_concat8, and set properties
+ set pmoda_o_concat8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmoda_o_concat8 ]
+ set_property -dict [ list \
+ CONFIG.NUM_PORTS {8} \
+ ] $pmoda_o_concat8
+
+ # Create instance: pmoda_z_concat8, and set properties
+ set pmoda_z_concat8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmoda_z_concat8 ]
+ set_property -dict [ list \
+ CONFIG.NUM_PORTS {8} \
+ ] $pmoda_z_concat8
+
+ # Create instance: proc_sys_reset_0, and set properties
+ set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ]
+
+ # Create instance: smartconnect_0, and set properties
+ set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ]
+ set_property -dict [ list \
+ CONFIG.NUM_MI {4} \
+ CONFIG.NUM_SI {1} \
+ ] $smartconnect_0
+
+ # Create instance: xlconstant_0, and set properties
+ set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ]
+ set_property -dict [ list \
+ CONFIG.CONST_VAL {0} \
+ ] $xlconstant_0
+
+ # Create instance: xlconstant_1, and set properties
+ set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ]
+
+ # Create interface connections
+ connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins smartconnect_0/M00_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins axi_gpio_1/S_AXI] [get_bd_intf_pins smartconnect_0/M01_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M02_AXI [get_bd_intf_pins axi_gpio_2/S_AXI] [get_bd_intf_pins smartconnect_0/M02_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M03_AXI [get_bd_intf_pins axi_uartlite_0/S_AXI] [get_bd_intf_pins smartconnect_0/M03_AXI]
+ connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_LPD [get_bd_intf_pins S00_AXI] [get_bd_intf_pins smartconnect_0/S00_AXI]
+
+ # Create port connections
+ connect_bd_net -net UART2_TXD [get_bd_pins axi_uartlite_0/rx] [get_bd_pins p1_o_bit5/Dout]
+ connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins p0_tri_i] [get_bd_pins axi_gpio_0/gpio_io_o]
+ connect_bd_net -net axi_gpio_1_gpio_io_o [get_bd_pins axi_gpio_1/gpio_io_o] [get_bd_pins p1_i_bit15to6/Din]
+ connect_bd_net -net axi_gpio_2_gpio2_io_o [get_bd_pins gpio2_tri_o] [get_bd_pins axi_gpio_2/gpio2_io_o]
+ connect_bd_net -net axi_gpio_2_gpio_io_o [get_bd_pins gpio_tri_i] [get_bd_pins axi_gpio_2/gpio_io_o]
+ connect_bd_net -net axi_uartlite_0_tx [get_bd_pins axi_uartlite_0/tx] [get_bd_pins p1_i_concat/In4]
+ connect_bd_net -net cmsdk_mcu_chip_0_p0_o [get_bd_pins p0_tri_o] [get_bd_pins axi_gpio_0/gpio_io_i]
+ connect_bd_net -net cmsdk_mcu_chip_0_p0_z [get_bd_pins p0_tri_z] [get_bd_pins axi_gpio_0/gpio2_io_i]
+ connect_bd_net -net cmsdk_mcu_chip_0_p1_o [get_bd_pins p1_tri_o] [get_bd_pins axi_gpio_1/gpio_io_i] [get_bd_pins p1_o_bit1/Din] [get_bd_pins p1_o_bit15to6/Din] [get_bd_pins p1_o_bit2/Din] [get_bd_pins p1_o_bit3/Din] [get_bd_pins p1_o_bit5/Din]
+ connect_bd_net -net cmsdk_mcu_chip_0_swdio_o [get_bd_pins gpio_tri_o] [get_bd_pins axi_gpio_2/gpio_io_i]
+ connect_bd_net -net cmsdk_mcu_chip_0_swdio_z [get_bd_pins gpio2_tri_z] [get_bd_pins axi_gpio_2/gpio2_io_i]
+ connect_bd_net -net const0 [get_bd_pins p1_i_concat/In1] [get_bd_pins p1_i_concat/In3] [get_bd_pins p1_i_concat/In5] [get_bd_pins pmoda_o_concat8/In2] [get_bd_pins pmoda_o_concat8/In4] [get_bd_pins pmoda_o_concat8/In5] [get_bd_pins pmoda_o_concat8/In6] [get_bd_pins pmoda_o_concat8/In7] [get_bd_pins pmoda_z_concat8/In0] [get_bd_pins pmoda_z_concat8/In1] [get_bd_pins xlconstant_0/dout]
+ connect_bd_net -net const1 [get_bd_pins pmoda_z_concat8/In2] [get_bd_pins pmoda_z_concat8/In4] [get_bd_pins pmoda_z_concat8/In5] [get_bd_pins pmoda_z_concat8/In6] [get_bd_pins pmoda_z_concat8/In7] [get_bd_pins xlconstant_1/dout]
+ connect_bd_net -net ftclk_o [get_bd_pins p1_o_bit1/Dout] [get_bd_pins pmoda_o_concat8/In0]
+ connect_bd_net -net ftmiosio_o [get_bd_pins p1_o_bit2/Dout] [get_bd_pins pmoda_o_concat8/In3]
+ connect_bd_net -net ftmiosio_z [get_bd_pins p1_z_bit2/Dout] [get_bd_pins pmoda_z_concat8/In3]
+ connect_bd_net -net ftssn_n [get_bd_pins p1_o_bit3/Dout] [get_bd_pins pmoda_o_concat8/In1]
+ connect_bd_net -net p1_i [get_bd_pins p1_tri_i] [get_bd_pins p1_i_concat/dout]
+ connect_bd_net -net p1_i_bit15to6_Dout [get_bd_pins p1_i_bit15to6/Dout] [get_bd_pins p1_i_concat/In6]
+ connect_bd_net -net p1_z [get_bd_pins p1_tri_z] [get_bd_pins axi_gpio_1/gpio2_io_i] [get_bd_pins p1_z_bit2/Din]
+ connect_bd_net -net pmoda_i_1 [get_bd_pins pmoda_tri_i] [get_bd_pins pmoda_i_bit2/Din] [get_bd_pins pmoda_i_bit3/Din]
+ connect_bd_net -net pmoda_i_bit2_Dout [get_bd_pins p1_i_concat/In0] [get_bd_pins pmoda_i_bit2/Dout]
+ connect_bd_net -net pmoda_i_bit3_Dout [get_bd_pins p1_i_concat/In2] [get_bd_pins pmoda_i_bit3/Dout]
+ connect_bd_net -net pmoda_o_concat9_dout [get_bd_pins pmoda_tri_z] [get_bd_pins pmoda_z_concat8/dout]
+ connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_gpio_2/s_axi_aresetn] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins smartconnect_0/aresetn]
+ connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins nrst] [get_bd_pins proc_sys_reset_0/peripheral_aresetn]
+ connect_bd_net -net xlconcat_0_dout [get_bd_pins pmoda_tri_o] [get_bd_pins pmoda_o_concat8/dout]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_gpio_2/s_axi_aclk] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins ext_reset_in] [get_bd_pins proc_sys_reset_0/ext_reset_in]
+
+ # Restore current instance
+ current_bd_instance $oldCurInst
+}
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+ variable script_folder
+
+ if { $parentCell eq "" } {
+ set parentCell [get_bd_cells /]
+ }
+
+ # Get object for parentCell
+ set parentObj [get_bd_cells $parentCell]
+ if { $parentObj == "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+ return
+ }
+
+ # Make sure parentObj is hier blk
+ set parentType [get_property TYPE $parentObj]
+ if { $parentType ne "hier" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+ return
+ }
+
+ # Save current instance; Restore later
+ set oldCurInst [current_bd_instance .]
+
+ # Set parent object as current
+ current_bd_instance $parentObj
+
+
+ # Create interface ports
+
+ # Create ports
+ set pmoda_tri_i [ create_bd_port -dir I -from 7 -to 0 pmoda_tri_i ]
+ set pmoda_tri_o [ create_bd_port -dir O -from 7 -to 0 pmoda_tri_o ]
+ set pmoda_tri_z [ create_bd_port -dir O -from 7 -to 0 pmoda_tri_z ]
+
+ # Create instance: cmsdk_mcu_chip_0, and set properties
+ set cmsdk_mcu_chip_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:cmsdk_mcu_chip:1.0 cmsdk_mcu_chip_0 ]
+
+ # Create instance: cmsdk_socket
+ create_hier_cell_cmsdk_socket [current_bd_instance .] cmsdk_socket
+
+ # Create instance: processing_system7_0, and set properties
+ set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
+ set_property -dict [ list \
+ CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \
+ CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \
+ CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {20.000000} \
+ CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
+ CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
+ CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \
+ CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
+ CONFIG.PCW_CLK0_FREQ {20000000} \
+ CONFIG.PCW_CLK1_FREQ {10000000} \
+ CONFIG.PCW_CLK2_FREQ {10000000} \
+ CONFIG.PCW_CLK3_FREQ {10000000} \
+ CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \
+ CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \
+ CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \
+ CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \
+ CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \
+ CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \
+ CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \
+ CONFIG.PCW_DDR_RAM_HIGHADDR {0x1FFFFFFF} \
+ CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
+ CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
+ CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {10} \
+ CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {8} \
+ CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \
+ CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \
+ CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \
+ CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {20} \
+ CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
+ CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \
+ CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \
+ CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \
+ CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {25} \
+ CONFIG.PCW_IOPLL_CTRL_FBDIV {48} \
+ CONFIG.PCW_IO_IO_PLL_FREQMHZ {1600.000} \
+ CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {8} \
+ CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \
+ ] $processing_system7_0
+
+ # Create interface connections
+ connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_pins cmsdk_socket/S00_AXI] [get_bd_intf_pins processing_system7_0/M_AXI_GP0]
+
+ # Create port connections
+ connect_bd_net -net cmsdk_mcu_chip_0_swdio_o [get_bd_pins cmsdk_mcu_chip_0/swdio_o] [get_bd_pins cmsdk_socket/gpio_tri_o]
+ connect_bd_net -net cmsdk_mcu_chip_0_swdio_z [get_bd_pins cmsdk_mcu_chip_0/swdio_z] [get_bd_pins cmsdk_socket/gpio2_tri_z]
+ connect_bd_net -net cmsdk_socket_gpio2_tri_o [get_bd_pins cmsdk_mcu_chip_0/swdclk_i] [get_bd_pins cmsdk_socket/gpio2_tri_o]
+ connect_bd_net -net cmsdk_socket_gpio_tri_i [get_bd_pins cmsdk_mcu_chip_0/swdio_i] [get_bd_pins cmsdk_socket/gpio_tri_i]
+ connect_bd_net -net cmsdk_socket_nrst [get_bd_pins cmsdk_mcu_chip_0/nrst_i] [get_bd_pins cmsdk_socket/nrst]
+ connect_bd_net -net cmsdk_socket_p0_tri_i [get_bd_pins cmsdk_mcu_chip_0/p0_i] [get_bd_pins cmsdk_socket/p0_tri_i]
+ connect_bd_net -net cmsdk_socket_p1_tri_i [get_bd_pins cmsdk_mcu_chip_0/p1_i] [get_bd_pins cmsdk_socket/p1_tri_i]
+ connect_bd_net -net p0_tri_o_1 [get_bd_pins cmsdk_mcu_chip_0/p0_o] [get_bd_pins cmsdk_socket/p0_tri_o]
+ connect_bd_net -net p0_tri_z_1 [get_bd_pins cmsdk_mcu_chip_0/p0_z] [get_bd_pins cmsdk_socket/p0_tri_z]
+ connect_bd_net -net p1_tri_o_1 [get_bd_pins cmsdk_mcu_chip_0/p1_o] [get_bd_pins cmsdk_socket/p1_tri_o]
+ connect_bd_net -net p1_tri_z_1 [get_bd_pins cmsdk_mcu_chip_0/p1_z] [get_bd_pins cmsdk_socket/p1_tri_z]
+ connect_bd_net -net pmoda_i_1 [get_bd_ports pmoda_tri_i] [get_bd_pins cmsdk_socket/pmoda_tri_i]
+ connect_bd_net -net pmoda_o_concat9_dout [get_bd_ports pmoda_tri_z] [get_bd_pins cmsdk_socket/pmoda_tri_z]
+ connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins cmsdk_mcu_chip_0/xtal_clk_i] [get_bd_pins cmsdk_socket/aclk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK]
+ connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins cmsdk_socket/ext_reset_in] [get_bd_pins processing_system7_0/FCLK_RESET0_N]
+ connect_bd_net -net xlconcat_0_dout [get_bd_ports pmoda_tri_o] [get_bd_pins cmsdk_socket/pmoda_tri_o]
+
+ # Create address segments
+ assign_bd_address -offset 0x41200000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x41210000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_1/S_AXI/Reg] -force
+ assign_bd_address -offset 0x41220000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_2/S_AXI/Reg] -force
+ assign_bd_address -offset 0x42C00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs cmsdk_socket/axi_uartlite_0/S_AXI/Reg] -force
+
+
+ # Restore current instance
+ current_bd_instance $oldCurInst
+
+}
+# End of create_root_design()
+
+
+
+
+proc available_tcl_procs { } {
+ puts "##################################################################"
+ puts "# Available Tcl procedures to recreate hierarchical blocks:"
+ puts "#"
+ puts "# create_hier_cell_cmsdk_socket parentCell nameHier"
+ puts "# create_root_design"
+ puts "#"
+ puts "#"
+ puts "# The following procedures will create hiearchical blocks with addressing "
+ puts "# for IPs within those blocks and their sub-hierarchical blocks. Addressing "
+ puts "# will not be handled outside those blocks:"
+ puts "#"
+ puts "# create_root_design"
+ puts "#"
+ puts "##################################################################"
+}
+
+available_tcl_procs
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_pynq_z2/design_1_wrapper.v b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_pynq_z2/design_1_wrapper.v
new file mode 100644
index 0000000..ce586c7
--- /dev/null
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_pynq_z2/design_1_wrapper.v
@@ -0,0 +1,107 @@
+//Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+//--------------------------------------------------------------------------------
+//Tool Version: Vivado v.2021.1 (lin64) Build 3247384 Thu Jun 10 19:36:07 MDT 2021
+//Date : Wed Jun 22 15:58:42 2022
+//Host : srv03335 running 64-bit Red Hat Enterprise Linux release 8.6 (Ootpa)
+//Command : generate_target design_1_wrapper.bd
+//Design : design_1_wrapper
+//Purpose : IP block netlist
+//--------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+module design_1_wrapper
+ (PMOD0_0,
+ PMOD0_1,
+ PMOD0_2,
+ PMOD0_3,
+ PMOD0_4,
+ PMOD0_5,
+ PMOD0_6,
+ PMOD0_7
+ );
+// PMOD1_0,
+// PMOD1_1,
+// PMOD1_2,
+// PMOD1_3,
+// PMOD1_4,
+// PMOD1_5,
+// PMOD1_6,
+// PMOD1_7,
+// dip_switch_4bits_tri_i,
+// led_4bits_tri_o);
+
+ inout wire PMOD0_0;
+ inout wire PMOD0_1;
+ inout wire PMOD0_2;
+ inout wire PMOD0_3;
+ inout wire PMOD0_4;
+ inout wire PMOD0_5;
+ inout wire PMOD0_6;
+ inout wire PMOD0_7;
+// inout wire PMOD1_0;
+// inout wire PMOD1_1;
+// inout wire PMOD1_2;
+// inout wire PMOD1_3;
+// inout wire PMOD1_4;
+// inout wire PMOD1_5;
+// inout wire PMOD1_6;
+// inout wire PMOD1_7;
+
+// input wire [3:0]dip_switch_4bits_tri_i;
+// output wire [3:0]led_4bits_tri_o;
+
+ wire [7:0]PMOD0_tri_i;
+ wire [7:0]PMOD0_tri_o;
+ wire [7:0]PMOD0_tri_z;
+
+ assign PMOD0_tri_i[0] = PMOD0_0;
+ assign PMOD0_tri_i[1] = PMOD0_1;
+ assign PMOD0_tri_i[2] = PMOD0_2;
+ assign PMOD0_tri_i[3] = PMOD0_3;
+ assign PMOD0_tri_i[4] = PMOD0_4;
+ assign PMOD0_tri_i[5] = PMOD0_5;
+ assign PMOD0_tri_i[6] = PMOD0_6;
+ assign PMOD0_tri_i[7] = PMOD0_7;
+
+ assign PMOD0_0 = PMOD0_tri_z[0] ? 1'bz : PMOD0_tri_o[0];
+ assign PMOD0_1 = PMOD0_tri_z[1] ? 1'bz : PMOD0_tri_o[1];
+ assign PMOD0_2 = PMOD0_tri_z[2] ? 1'bz : PMOD0_tri_o[2];
+ assign PMOD0_3 = PMOD0_tri_z[3] ? 1'bz : PMOD0_tri_o[3];
+ assign PMOD0_4 = PMOD0_tri_z[4] ? 1'bz : PMOD0_tri_o[4];
+ assign PMOD0_5 = PMOD0_tri_z[5] ? 1'bz : PMOD0_tri_o[5];
+ assign PMOD0_6 = PMOD0_tri_z[6] ? 1'bz : PMOD0_tri_o[6];
+ assign PMOD0_7 = PMOD0_tri_z[7] ? 1'bz : PMOD0_tri_o[7];
+
+// wire [7:0]PMOD1_tri_i;
+// wire [7:0]PMOD1_tri_o;
+// wire [7:0]PMOD1_tri_z;
+
+// assign PMOD1_tri_i[0] = PMOD1_0;
+// assign PMOD1_tri_i[1] = PMOD1_1;
+// assign PMOD1_tri_i[2] = PMOD1_2;
+// assign PMOD1_tri_i[3] = PMOD1_3;
+// assign PMOD1_tri_i[4] = PMOD1_4;
+// assign PMOD1_tri_i[5] = PMOD1_5;
+// assign PMOD1_tri_i[6] = PMOD1_6;
+// assign PMOD1_tri_i[7] = PMOD1_7;
+
+// assign PMOD1_0 = PMOD1_tri_z[0] ? 1'bz : PMOD1_tri_o[0];
+// assign PMOD1_1 = PMOD1_tri_z[1] ? 1'bz : PMOD1_tri_o[1];
+// assign PMOD1_2 = PMOD1_tri_z[2] ? 1'bz : PMOD1_tri_o[2];
+// assign PMOD1_3 = PMOD1_tri_z[3] ? 1'bz : PMOD1_tri_o[3];
+// assign PMOD1_4 = PMOD1_tri_z[4] ? 1'bz : PMOD1_tri_o[4];
+// assign PMOD1_5 = PMOD1_tri_z[5] ? 1'bz : PMOD1_tri_o[5];
+// assign PMOD1_6 = PMOD1_tri_z[6] ? 1'bz : PMOD1_tri_o[6];
+// assign PMOD1_7 = PMOD1_tri_z[7] ? 1'bz : PMOD1_tri_o[7];
+
+ design_1 design_1_i
+ (.pmoda_tri_i(PMOD0_tri_i),
+ .pmoda_tri_o(PMOD0_tri_o),
+ .pmoda_tri_z(PMOD0_tri_z)//,
+// .PMOD1_tri_i(PMOD1_tri_i),
+// .PMOD1_tri_o(PMOD1_tri_o),
+// .PMOD1_tri_z(PMOD1_tri_z),
+// .dip_switch_4bits_tri_i(dip_switch_4bits_tri_i),
+// .led_4bits_tri_o(led_4bits_tri_o)
+ );
+endmodule
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_pynq_z2/fpga_pinmap.xdc b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_pynq_z2/fpga_pinmap.xdc
index 2f049a7..ab99a9c 100644
--- a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_pynq_z2/fpga_pinmap.xdc
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_pynq_z2/fpga_pinmap.xdc
@@ -1,228 +1,32 @@
##################################################################################
## ##
-## TUL pynq_z2 XDC ##
+## PZ2 PMODA XDC ##
## ##
##################################################################################
-#set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_0]
-#set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_1]
-#set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_2]
-#set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_3]
-#set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_4]
-#set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_5]
-#set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_6]
-#set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_7]
-#set_property PACKAGE_PIN Y18 [get_ports PMOD0_0]
-#set_property PACKAGE_PIN Y19 [get_ports PMOD0_1]
-#set_property PACKAGE_PIN Y16 [get_ports PMOD0_2]
-#set_property PACKAGE_PIN Y17 [get_ports PMOD0_3]
-#set_property PACKAGE_PIN U18 [get_ports PMOD0_4]
-#set_property PACKAGE_PIN U19 [get_ports PMOD0_5]
-#set_property PACKAGE_PIN W18 [get_ports PMOD0_6]
-#set_property PACKAGE_PIN W19 [get_ports PMOD0_7]
-#set_property PULLUP true [get_ports PMOD0_2]
-#set_property PULLUP true [get_ports PMOD0_3]
-#set_property PULLUP true [get_ports PMOD0_4]
-#set_property PULLUP true [get_ports PMOD0_5]
-#set_property PULLUP true [get_ports PMOD0_6]
-#set_property PULLUP true [get_ports PMOD0_7]
-#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_0]
-#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_1]
-#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_2]
-#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_3]
-#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_4]
-#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_5]
-#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_6]
-#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_7]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_0]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_1]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_2]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_3]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_4]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_5]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_6]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_7]
+
+set_property PACKAGE_PIN Y18 [get_ports PMOD0_0]
+set_property PACKAGE_PIN Y19 [get_ports PMOD0_1]
+set_property PACKAGE_PIN Y16 [get_ports PMOD0_2]
+set_property PACKAGE_PIN Y17 [get_ports PMOD0_3]
+set_property PACKAGE_PIN U18 [get_ports PMOD0_4]
+set_property PACKAGE_PIN U19 [get_ports PMOD0_5]
+set_property PACKAGE_PIN W18 [get_ports PMOD0_6]
+set_property PACKAGE_PIN W19 [get_ports PMOD0_7]
+
+set_property PULLUP true [get_ports PMOD0_2]
+set_property PULLDOWN true [get_ports PMOD0_3]
+set_property PULLUP true [get_ports PMOD0_4]
+set_property PULLUP true [get_ports PMOD0_5]
+set_property PULLUP true [get_ports PMOD0_6]
+set_property PULLUP true [get_ports PMOD0_7]
-#PMODA pin0 : FTCLK
-#set_property PACKAGE_PIN J9 [get_ports PMOD1_0]
-#PMODA pin1 : FTSSN
-#set_property PACKAGE_PIN K9 [get_ports PMOD1_1]
-#PMODA pin2 : FTMISO
-#set_property PACKAGE_PIN K8 [get_ports PMOD1_2]
-#PMODA pin3 : FTMIOSIO
-#set_property PACKAGE_PIN L8 [get_ports PMOD1_3]
-#PMODA pin4 : UART2RXD
-#set_property PACKAGE_PIN L10 [get_ports PMOD1_4]
-#PMODA pin4 : UART2TXD
-#set_property PACKAGE_PIN M10 [get_ports PMOD1_5]
-#set_property PACKAGE_PIN M8 [get_ports PMOD1_6]
-#set_property PACKAGE_PIN M9 [get_ports PMOD1_7]
-
-#set_property PULLUP true [get_ports PMOD1_7]
-#set_property PULLUP true [get_ports PMOD1_6]
-#set_property PULLUP true [get_ports PMOD1_5]
-#set_property PULLUP true [get_ports PMOD1_4]
-#set_property PULLUP true [get_ports PMOD1_3]
-#set_property PULLUP true [get_ports PMOD1_2]
-#set_property PULLUP true [get_ports PMOD1_1]
-#set_property PULLUP true [get_ports PMOD1_0]
-
-set_property IOSTANDARD LVCMOS33 [get_ports XTAL1]
-set_property IOSTANDARD LVCMOS33 [get_ports XTAL2]
-set_property IOSTANDARD LVCMOS33 [get_ports NRST]
-set_property IOSTANDARD LVCMOS33 [get_ports SWCLKTCK]
-set_property IOSTANDARD LVCMOS33 [get_ports SWDIOTMS]
-
-set_property IOSTANDARD LVCMOS33 [get_ports {P0[0]} ]
-set_property IOSTANDARD LVCMOS33 [get_ports {P0[1]} ]
-set_property IOSTANDARD LVCMOS33 [get_ports {P0[2]} ]
-set_property IOSTANDARD LVCMOS33 [get_ports {P0[3]} ]
-set_property IOSTANDARD LVCMOS33 [get_ports {P0[4]} ]
-set_property IOSTANDARD LVCMOS33 [get_ports {P0[5]} ]
-set_property IOSTANDARD LVCMOS33 [get_ports {P0[6]} ]
-set_property IOSTANDARD LVCMOS33 [get_ports {P0[7]} ]
-set_property IOSTANDARD LVCMOS33 [get_ports {P0[8]} ]
-set_property IOSTANDARD LVCMOS33 [get_ports {P0[9]} ]
-set_property IOSTANDARD LVCMOS33 [get_ports {P0[10]} ]
-set_property IOSTANDARD LVCMOS33 [get_ports {P0[11]} ]
-set_property IOSTANDARD LVCMOS33 [get_ports {P0[12]} ]
-set_property IOSTANDARD LVCMOS33 [get_ports {P0[13]} ]
-set_property IOSTANDARD LVCMOS33 [get_ports {P0[14]} ]
-set_property IOSTANDARD LVCMOS33 [get_ports {P0[15]} ]
-
-set_property PULLUP true [get_ports {P0[0]} ]
-set_property PULLUP true [get_ports {P0[1]} ]
-set_property PULLUP true [get_ports {P0[2]} ]
-set_property PULLUP true [get_ports {P0[3]} ]
-set_property PULLUP true [get_ports {P0[4]} ]
-set_property PULLUP true [get_ports {P0[5]} ]
-set_property PULLUP true [get_ports {P0[6]} ]
-set_property PULLUP true [get_ports {P0[7]} ]
-set_property PULLUP true [get_ports {P0[8]} ]
-set_property PULLUP true [get_ports {P0[9]} ]
-set_property PULLUP true [get_ports {P0[10]} ]
-set_property PULLUP true [get_ports {P0[11]} ]
-set_property PULLUP true [get_ports {P0[12]} ]
-set_property PULLUP true [get_ports {P0[13]} ]
-set_property PULLUP true [get_ports {P0[14]} ]
-set_property PULLUP true [get_ports {P0[15]} ]
-
-set_property IOSTANDARD LVCMOS33 [get_ports {P1[0]} ]
-set_property IOSTANDARD LVCMOS33 [get_ports {P1[1]} ]
-set_property IOSTANDARD LVCMOS33 [get_ports {P1[2]} ]
-set_property IOSTANDARD LVCMOS33 [get_ports {P1[3]} ]
-set_property IOSTANDARD LVCMOS33 [get_ports {P1[4]} ]
-set_property IOSTANDARD LVCMOS33 [get_ports {P1[5]} ]
-set_property IOSTANDARD LVCMOS33 [get_ports {P1[6]} ]
-set_property IOSTANDARD LVCMOS33 [get_ports {P1[7]} ]
-set_property IOSTANDARD LVCMOS33 [get_ports {P1[8]} ]
-set_property IOSTANDARD LVCMOS33 [get_ports {P1[9]} ]
-set_property IOSTANDARD LVCMOS33 [get_ports {P1[10]} ]
-set_property IOSTANDARD LVCMOS33 [get_ports {P1[11]} ]
-set_property IOSTANDARD LVCMOS33 [get_ports {P1[12]} ]
-set_property IOSTANDARD LVCMOS33 [get_ports {P1[13]} ]
-set_property IOSTANDARD LVCMOS33 [get_ports {P1[14]} ]
-set_property IOSTANDARD LVCMOS33 [get_ports {P1[15]} ]
-
-set_property PULLUP true [get_ports {P1[0]} ]
-set_property PULLUP true [get_ports {P1[1]} ]
-set_property PULLUP true [get_ports {P1[2]} ]
-set_property PULLUP true [get_ports {P1[3]} ]
-set_property PULLUP true [get_ports {P1[4]} ]
-set_property PULLUP true [get_ports {P1[5]} ]
-set_property PULLUP true [get_ports {P1[6]} ]
-set_property PULLUP true [get_ports {P1[7]} ]
-set_property PULLUP true [get_ports {P1[8]} ]
-set_property PULLUP true [get_ports {P1[9]} ]
-set_property PULLUP true [get_ports {P1[10]} ]
-set_property PULLUP true [get_ports {P1[11]} ]
-set_property PULLUP true [get_ports {P1[12]} ]
-set_property PULLUP true [get_ports {P1[13]} ]
-set_property PULLUP true [get_ports {P1[14]} ]
-set_property PULLUP true [get_ports {P1[15]} ]
-
-
-### PMODA ###
-#set_property PACKAGE_PIN Y18 [get_ports PMOD0_0]
-#set_property PACKAGE_PIN Y19 [get_ports PMOD0_1]
-#set_property PACKAGE_PIN Y16 [get_ports PMOD0_2]
-#set_property PACKAGE_PIN Y17 [get_ports PMOD0_3]
-#set_property PACKAGE_PIN U18 [get_ports PMOD0_4]
-#set_property PACKAGE_PIN U19 [get_ports PMOD0_5]
-#set_property PACKAGE_PIN W18 [get_ports PMOD0_6]
-#set_property PACKAGE_PIN W19 [get_ports PMOD0_7]
-
-## low row, PMOD-FT1248
-#PMODAL pin1 to FTMISO
-set_property PACKAGE_PIN Y18 [get_ports {P1[0]}]
-#PMODAL pin2 to FTCLK
-set_property PACKAGE_PIN Y19 [get_ports {P1[1]}]
-#PMODAL pin3 to FTMIOSIO
-set_property PACKAGE_PIN Y16 [get_ports {P1[2]}]
-#PMODAL pin4 to FTSSN
-set_property PACKAGE_PIN Y17 [get_ports {P1[3]}]
-
-## upper row, AUP-SWD
-#PMODAU pin1 to SWDIO
-set_property PACKAGE_PIN U18 [get_ports SWDIOTMS]
-#PMODAU pin2 to CLK15MHz
-##set_property PACKAGE_PIN U19 [get_ports XTAL1]
-#PMODAU pin3 to CLK30MHz
-set_property PACKAGE_PIN W18 [get_ports XTAL1]
-#PMODAU pin1 to SWDIO
-set_property PACKAGE_PIN W19 [get_ports SWCLKTCK]
-set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets uPAD_XTAL_I/IOBUF3V3/O]
-
-set_property PULLDOWN [get_ports SWDIOTMS]
-set_property PULLDOWN [get_ports SWDIOTCK]
-set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets uPAD_SWDCLK_I/IOBUF3V3/O]
-
-### PMODB ###
-
-#set_property PACKAGE_PIN L10 [get_ports PMOD1_4]
-#set_property PACKAGE_PIN M10 [get_ports PMOD1_5]
-#set_property PACKAGE_PIN M8 [get_ports PMOD1_6]
-#set_property PACKAGE_PIN M9 [get_ports PMOD1_7]
-
-#PMODA pin4 : UART2RXD
-#PMODA pin4 : UART2TXD
-
-
-# LED0 to P0[0]
-set_property PACKAGE_PIN R14 [get_ports {P0[0]}]
-# LED1 to P0[1]
-set_property PACKAGE_PIN P14 [get_ports {P0[1]}]
-# LED2 to P0[2]
-set_property PACKAGE_PIN N16 [get_ports {P0[2]}]
-# LED3 to P0[3]
-set_property PACKAGE_PIN M14 [get_ports {P0[3]}]
-
-# SW0 to NRST (Down for active low)
-set_property PACKAGE_PIN M20 [get_ports NRST]
-
-# CLK125MHz (need dvider)
-##set_property PACKAGE_PIN H16 [get_ports XTAL1]
-
-## Vivado allocations
-set_property PACKAGE_PIN V17 [get_ports {P0[10]}]
-set_property PACKAGE_PIN R18 [get_ports {P0[11]}]
-set_property PACKAGE_PIN T17 [get_ports {P0[12]}]
-set_property PACKAGE_PIN R17 [get_ports {P0[13]}]
-set_property PACKAGE_PIN R16 [get_ports {P0[14]}]
-set_property PACKAGE_PIN W16 [get_ports {P0[15]}]
-set_property PACKAGE_PIN T19 [get_ports {P0[4]}]
-set_property PACKAGE_PIN P16 [get_ports {P0[5]}]
-set_property PACKAGE_PIN P15 [get_ports {P0[6]}]
-set_property PACKAGE_PIN P18 [get_ports {P0[7]}]
-set_property PACKAGE_PIN N17 [get_ports {P0[8]}]
-set_property PACKAGE_PIN V18 [get_ports {P0[9]}]
-set_property PACKAGE_PIN N20 [get_ports {P1[10]}]
-set_property PACKAGE_PIN P19 [get_ports {P1[11]}]
-set_property PACKAGE_PIN N18 [get_ports {P1[12]}]
-set_property PACKAGE_PIN U19 [get_ports {P1[13]}]
-set_property PACKAGE_PIN U15 [get_ports {P1[14]}]
-set_property PACKAGE_PIN U14 [get_ports {P1[15]}]
-set_property PACKAGE_PIN V16 [get_ports {P1[4]}]
-set_property PACKAGE_PIN W20 [get_ports {P1[5]}]
-set_property PACKAGE_PIN V20 [get_ports {P1[6]}]
-set_property PACKAGE_PIN U20 [get_ports {P1[7]}]
-set_property PACKAGE_PIN T20 [get_ports {P1[8]}]
-set_property PACKAGE_PIN P20 [get_ports {P1[9]}]
-set_property PACKAGE_PIN W15 [get_ports VDD]
-set_property PACKAGE_PIN V15 [get_ports VDDIO]
-set_property PACKAGE_PIN U17 [get_ports VSS]
-set_property PACKAGE_PIN T16 [get_ports VSSIO]
-set_property PACKAGE_PIN Y14 [get_ports XTAL2]
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_zcu104/design_1.tcl b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_zcu104/design_1.tcl
new file mode 100644
index 0000000..0f4fda4
--- /dev/null
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_zcu104/design_1.tcl
@@ -0,0 +1,1017 @@
+
+################################################################
+# This is a generated script based on design: design_1
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+ set script_path [file normalize [info script]]
+ set script_folder [file dirname $script_path]
+ return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2021.1
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+ puts ""
+ catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+ return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source design_1_script.tcl
+
+set bCheckIPsPassed 1
+##################################################################
+# CHECK IPs
+##################################################################
+set bCheckIPs 1
+if { $bCheckIPs == 1 } {
+ set list_check_ips "\
+soclabs.org:user:cmsdk_mcu_chip:1.0\
+xilinx.com:ip:zynq_ultra_ps_e:3.3\
+xilinx.com:ip:axi_gpio:2.0\
+xilinx.com:ip:axi_uartlite:2.0\
+xilinx.com:ip:xlslice:1.0\
+xilinx.com:ip:xlconcat:2.1\
+xilinx.com:ip:proc_sys_reset:5.0\
+xilinx.com:ip:smartconnect:1.0\
+xilinx.com:ip:xlconstant:1.1\
+"
+
+ set list_ips_missing ""
+ common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+ foreach ip_vlnv $list_check_ips {
+ set ip_obj [get_ipdefs -all $ip_vlnv]
+ if { $ip_obj eq "" } {
+ lappend list_ips_missing $ip_vlnv
+ }
+ }
+
+ if { $list_ips_missing ne "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+ set bCheckIPsPassed 0
+ }
+
+}
+
+if { $bCheckIPsPassed != 1 } {
+ common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
+ return 3
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+# Hierarchical cell: cmsdk_socket
+proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
+
+ variable script_folder
+
+ if { $parentCell eq "" || $nameHier eq "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_cmsdk_socket() - Empty argument(s)!"}
+ return
+ }
+
+ # Get object for parentCell
+ set parentObj [get_bd_cells $parentCell]
+ if { $parentObj == "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+ return
+ }
+
+ # Make sure parentObj is hier blk
+ set parentType [get_property TYPE $parentObj]
+ if { $parentType ne "hier" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+ return
+ }
+
+ # Save current instance; Restore later
+ set oldCurInst [current_bd_instance .]
+
+ # Set parent object as current
+ current_bd_instance $parentObj
+
+ # Create cell and set as current instance
+ set hier_obj [create_bd_cell -type hier $nameHier]
+ current_bd_instance $hier_obj
+
+ # Create interface pins
+ create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S00_AXI
+
+
+ # Create pins
+ create_bd_pin -dir I -type clk aclk
+ create_bd_pin -dir I -type rst ext_reset_in
+ create_bd_pin -dir O -from 15 -to 0 gpio2_tri_o
+ create_bd_pin -dir I -from 15 -to 0 gpio2_tri_z
+ create_bd_pin -dir O -from 15 -to 0 gpio_tri_i
+ create_bd_pin -dir I -from 15 -to 0 gpio_tri_o
+ create_bd_pin -dir O -from 0 -to 0 -type rst nrst
+ create_bd_pin -dir O -from 15 -to 0 p0_tri_i
+ create_bd_pin -dir I -from 15 -to 0 p0_tri_o
+ create_bd_pin -dir I -from 15 -to 0 p0_tri_z
+ create_bd_pin -dir O -from 15 -to 0 p1_tri_i
+ create_bd_pin -dir I -from 15 -to 0 p1_tri_o
+ create_bd_pin -dir I -from 15 -to 0 p1_tri_z
+ create_bd_pin -dir I -from 7 -to 0 pmoda_tri_i
+ create_bd_pin -dir O -from 7 -to 0 pmoda_tri_o
+ create_bd_pin -dir O -from 7 -to 0 pmoda_tri_z
+
+ # Create instance: axi_gpio_0, and set properties
+ set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ]
+ set_property -dict [ list \
+ CONFIG.C_GPIO2_WIDTH {16} \
+ CONFIG.C_GPIO_WIDTH {16} \
+ CONFIG.C_IS_DUAL {1} \
+ ] $axi_gpio_0
+
+ # Create instance: axi_gpio_1, and set properties
+ set axi_gpio_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_1 ]
+ set_property -dict [ list \
+ CONFIG.C_GPIO2_WIDTH {16} \
+ CONFIG.C_GPIO_WIDTH {16} \
+ CONFIG.C_IS_DUAL {1} \
+ ] $axi_gpio_1
+
+ # Create instance: axi_gpio_2, and set properties
+ set axi_gpio_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_2 ]
+ set_property -dict [ list \
+ CONFIG.C_GPIO2_WIDTH {16} \
+ CONFIG.C_GPIO_WIDTH {16} \
+ CONFIG.C_IS_DUAL {1} \
+ ] $axi_gpio_2
+
+ # Create instance: axi_uartlite_0, and set properties
+ set axi_uartlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_0 ]
+
+ # Create instance: p1_i_bit15to6, and set properties
+ set p1_i_bit15to6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_i_bit15to6 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {15} \
+ CONFIG.DIN_TO {6} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {10} \
+ ] $p1_i_bit15to6
+
+ # Create instance: p1_i_concat, and set properties
+ set p1_i_concat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 p1_i_concat ]
+ set_property -dict [ list \
+ CONFIG.IN0_WIDTH {1} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {1} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.IN5_WIDTH {1} \
+ CONFIG.IN6_WIDTH {10} \
+ CONFIG.NUM_PORTS {7} \
+ ] $p1_i_concat
+
+ # Create instance: p1_o_bit1, and set properties
+ set p1_o_bit1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit1 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {1} \
+ CONFIG.DIN_TO {1} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_o_bit1
+
+ # Create instance: p1_o_bit15to6, and set properties
+ set p1_o_bit15to6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit15to6 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {15} \
+ CONFIG.DIN_TO {6} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {10} \
+ ] $p1_o_bit15to6
+
+ # Create instance: p1_o_bit2, and set properties
+ set p1_o_bit2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit2 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {2} \
+ CONFIG.DIN_TO {2} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_o_bit2
+
+ # Create instance: p1_o_bit3, and set properties
+ set p1_o_bit3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit3 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {3} \
+ CONFIG.DIN_TO {3} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_o_bit3
+
+ # Create instance: p1_o_bit5, and set properties
+ set p1_o_bit5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit5 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {5} \
+ CONFIG.DIN_TO {5} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_o_bit5
+
+ # Create instance: p1_z_bit2, and set properties
+ set p1_z_bit2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_z_bit2 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {2} \
+ CONFIG.DIN_TO {2} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_z_bit2
+
+ # Create instance: pmoda_i_bit2, and set properties
+ set pmoda_i_bit2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit2 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {2} \
+ CONFIG.DIN_TO {2} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $pmoda_i_bit2
+
+ # Create instance: pmoda_i_bit3, and set properties
+ set pmoda_i_bit3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit3 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {3} \
+ CONFIG.DIN_TO {3} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $pmoda_i_bit3
+
+ # Create instance: pmoda_o_concat8, and set properties
+ set pmoda_o_concat8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmoda_o_concat8 ]
+ set_property -dict [ list \
+ CONFIG.NUM_PORTS {8} \
+ ] $pmoda_o_concat8
+
+ # Create instance: pmoda_z_concat8, and set properties
+ set pmoda_z_concat8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmoda_z_concat8 ]
+ set_property -dict [ list \
+ CONFIG.NUM_PORTS {8} \
+ ] $pmoda_z_concat8
+
+ # Create instance: proc_sys_reset_0, and set properties
+ set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ]
+
+ # Create instance: smartconnect_0, and set properties
+ set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ]
+ set_property -dict [ list \
+ CONFIG.NUM_MI {4} \
+ CONFIG.NUM_SI {1} \
+ ] $smartconnect_0
+
+ # Create instance: xlconstant_0, and set properties
+ set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ]
+ set_property -dict [ list \
+ CONFIG.CONST_VAL {0} \
+ ] $xlconstant_0
+
+ # Create instance: xlconstant_1, and set properties
+ set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ]
+
+ # Create interface connections
+ connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins smartconnect_0/M00_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins axi_gpio_1/S_AXI] [get_bd_intf_pins smartconnect_0/M01_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M02_AXI [get_bd_intf_pins axi_gpio_2/S_AXI] [get_bd_intf_pins smartconnect_0/M02_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M03_AXI [get_bd_intf_pins axi_uartlite_0/S_AXI] [get_bd_intf_pins smartconnect_0/M03_AXI]
+ connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_LPD [get_bd_intf_pins S00_AXI] [get_bd_intf_pins smartconnect_0/S00_AXI]
+
+ # Create port connections
+ connect_bd_net -net UART2_TXD [get_bd_pins axi_uartlite_0/rx] [get_bd_pins p1_o_bit5/Dout]
+ connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins p0_tri_i] [get_bd_pins axi_gpio_0/gpio_io_o]
+ connect_bd_net -net axi_gpio_1_gpio_io_o [get_bd_pins axi_gpio_1/gpio_io_o] [get_bd_pins p1_i_bit15to6/Din]
+ connect_bd_net -net axi_gpio_2_gpio2_io_o [get_bd_pins gpio2_tri_o] [get_bd_pins axi_gpio_2/gpio2_io_o]
+ connect_bd_net -net axi_gpio_2_gpio_io_o [get_bd_pins gpio_tri_i] [get_bd_pins axi_gpio_2/gpio_io_o]
+ connect_bd_net -net axi_uartlite_0_tx [get_bd_pins axi_uartlite_0/tx] [get_bd_pins p1_i_concat/In4]
+ connect_bd_net -net cmsdk_mcu_chip_0_p0_o [get_bd_pins p0_tri_o] [get_bd_pins axi_gpio_0/gpio_io_i]
+ connect_bd_net -net cmsdk_mcu_chip_0_p0_z [get_bd_pins p0_tri_z] [get_bd_pins axi_gpio_0/gpio2_io_i]
+ connect_bd_net -net cmsdk_mcu_chip_0_p1_o [get_bd_pins p1_tri_o] [get_bd_pins axi_gpio_1/gpio_io_i] [get_bd_pins p1_o_bit1/Din] [get_bd_pins p1_o_bit15to6/Din] [get_bd_pins p1_o_bit2/Din] [get_bd_pins p1_o_bit3/Din] [get_bd_pins p1_o_bit5/Din]
+ connect_bd_net -net cmsdk_mcu_chip_0_swdio_o [get_bd_pins gpio_tri_o] [get_bd_pins axi_gpio_2/gpio_io_i]
+ connect_bd_net -net cmsdk_mcu_chip_0_swdio_z [get_bd_pins gpio2_tri_z] [get_bd_pins axi_gpio_2/gpio2_io_i]
+ connect_bd_net -net const0 [get_bd_pins p1_i_concat/In1] [get_bd_pins p1_i_concat/In3] [get_bd_pins p1_i_concat/In5] [get_bd_pins pmoda_o_concat8/In2] [get_bd_pins pmoda_o_concat8/In4] [get_bd_pins pmoda_o_concat8/In5] [get_bd_pins pmoda_o_concat8/In6] [get_bd_pins pmoda_o_concat8/In7] [get_bd_pins pmoda_z_concat8/In0] [get_bd_pins pmoda_z_concat8/In1] [get_bd_pins xlconstant_0/dout]
+ connect_bd_net -net const1 [get_bd_pins pmoda_z_concat8/In2] [get_bd_pins pmoda_z_concat8/In4] [get_bd_pins pmoda_z_concat8/In5] [get_bd_pins pmoda_z_concat8/In6] [get_bd_pins pmoda_z_concat8/In7] [get_bd_pins xlconstant_1/dout]
+ connect_bd_net -net ftclk_o [get_bd_pins p1_o_bit1/Dout] [get_bd_pins pmoda_o_concat8/In0]
+ connect_bd_net -net ftmiosio_o [get_bd_pins p1_o_bit2/Dout] [get_bd_pins pmoda_o_concat8/In3]
+ connect_bd_net -net ftmiosio_z [get_bd_pins p1_z_bit2/Dout] [get_bd_pins pmoda_z_concat8/In3]
+ connect_bd_net -net ftssn_n [get_bd_pins p1_o_bit3/Dout] [get_bd_pins pmoda_o_concat8/In1]
+ connect_bd_net -net p1_i [get_bd_pins p1_tri_i] [get_bd_pins p1_i_concat/dout]
+ connect_bd_net -net p1_i_bit15to6_Dout [get_bd_pins p1_i_bit15to6/Dout] [get_bd_pins p1_i_concat/In6]
+ connect_bd_net -net p1_z [get_bd_pins p1_tri_z] [get_bd_pins axi_gpio_1/gpio2_io_i] [get_bd_pins p1_z_bit2/Din]
+ connect_bd_net -net pmoda_i_1 [get_bd_pins pmoda_tri_i] [get_bd_pins pmoda_i_bit2/Din] [get_bd_pins pmoda_i_bit3/Din]
+ connect_bd_net -net pmoda_i_bit2_Dout [get_bd_pins p1_i_concat/In0] [get_bd_pins pmoda_i_bit2/Dout]
+ connect_bd_net -net pmoda_i_bit3_Dout [get_bd_pins p1_i_concat/In2] [get_bd_pins pmoda_i_bit3/Dout]
+ connect_bd_net -net pmoda_o_concat9_dout [get_bd_pins pmoda_tri_z] [get_bd_pins pmoda_z_concat8/dout]
+ connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_gpio_2/s_axi_aresetn] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins smartconnect_0/aresetn]
+ connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins nrst] [get_bd_pins proc_sys_reset_0/peripheral_aresetn]
+ connect_bd_net -net xlconcat_0_dout [get_bd_pins pmoda_tri_o] [get_bd_pins pmoda_o_concat8/dout]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_gpio_2/s_axi_aclk] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins ext_reset_in] [get_bd_pins proc_sys_reset_0/ext_reset_in]
+
+ # Restore current instance
+ current_bd_instance $oldCurInst
+}
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+ variable script_folder
+
+ if { $parentCell eq "" } {
+ set parentCell [get_bd_cells /]
+ }
+
+ # Get object for parentCell
+ set parentObj [get_bd_cells $parentCell]
+ if { $parentObj == "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+ return
+ }
+
+ # Make sure parentObj is hier blk
+ set parentType [get_property TYPE $parentObj]
+ if { $parentType ne "hier" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+ return
+ }
+
+ # Save current instance; Restore later
+ set oldCurInst [current_bd_instance .]
+
+ # Set parent object as current
+ current_bd_instance $parentObj
+
+
+ # Create interface ports
+
+ # Create ports
+ set pmoda_tri_i [ create_bd_port -dir I -from 7 -to 0 pmoda_tri_i ]
+ set pmoda_tri_o [ create_bd_port -dir O -from 7 -to 0 pmoda_tri_o ]
+ set pmoda_tri_z [ create_bd_port -dir O -from 7 -to 0 pmoda_tri_z ]
+
+ # Create instance: cmsdk_mcu_chip_0, and set properties
+ set cmsdk_mcu_chip_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:cmsdk_mcu_chip:1.0 cmsdk_mcu_chip_0 ]
+
+ # Create instance: cmsdk_socket
+ create_hier_cell_cmsdk_socket [current_bd_instance .] cmsdk_socket
+
+ # Create instance: zynq_ultra_ps_e_0, and set properties
+ set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ]
+ set_property -dict [ list \
+ CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
+ CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
+ CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
+ CONFIG.PSU_DDR_RAM_HIGHADDR {0x7FFFFFFF} \
+ CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x00000002} \
+ CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
+ CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \
+ CONFIG.PSU_MIO_0_DIRECTION {out} \
+ CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_0_POLARITY {Default} \
+ CONFIG.PSU_MIO_16_DIRECTION {inout} \
+ CONFIG.PSU_MIO_16_POLARITY {Default} \
+ CONFIG.PSU_MIO_17_DIRECTION {inout} \
+ CONFIG.PSU_MIO_17_POLARITY {Default} \
+ CONFIG.PSU_MIO_18_DIRECTION {in} \
+ CONFIG.PSU_MIO_18_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_18_POLARITY {Default} \
+ CONFIG.PSU_MIO_18_SLEW {fast} \
+ CONFIG.PSU_MIO_19_DIRECTION {out} \
+ CONFIG.PSU_MIO_19_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_19_POLARITY {Default} \
+ CONFIG.PSU_MIO_1_DIRECTION {inout} \
+ CONFIG.PSU_MIO_1_POLARITY {Default} \
+ CONFIG.PSU_MIO_20_DIRECTION {out} \
+ CONFIG.PSU_MIO_20_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_20_POLARITY {Default} \
+ CONFIG.PSU_MIO_21_DIRECTION {in} \
+ CONFIG.PSU_MIO_21_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_21_POLARITY {Default} \
+ CONFIG.PSU_MIO_21_SLEW {fast} \
+ CONFIG.PSU_MIO_24_DIRECTION {out} \
+ CONFIG.PSU_MIO_24_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_24_POLARITY {Default} \
+ CONFIG.PSU_MIO_25_DIRECTION {in} \
+ CONFIG.PSU_MIO_25_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_25_POLARITY {Default} \
+ CONFIG.PSU_MIO_25_SLEW {fast} \
+ CONFIG.PSU_MIO_27_DIRECTION {out} \
+ CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_27_POLARITY {Default} \
+ CONFIG.PSU_MIO_28_DIRECTION {in} \
+ CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_28_POLARITY {Default} \
+ CONFIG.PSU_MIO_28_SLEW {fast} \
+ CONFIG.PSU_MIO_29_DIRECTION {out} \
+ CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_29_POLARITY {Default} \
+ CONFIG.PSU_MIO_2_DIRECTION {inout} \
+ CONFIG.PSU_MIO_2_POLARITY {Default} \
+ CONFIG.PSU_MIO_30_DIRECTION {in} \
+ CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_30_POLARITY {Default} \
+ CONFIG.PSU_MIO_30_SLEW {fast} \
+ CONFIG.PSU_MIO_3_DIRECTION {inout} \
+ CONFIG.PSU_MIO_3_POLARITY {Default} \
+ CONFIG.PSU_MIO_45_DIRECTION {in} \
+ CONFIG.PSU_MIO_45_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_45_POLARITY {Default} \
+ CONFIG.PSU_MIO_45_SLEW {fast} \
+ CONFIG.PSU_MIO_46_DIRECTION {inout} \
+ CONFIG.PSU_MIO_46_POLARITY {Default} \
+ CONFIG.PSU_MIO_47_DIRECTION {inout} \
+ CONFIG.PSU_MIO_47_POLARITY {Default} \
+ CONFIG.PSU_MIO_48_DIRECTION {inout} \
+ CONFIG.PSU_MIO_48_POLARITY {Default} \
+ CONFIG.PSU_MIO_49_DIRECTION {inout} \
+ CONFIG.PSU_MIO_49_POLARITY {Default} \
+ CONFIG.PSU_MIO_4_DIRECTION {inout} \
+ CONFIG.PSU_MIO_4_POLARITY {Default} \
+ CONFIG.PSU_MIO_50_DIRECTION {inout} \
+ CONFIG.PSU_MIO_50_POLARITY {Default} \
+ CONFIG.PSU_MIO_51_DIRECTION {out} \
+ CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_51_POLARITY {Default} \
+ CONFIG.PSU_MIO_52_DIRECTION {in} \
+ CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_52_POLARITY {Default} \
+ CONFIG.PSU_MIO_52_SLEW {fast} \
+ CONFIG.PSU_MIO_53_DIRECTION {in} \
+ CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_53_POLARITY {Default} \
+ CONFIG.PSU_MIO_53_SLEW {fast} \
+ CONFIG.PSU_MIO_54_DIRECTION {inout} \
+ CONFIG.PSU_MIO_54_POLARITY {Default} \
+ CONFIG.PSU_MIO_55_DIRECTION {in} \
+ CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_55_POLARITY {Default} \
+ CONFIG.PSU_MIO_55_SLEW {fast} \
+ CONFIG.PSU_MIO_56_DIRECTION {inout} \
+ CONFIG.PSU_MIO_56_POLARITY {Default} \
+ CONFIG.PSU_MIO_57_DIRECTION {inout} \
+ CONFIG.PSU_MIO_57_POLARITY {Default} \
+ CONFIG.PSU_MIO_58_DIRECTION {out} \
+ CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_58_POLARITY {Default} \
+ CONFIG.PSU_MIO_59_DIRECTION {inout} \
+ CONFIG.PSU_MIO_59_POLARITY {Default} \
+ CONFIG.PSU_MIO_5_DIRECTION {out} \
+ CONFIG.PSU_MIO_5_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_5_POLARITY {Default} \
+ CONFIG.PSU_MIO_60_DIRECTION {inout} \
+ CONFIG.PSU_MIO_60_POLARITY {Default} \
+ CONFIG.PSU_MIO_61_DIRECTION {inout} \
+ CONFIG.PSU_MIO_61_POLARITY {Default} \
+ CONFIG.PSU_MIO_62_DIRECTION {inout} \
+ CONFIG.PSU_MIO_62_POLARITY {Default} \
+ CONFIG.PSU_MIO_63_DIRECTION {inout} \
+ CONFIG.PSU_MIO_63_POLARITY {Default} \
+ CONFIG.PSU_MIO_64_DIRECTION {out} \
+ CONFIG.PSU_MIO_64_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_64_POLARITY {Default} \
+ CONFIG.PSU_MIO_65_DIRECTION {out} \
+ CONFIG.PSU_MIO_65_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_65_POLARITY {Default} \
+ CONFIG.PSU_MIO_66_DIRECTION {out} \
+ CONFIG.PSU_MIO_66_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_66_POLARITY {Default} \
+ CONFIG.PSU_MIO_67_DIRECTION {out} \
+ CONFIG.PSU_MIO_67_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_67_POLARITY {Default} \
+ CONFIG.PSU_MIO_68_DIRECTION {out} \
+ CONFIG.PSU_MIO_68_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_68_POLARITY {Default} \
+ CONFIG.PSU_MIO_69_DIRECTION {out} \
+ CONFIG.PSU_MIO_69_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_69_POLARITY {Default} \
+ CONFIG.PSU_MIO_6_DIRECTION {out} \
+ CONFIG.PSU_MIO_6_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_6_POLARITY {Default} \
+ CONFIG.PSU_MIO_70_DIRECTION {in} \
+ CONFIG.PSU_MIO_70_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_70_POLARITY {Default} \
+ CONFIG.PSU_MIO_70_SLEW {fast} \
+ CONFIG.PSU_MIO_71_DIRECTION {in} \
+ CONFIG.PSU_MIO_71_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_71_POLARITY {Default} \
+ CONFIG.PSU_MIO_71_SLEW {fast} \
+ CONFIG.PSU_MIO_72_DIRECTION {in} \
+ CONFIG.PSU_MIO_72_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_72_POLARITY {Default} \
+ CONFIG.PSU_MIO_72_SLEW {fast} \
+ CONFIG.PSU_MIO_73_DIRECTION {in} \
+ CONFIG.PSU_MIO_73_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_73_POLARITY {Default} \
+ CONFIG.PSU_MIO_73_SLEW {fast} \
+ CONFIG.PSU_MIO_74_DIRECTION {in} \
+ CONFIG.PSU_MIO_74_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_74_POLARITY {Default} \
+ CONFIG.PSU_MIO_74_SLEW {fast} \
+ CONFIG.PSU_MIO_75_DIRECTION {in} \
+ CONFIG.PSU_MIO_75_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_75_POLARITY {Default} \
+ CONFIG.PSU_MIO_75_SLEW {fast} \
+ CONFIG.PSU_MIO_76_DIRECTION {out} \
+ CONFIG.PSU_MIO_76_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_76_POLARITY {Default} \
+ CONFIG.PSU_MIO_77_DIRECTION {inout} \
+ CONFIG.PSU_MIO_77_POLARITY {Default} \
+ CONFIG.PSU_MIO_TREE_PERIPHERALS {Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad\
+SPI Flash#Feedback Clk##########I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1###CAN\
+1#CAN 1##DPAUX#DPAUX#DPAUX#DPAUX###############SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD\
+1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem\
+3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO\
+3}\
+ CONFIG.PSU_MIO_TREE_SIGNALS {sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#clk_for_lpbk##########scl_out#sda_out#rxd#txd#txd#rxd###phy_tx#phy_rx##dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in###############sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out}\
+ CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \
+ CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \
+ CONFIG.PSU__ACT_DDR_FREQ_MHZ {1050.000000} \
+ CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \
+ CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__CAN1__PERIPHERAL__IO {MIO 24 .. 25} \
+ CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1200.000000} \
+ CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \
+ CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \
+ CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
+ CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \
+ CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \
+ CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0.000000} \
+ CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \
+ CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {5} \
+ CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {525.000000} \
+ CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1067} \
+ CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+ CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \
+ CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
+ CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
+ CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {63} \
+ CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0.000000} \
+ CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \
+ CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {25.000000} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {0} \
+ CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.785715} \
+ CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {14} \
+ CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {300.000000} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {5} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {0} \
+ CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+ CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \
+ CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
+ CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {500.000000} \
+ CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {1} \
+ CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {6} \
+ CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \
+ CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {525.000000} \
+ CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.33} \
+ CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \
+ CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {90} \
+ CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.000000} \
+ CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {0} \
+ CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000000} \
+ CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {50.000000} \
+ CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {30} \
+ CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000000} \
+ CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \
+ CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500.000000} \
+ CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \
+ CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \
+ CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \
+ CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {125.000000} \
+ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \
+ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \
+ CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {1} \
+ CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {90} \
+ CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0.000000} \
+ CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \
+ CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \
+ CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000000} \
+ CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500000} \
+ CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \
+ CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \
+ CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {20.000000} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {25} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {3} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {20} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {4} \
+ CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {4} \
+ CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \
+ CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {125.000000} \
+ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \
+ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \
+ CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {45} \
+ CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.000000} \
+ CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {0} \
+ CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {7} \
+ CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.500000} \
+ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \
+ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \
+ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {7} \
+ CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {7} \
+ CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \
+ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \
+ CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000000} \
+ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {25} \
+ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {3} \
+ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \
+ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
+ CONFIG.PSU__DDRC__ADDR_MIRROR {0} \
+ CONFIG.PSU__DDRC__BANK_ADDR_COUNT {2} \
+ CONFIG.PSU__DDRC__BG_ADDR_COUNT {1} \
+ CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \
+ CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \
+ CONFIG.PSU__DDRC__CL {15} \
+ CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \
+ CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \
+ CONFIG.PSU__DDRC__COMPONENTS {Components} \
+ CONFIG.PSU__DDRC__CWL {14} \
+ CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \
+ CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \
+ CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \
+ CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \
+ CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \
+ CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \
+ CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {Normal (0-85)} \
+ CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \
+ CONFIG.PSU__DDRC__DEVICE_CAPACITY {4096 MBits} \
+ CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \
+ CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \
+ CONFIG.PSU__DDRC__DQMAP_0_3 {0} \
+ CONFIG.PSU__DDRC__DQMAP_12_15 {0} \
+ CONFIG.PSU__DDRC__DQMAP_16_19 {0} \
+ CONFIG.PSU__DDRC__DQMAP_20_23 {0} \
+ CONFIG.PSU__DDRC__DQMAP_24_27 {0} \
+ CONFIG.PSU__DDRC__DQMAP_28_31 {0} \
+ CONFIG.PSU__DDRC__DQMAP_32_35 {0} \
+ CONFIG.PSU__DDRC__DQMAP_36_39 {0} \
+ CONFIG.PSU__DDRC__DQMAP_40_43 {0} \
+ CONFIG.PSU__DDRC__DQMAP_44_47 {0} \
+ CONFIG.PSU__DDRC__DQMAP_48_51 {0} \
+ CONFIG.PSU__DDRC__DQMAP_4_7 {0} \
+ CONFIG.PSU__DDRC__DQMAP_52_55 {0} \
+ CONFIG.PSU__DDRC__DQMAP_56_59 {0} \
+ CONFIG.PSU__DDRC__DQMAP_60_63 {0} \
+ CONFIG.PSU__DDRC__DQMAP_64_67 {0} \
+ CONFIG.PSU__DDRC__DQMAP_68_71 {0} \
+ CONFIG.PSU__DDRC__DQMAP_8_11 {0} \
+ CONFIG.PSU__DDRC__DRAM_WIDTH {16 Bits} \
+ CONFIG.PSU__DDRC__ECC {Disabled} \
+ CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \
+ CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \
+ CONFIG.PSU__DDRC__FGRM {1X} \
+ CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \
+ CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {NA} \
+ CONFIG.PSU__DDRC__LP_ASR {manual normal} \
+ CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \
+ CONFIG.PSU__DDRC__PARITY_ENABLE {0} \
+ CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
+ CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
+ CONFIG.PSU__DDRC__ROW_ADDR_COUNT {15} \
+ CONFIG.PSU__DDRC__SB_TARGET {15-15-15} \
+ CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \
+ CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2133P} \
+ CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
+ CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
+ CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
+ CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
+ CONFIG.PSU__DDRC__T_FAW {30.0} \
+ CONFIG.PSU__DDRC__T_RAS_MIN {33} \
+ CONFIG.PSU__DDRC__T_RC {47.06} \
+ CONFIG.PSU__DDRC__T_RCD {15} \
+ CONFIG.PSU__DDRC__T_RP {15} \
+ CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \
+ CONFIG.PSU__DDRC__VREF {1} \
+ CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {0} \
+ CONFIG.PSU__DDR__INTERFACE__FREQMHZ {533.500} \
+ CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \
+ CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \
+ CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \
+ CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \
+ CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__DLL__ISUSED {1} \
+ CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \
+ CONFIG.PSU__DP__LANE_SEL {Dual Lower} \
+ CONFIG.PSU__DP__REF_CLK_FREQ {27} \
+ CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk3} \
+ CONFIG.PSU__ENET3__FIFO__ENABLE {0} \
+ CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \
+ CONFIG.PSU__ENET3__GRP_MDIO__IO {MIO 76 .. 77} \
+ CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__ENET3__PERIPHERAL__IO {MIO 64 .. 75} \
+ CONFIG.PSU__ENET3__PTP__ENABLE {0} \
+ CONFIG.PSU__ENET3__TSU__ENABLE {0} \
+ CONFIG.PSU__FPDMASTERS_COHERENCY {0} \
+ CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {100.000000} \
+ CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \
+ CONFIG.PSU__FPGA_PL0_ENABLE {1} \
+ CONFIG.PSU__GEM3_COHERENCY {0} \
+ CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \
+ CONFIG.PSU__GEM__TSU__ENABLE {0} \
+ CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__GT__LINK_SPEED {HBR} \
+ CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \
+ CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \
+ CONFIG.PSU__HIGH_ADDRESS__ENABLE {0} \
+ CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 16 .. 17} \
+ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \
+ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \
+ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \
+ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \
+ CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \
+ CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \
+ CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \
+ CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \
+ CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \
+ CONFIG.PSU__PL_CLK0_BUF {TRUE} \
+ CONFIG.PSU__PRESET_APPLIED {1} \
+ CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;0|SATA1:NonSecure;1|SATA0:NonSecure;1|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1}\
+ CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;1|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;0|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display\
+Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;800000000;0|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;1|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1}\
+ CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333333} \
+ CONFIG.PSU__QSPI_COHERENCY {0} \
+ CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \
+ CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {1} \
+ CONFIG.PSU__QSPI__GRP_FBCLK__IO {MIO 6} \
+ CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {x4} \
+ CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__QSPI__PERIPHERAL__IO {MIO 0 .. 5} \
+ CONFIG.PSU__QSPI__PERIPHERAL__MODE {Single} \
+ CONFIG.PSU__SATA__LANE0__ENABLE {0} \
+ CONFIG.PSU__SATA__LANE1__ENABLE {1} \
+ CONFIG.PSU__SATA__LANE1__IO {GT Lane3} \
+ CONFIG.PSU__SATA__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__SATA__REF_CLK_FREQ {125} \
+ CONFIG.PSU__SATA__REF_CLK_SEL {Ref Clk1} \
+ CONFIG.PSU__SD1_COHERENCY {0} \
+ CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \
+ CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \
+ CONFIG.PSU__SD1__GRP_CD__ENABLE {1} \
+ CONFIG.PSU__SD1__GRP_CD__IO {MIO 45} \
+ CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \
+ CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \
+ CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \
+ CONFIG.PSU__SD1__RESET__ENABLE {0} \
+ CONFIG.PSU__SD1__SLOT_TYPE {SD 2.0} \
+ CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \
+ CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__SWDT0__RESET__ENABLE {0} \
+ CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \
+ CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__SWDT1__RESET__ENABLE {0} \
+ CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \
+ CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \
+ CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \
+ CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \
+ CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \
+ CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \
+ CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \
+ CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \
+ CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \
+ CONFIG.PSU__UART0__BAUD_RATE {115200} \
+ CONFIG.PSU__UART0__MODEM__ENABLE {0} \
+ CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 18 .. 19} \
+ CONFIG.PSU__UART1__BAUD_RATE {115200} \
+ CONFIG.PSU__UART1__MODEM__ENABLE {0} \
+ CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 20 .. 21} \
+ CONFIG.PSU__USB0_COHERENCY {0} \
+ CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \
+ CONFIG.PSU__USB0__REF_CLK_FREQ {26} \
+ CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk2} \
+ CONFIG.PSU__USB0__RESET__ENABLE {0} \
+ CONFIG.PSU__USB1__RESET__ENABLE {0} \
+ CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \
+ CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \
+ CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \
+ CONFIG.PSU__USB__RESET__MODE {Boot Pin} \
+ CONFIG.PSU__USB__RESET__POLARITY {Active Low} \
+ CONFIG.PSU__USE__IRQ0 {1} \
+ CONFIG.PSU__USE__M_AXI_GP0 {0} \
+ CONFIG.PSU__USE__M_AXI_GP1 {0} \
+ CONFIG.PSU__USE__M_AXI_GP2 {1} \
+ ] $zynq_ultra_ps_e_0
+
+ # Create interface connections
+ connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_LPD [get_bd_intf_pins cmsdk_socket/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_LPD]
+
+ # Create port connections
+ connect_bd_net -net cmsdk_mcu_chip_0_swdio_o [get_bd_pins cmsdk_mcu_chip_0/swdio_o] [get_bd_pins cmsdk_socket/gpio_tri_o]
+ connect_bd_net -net cmsdk_mcu_chip_0_swdio_z [get_bd_pins cmsdk_mcu_chip_0/swdio_z] [get_bd_pins cmsdk_socket/gpio2_tri_z]
+ connect_bd_net -net cmsdk_socket_gpio2_tri_o [get_bd_pins cmsdk_mcu_chip_0/swdclk_i] [get_bd_pins cmsdk_socket/gpio2_tri_o]
+ connect_bd_net -net cmsdk_socket_gpio_tri_i [get_bd_pins cmsdk_mcu_chip_0/swdio_i] [get_bd_pins cmsdk_socket/gpio_tri_i]
+ connect_bd_net -net cmsdk_socket_nrst [get_bd_pins cmsdk_mcu_chip_0/nrst_i] [get_bd_pins cmsdk_socket/nrst]
+ connect_bd_net -net cmsdk_socket_p0_tri_i [get_bd_pins cmsdk_mcu_chip_0/p0_i] [get_bd_pins cmsdk_socket/p0_tri_i]
+ connect_bd_net -net cmsdk_socket_p1_tri_i [get_bd_pins cmsdk_mcu_chip_0/p1_i] [get_bd_pins cmsdk_socket/p1_tri_i]
+ connect_bd_net -net p0_tri_o_1 [get_bd_pins cmsdk_mcu_chip_0/p0_o] [get_bd_pins cmsdk_socket/p0_tri_o]
+ connect_bd_net -net p0_tri_z_1 [get_bd_pins cmsdk_mcu_chip_0/p0_z] [get_bd_pins cmsdk_socket/p0_tri_z]
+ connect_bd_net -net p1_tri_o_1 [get_bd_pins cmsdk_mcu_chip_0/p1_o] [get_bd_pins cmsdk_socket/p1_tri_o]
+ connect_bd_net -net p1_tri_z_1 [get_bd_pins cmsdk_mcu_chip_0/p1_z] [get_bd_pins cmsdk_socket/p1_tri_z]
+ connect_bd_net -net pmoda_i_1 [get_bd_ports pmoda_tri_i] [get_bd_pins cmsdk_socket/pmoda_tri_i]
+ connect_bd_net -net pmoda_o_concat9_dout [get_bd_ports pmoda_tri_z] [get_bd_pins cmsdk_socket/pmoda_tri_z]
+ connect_bd_net -net xlconcat_0_dout [get_bd_ports pmoda_tri_o] [get_bd_pins cmsdk_socket/pmoda_tri_o]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins cmsdk_mcu_chip_0/xtal_clk_i] [get_bd_pins cmsdk_socket/aclk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_lpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins cmsdk_socket/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0]
+
+ # Create address segments
+ assign_bd_address -offset 0x80000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_1/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_2/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_uartlite_0/S_AXI/Reg] -force
+
+
+ # Restore current instance
+ current_bd_instance $oldCurInst
+
+}
+# End of create_root_design()
+
+
+
+
+proc available_tcl_procs { } {
+ puts "##################################################################"
+ puts "# Available Tcl procedures to recreate hierarchical blocks:"
+ puts "#"
+ puts "# create_hier_cell_cmsdk_socket parentCell nameHier"
+ puts "# create_root_design"
+ puts "#"
+ puts "#"
+ puts "# The following procedures will create hiearchical blocks with addressing "
+ puts "# for IPs within those blocks and their sub-hierarchical blocks. Addressing "
+ puts "# will not be handled outside those blocks:"
+ puts "#"
+ puts "# create_root_design"
+ puts "#"
+ puts "##################################################################"
+}
+
+available_tcl_procs
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_zcu104/design_1_wrapper.v b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_zcu104/design_1_wrapper.v
new file mode 100644
index 0000000..ce586c7
--- /dev/null
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_zcu104/design_1_wrapper.v
@@ -0,0 +1,107 @@
+//Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+//--------------------------------------------------------------------------------
+//Tool Version: Vivado v.2021.1 (lin64) Build 3247384 Thu Jun 10 19:36:07 MDT 2021
+//Date : Wed Jun 22 15:58:42 2022
+//Host : srv03335 running 64-bit Red Hat Enterprise Linux release 8.6 (Ootpa)
+//Command : generate_target design_1_wrapper.bd
+//Design : design_1_wrapper
+//Purpose : IP block netlist
+//--------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+module design_1_wrapper
+ (PMOD0_0,
+ PMOD0_1,
+ PMOD0_2,
+ PMOD0_3,
+ PMOD0_4,
+ PMOD0_5,
+ PMOD0_6,
+ PMOD0_7
+ );
+// PMOD1_0,
+// PMOD1_1,
+// PMOD1_2,
+// PMOD1_3,
+// PMOD1_4,
+// PMOD1_5,
+// PMOD1_6,
+// PMOD1_7,
+// dip_switch_4bits_tri_i,
+// led_4bits_tri_o);
+
+ inout wire PMOD0_0;
+ inout wire PMOD0_1;
+ inout wire PMOD0_2;
+ inout wire PMOD0_3;
+ inout wire PMOD0_4;
+ inout wire PMOD0_5;
+ inout wire PMOD0_6;
+ inout wire PMOD0_7;
+// inout wire PMOD1_0;
+// inout wire PMOD1_1;
+// inout wire PMOD1_2;
+// inout wire PMOD1_3;
+// inout wire PMOD1_4;
+// inout wire PMOD1_5;
+// inout wire PMOD1_6;
+// inout wire PMOD1_7;
+
+// input wire [3:0]dip_switch_4bits_tri_i;
+// output wire [3:0]led_4bits_tri_o;
+
+ wire [7:0]PMOD0_tri_i;
+ wire [7:0]PMOD0_tri_o;
+ wire [7:0]PMOD0_tri_z;
+
+ assign PMOD0_tri_i[0] = PMOD0_0;
+ assign PMOD0_tri_i[1] = PMOD0_1;
+ assign PMOD0_tri_i[2] = PMOD0_2;
+ assign PMOD0_tri_i[3] = PMOD0_3;
+ assign PMOD0_tri_i[4] = PMOD0_4;
+ assign PMOD0_tri_i[5] = PMOD0_5;
+ assign PMOD0_tri_i[6] = PMOD0_6;
+ assign PMOD0_tri_i[7] = PMOD0_7;
+
+ assign PMOD0_0 = PMOD0_tri_z[0] ? 1'bz : PMOD0_tri_o[0];
+ assign PMOD0_1 = PMOD0_tri_z[1] ? 1'bz : PMOD0_tri_o[1];
+ assign PMOD0_2 = PMOD0_tri_z[2] ? 1'bz : PMOD0_tri_o[2];
+ assign PMOD0_3 = PMOD0_tri_z[3] ? 1'bz : PMOD0_tri_o[3];
+ assign PMOD0_4 = PMOD0_tri_z[4] ? 1'bz : PMOD0_tri_o[4];
+ assign PMOD0_5 = PMOD0_tri_z[5] ? 1'bz : PMOD0_tri_o[5];
+ assign PMOD0_6 = PMOD0_tri_z[6] ? 1'bz : PMOD0_tri_o[6];
+ assign PMOD0_7 = PMOD0_tri_z[7] ? 1'bz : PMOD0_tri_o[7];
+
+// wire [7:0]PMOD1_tri_i;
+// wire [7:0]PMOD1_tri_o;
+// wire [7:0]PMOD1_tri_z;
+
+// assign PMOD1_tri_i[0] = PMOD1_0;
+// assign PMOD1_tri_i[1] = PMOD1_1;
+// assign PMOD1_tri_i[2] = PMOD1_2;
+// assign PMOD1_tri_i[3] = PMOD1_3;
+// assign PMOD1_tri_i[4] = PMOD1_4;
+// assign PMOD1_tri_i[5] = PMOD1_5;
+// assign PMOD1_tri_i[6] = PMOD1_6;
+// assign PMOD1_tri_i[7] = PMOD1_7;
+
+// assign PMOD1_0 = PMOD1_tri_z[0] ? 1'bz : PMOD1_tri_o[0];
+// assign PMOD1_1 = PMOD1_tri_z[1] ? 1'bz : PMOD1_tri_o[1];
+// assign PMOD1_2 = PMOD1_tri_z[2] ? 1'bz : PMOD1_tri_o[2];
+// assign PMOD1_3 = PMOD1_tri_z[3] ? 1'bz : PMOD1_tri_o[3];
+// assign PMOD1_4 = PMOD1_tri_z[4] ? 1'bz : PMOD1_tri_o[4];
+// assign PMOD1_5 = PMOD1_tri_z[5] ? 1'bz : PMOD1_tri_o[5];
+// assign PMOD1_6 = PMOD1_tri_z[6] ? 1'bz : PMOD1_tri_o[6];
+// assign PMOD1_7 = PMOD1_tri_z[7] ? 1'bz : PMOD1_tri_o[7];
+
+ design_1 design_1_i
+ (.pmoda_tri_i(PMOD0_tri_i),
+ .pmoda_tri_o(PMOD0_tri_o),
+ .pmoda_tri_z(PMOD0_tri_z)//,
+// .PMOD1_tri_i(PMOD1_tri_i),
+// .PMOD1_tri_o(PMOD1_tri_o),
+// .PMOD1_tri_z(PMOD1_tri_z),
+// .dip_switch_4bits_tri_i(dip_switch_4bits_tri_i),
+// .led_4bits_tri_o(led_4bits_tri_o)
+ );
+endmodule
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_zcu104/fpga_pinmap.xdc b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_zcu104/fpga_pinmap.xdc
index 293b3a8..078c270 100644
--- a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_zcu104/fpga_pinmap.xdc
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_zcu104/fpga_pinmap.xdc
@@ -907,28 +907,28 @@
#Other net PACKAGE_PIN AD23 - VCCINT_VCU Bank 999 - VCCINT_VCU
#Other net PACKAGE_PIN AD24 - VCCINT_VCU Bank 999 - VCCINT_VCU
-#set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_0]
-#set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_1]
-#set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_2]
-#set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_3]
-#set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_4]
-#set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_5]
-#set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_6]
-#set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_7]
-#set_property PACKAGE_PIN G8 [get_ports PMOD0_0]
-#set_property PACKAGE_PIN H8 [get_ports PMOD0_1]
-#set_property PACKAGE_PIN G7 [get_ports PMOD0_2]
-#set_property PACKAGE_PIN H7 [get_ports PMOD0_3]
-#set_property PACKAGE_PIN G6 [get_ports PMOD0_4]
-#set_property PACKAGE_PIN H6 [get_ports PMOD0_5]
-#set_property PACKAGE_PIN J6 [get_ports PMOD0_6]
-#set_property PACKAGE_PIN J7 [get_ports PMOD0_7]
-#set_property PULLUP true [get_ports PMOD0_2]
-#set_property PULLUP true [get_ports PMOD0_3]
-#set_property PULLUP true [get_ports PMOD0_4]
-#set_property PULLUP true [get_ports PMOD0_5]
-#set_property PULLUP true [get_ports PMOD0_6]
-#set_property PULLUP true [get_ports PMOD0_7]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_0]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_1]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_2]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_3]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_4]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_5]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_6]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_7]
+set_property PACKAGE_PIN G8 [get_ports PMOD0_0]
+set_property PACKAGE_PIN H8 [get_ports PMOD0_1]
+set_property PACKAGE_PIN G7 [get_ports PMOD0_2]
+set_property PACKAGE_PIN H7 [get_ports PMOD0_3]
+set_property PACKAGE_PIN G6 [get_ports PMOD0_4]
+set_property PACKAGE_PIN H6 [get_ports PMOD0_5]
+set_property PACKAGE_PIN J6 [get_ports PMOD0_6]
+set_property PACKAGE_PIN J7 [get_ports PMOD0_7]
+set_property PULLUP true [get_ports PMOD0_2]
+set_property PULLDOWN true [get_ports PMOD0_3]
+set_property PULLUP true [get_ports PMOD0_4]
+set_property PULLUP true [get_ports PMOD0_5]
+set_property PULLUP true [get_ports PMOD0_6]
+set_property PULLUP true [get_ports PMOD0_7]
#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_0]
#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_1]
@@ -956,122 +956,74 @@
#set_property PULLUP true [get_ports PMOD1_1]
#set_property PULLUP true [get_ports PMOD1_0]
-set_property IOSTANDARD LVCMOS33 [get_ports {P0[0]} ]
-set_property IOSTANDARD LVCMOS33 [get_ports {P0[1]} ]
-set_property IOSTANDARD LVCMOS33 [get_ports {P0[2]} ]
-set_property IOSTANDARD LVCMOS33 [get_ports {P0[3]} ]
-set_property IOSTANDARD LVCMOS33 [get_ports {P0[4]} ]
-set_property IOSTANDARD LVCMOS33 [get_ports {P0[5]} ]
-set_property IOSTANDARD LVCMOS33 [get_ports {P0[6]} ]
-set_property IOSTANDARD LVCMOS33 [get_ports {P0[7]} ]
-#set_property PACKAGE_PIN G8 [get_ports {P0[0]} ]
-#set_property PACKAGE_PIN H8 [get_ports {P0[1]} ]
-#set_property PACKAGE_PIN G7 [get_ports {P0[2]} ]
-#set_property PACKAGE_PIN H7 [get_ports {P0[3]} ]
-#set_property PACKAGE_PIN G6 [get_ports {P0[4]} ]
-#set_property PACKAGE_PIN H6 [get_ports {P0[5]} ]
-#set_property PACKAGE_PIN J6 [get_ports {P0[6]} ]
-#set_property PACKAGE_PIN J7 [get_ports {P0[7]} ]
-set_property PULLUP true [get_ports {P0[2]} ]
-set_property PULLUP true [get_ports {P0[3]} ]
-set_property PULLUP true [get_ports {P0[4]} ]
-set_property PULLUP true [get_ports {P0[5]} ]
-set_property PULLUP true [get_ports {P0[6]} ]
-set_property PULLUP true [get_ports {P0[7]} ]
-
-set_property IOSTANDARD LVCMOS33 [get_ports {P1[0]} ]
-set_property IOSTANDARD LVCMOS33 [get_ports {P1[1]} ]
-set_property IOSTANDARD LVCMOS33 [get_ports {P1[2]} ]
-set_property IOSTANDARD LVCMOS33 [get_ports {P1[3]} ]
-set_property IOSTANDARD LVCMOS33 [get_ports {P1[4]} ]
-set_property IOSTANDARD LVCMOS33 [get_ports {P1[5]} ]
-set_property IOSTANDARD LVCMOS33 [get_ports {P1[6]} ]
-set_property IOSTANDARD LVCMOS33 [get_ports {P1[7]} ]
-#set_property PACKAGE_PIN J9 [get_ports {P1[0]} ]
-#set_property PACKAGE_PIN K9 [get_ports {P1[1]} ]
-#set_property PACKAGE_PIN K8 [get_ports {P1[2]} ]
-#set_property PACKAGE_PIN L8 [get_ports {P1[3]} ]
-#set_property PACKAGE_PIN L10 [get_ports {P1[4]} ]
-#set_property PACKAGE_PIN M10 [get_ports {P1[5]} ]
-#set_property PACKAGE_PIN M8 [get_ports {P1[6]} ]
-#set_property PACKAGE_PIN M9 [get_ports {P1[7]} ]
-
-set_property PULLUP true [get_ports {P1[7]} ]
-set_property PULLUP true [get_ports {P1[6]} ]
-set_property PULLUP true [get_ports {P1[5]} ]
-set_property PULLUP true [get_ports {P1[4]} ]
-set_property PULLUP true [get_ports {P1[3]} ]
-set_property PULLUP true [get_ports {P1[2]} ]
-set_property PULLUP true [get_ports {P1[1]} ]
-set_property PULLUP true [get_ports {P1[0]} ]
#PMODA pin0 to FTCLK
-set_property PACKAGE_PIN K9 [get_ports {P1[1]}]
+#set_property PACKAGE_PIN K9 [get_ports {P1[1]}]
#PMODA pin1 to FTSSN
-set_property PACKAGE_PIN L8 [get_ports {P1[3]}]
+#set_property PACKAGE_PIN L8 [get_ports {P1[3]}]
#PMODA pin2 to FTMISO
-set_property PACKAGE_PIN J9 [get_ports {P1[0]}]
+#set_property PACKAGE_PIN J9 [get_ports {P1[0]}]
#PMODA pin3 to FTMIOSIO
-set_property PACKAGE_PIN K8 [get_ports {P1[2]}]
+#set_property PACKAGE_PIN K8 [get_ports {P1[2]}]
#PMODB pin1 to SWDIOTMS
-set_property PACKAGE_PIN G8 [get_ports SWDIOTMS]
+#set_property PACKAGE_PIN G8 [get_ports SWDIOTMS]
#PMODB pin4 to SWCLKTCK
-set_property PACKAGE_PIN H7 [get_ports SWCLKTCK]
-set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets uPAD_SWDCLK_I/IOBUF3V3/O]
+#set_property PACKAGE_PIN H7 [get_ports SWCLKTCK]
+#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets uPAD_SWDCLK_I/IOBUF3V3/O]
#PMODA pin4 : UART2RXD
#PMODA pin4 : UART2TXD
# LED0 to P0[0]
-set_property PACKAGE_PIN D5 [get_ports {P0[0]}]
+#set_property PACKAGE_PIN D5 [get_ports {P0[0]}]
# LED1 to P0[1]
-set_property PACKAGE_PIN D6 [get_ports {P0[1]}]
+#set_property PACKAGE_PIN D6 [get_ports {P0[1]}]
# LED2 to P0[2]
-set_property PACKAGE_PIN A5 [get_ports {P0[2]}]
+#set_property PACKAGE_PIN A5 [get_ports {P0[2]}]
# LED3 to P0[3]
-set_property PACKAGE_PIN B5 [get_ports {P0[3]}]
+#set_property PACKAGE_PIN B5 [get_ports {P0[3]}]
# SW0 to NRST (Down for active low)
-set_property PACKAGE_PIN B4 [get_ports NRST]
+#set_property PACKAGE_PIN B4 [get_ports NRST]
# CLK125MHz (need dvider)
-set_property IOSTANDARD LVCMOS18 [get_ports XTAL1 ]
-set_property PACKAGE_PIN F23 [get_ports XTAL1]
+#set_property IOSTANDARD LVCMOS18 [get_ports XTAL1 ]
+#set_property PACKAGE_PIN F23 [get_ports XTAL1]
## auto mapped - to remap
-set_property PACKAGE_PIN C4 [get_ports {P0[10]}]
-set_property PACKAGE_PIN C3 [get_ports {P0[11]}]
-set_property PACKAGE_PIN B3 [get_ports {P0[12]}]
-set_property PACKAGE_PIN D2 [get_ports {P0[13]}]
-set_property PACKAGE_PIN C2 [get_ports {P0[14]}]
-set_property PACKAGE_PIN E3 [get_ports {P0[15]}]
-set_property PACKAGE_PIN F6 [get_ports {P0[4]}]
-set_property PACKAGE_PIN E5 [get_ports {P0[5]}]
-set_property PACKAGE_PIN F5 [get_ports {P0[6]}]
-set_property PACKAGE_PIN F4 [get_ports {P0[7]}]
-set_property PACKAGE_PIN E4 [get_ports {P0[8]}]
-set_property PACKAGE_PIN D4 [get_ports {P0[9]}]
-set_property PACKAGE_PIN M10 [get_ports {P1[10]}]
-set_property PACKAGE_PIN L10 [get_ports {P1[11]}]
-set_property PACKAGE_PIN M9 [get_ports {P1[12]}]
-set_property PACKAGE_PIN M8 [get_ports {P1[13]}]
-set_property PACKAGE_PIN N11 [get_ports {P1[14]}]
-set_property PACKAGE_PIN M11 [get_ports {P1[15]}]
-set_property PACKAGE_PIN H8 [get_ports {P1[4]}]
-set_property PACKAGE_PIN G7 [get_ports {P1[5]}]
-set_property PACKAGE_PIN H6 [get_ports {P1[6]}]
-set_property PACKAGE_PIN G6 [get_ports {P1[7]}]
-set_property PACKAGE_PIN J7 [get_ports {P1[8]}]
-set_property PACKAGE_PIN J6 [get_ports {P1[9]}]
-set_property PACKAGE_PIN E2 [get_ports VDD]
-set_property PACKAGE_PIN A3 [get_ports VDDIO]
-set_property PACKAGE_PIN A2 [get_ports VSS]
-set_property PACKAGE_PIN C1 [get_ports VSSIO]
-set_property PACKAGE_PIN B1 [get_ports XTAL2]
+#set_property PACKAGE_PIN C4 [get_ports {P0[10]}]
+#set_property PACKAGE_PIN C3 [get_ports {P0[11]}]
+#set_property PACKAGE_PIN B3 [get_ports {P0[12]}]
+#set_property PACKAGE_PIN D2 [get_ports {P0[13]}]
+#set_property PACKAGE_PIN C2 [get_ports {P0[14]}]
+#set_property PACKAGE_PIN E3 [get_ports {P0[15]}]
+#set_property PACKAGE_PIN F6 [get_ports {P0[4]}]
+#set_property PACKAGE_PIN E5 [get_ports {P0[5]}]
+#set_property PACKAGE_PIN F5 [get_ports {P0[6]}]
+#set_property PACKAGE_PIN F4 [get_ports {P0[7]}]
+#set_property PACKAGE_PIN E4 [get_ports {P0[8]}]
+#set_property PACKAGE_PIN D4 [get_ports {P0[9]}]
+#set_property PACKAGE_PIN M10 [get_ports {P1[10]}]
+#set_property PACKAGE_PIN L10 [get_ports {P1[11]}]
+#set_property PACKAGE_PIN M9 [get_ports {P1[12]}]
+#set_property PACKAGE_PIN M8 [get_ports {P1[13]}]
+#set_property PACKAGE_PIN N11 [get_ports {P1[14]}]
+#set_property PACKAGE_PIN M11 [get_ports {P1[15]}]
+#set_property PACKAGE_PIN H8 [get_ports {P1[4]}]
+#set_property PACKAGE_PIN G7 [get_ports {P1[5]}]
+#set_property PACKAGE_PIN H6 [get_ports {P1[6]}]
+#set_property PACKAGE_PIN G6 [get_ports {P1[7]}]
+#set_property PACKAGE_PIN J7 [get_ports {P1[8]}]
+#set_property PACKAGE_PIN J6 [get_ports {P1[9]}]
+#set_property PACKAGE_PIN E2 [get_ports VDD]
+#set_property PACKAGE_PIN A3 [get_ports VDDIO]
+#set_property PACKAGE_PIN A2 [get_ports VSS]
+#set_property PACKAGE_PIN C1 [get_ports VSSIO]
+#set_property PACKAGE_PIN B1 [get_ports XTAL2]
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_zcu104/fpga_timing.xdc b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_zcu104/fpga_timing.xdc
index b93d2f8..fe6eb50 100644
--- a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_zcu104/fpga_timing.xdc
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_zcu104/fpga_timing.xdc
@@ -4,10 +4,10 @@
## ##
##################################################################################
-create_clock -name CLK -period 30 [get_ports XTAL1]
+create_clock -name CLK -period 30 [get_ports xtal_clk_i]
create_clock -name VCLK -period 30 -waveform {5 20}
-create_clock -name SWCLK -period 60 [get_ports SWCLKTCK]
+create_clock -name SWCLK -period 60 [get_ports swdclk_i]
create_clock -name VSWCLK -period 60 -waveform {5 35}
set_clock_groups -name async_clk_swclock -asynchronous \
@@ -23,71 +23,71 @@ set_clock_groups -name async_clk_swclock -asynchronous \
#set_output_delay -clock [get_clocks clk_pl_0] -min -add_delay 5.000 [get_ports {led_4bits_tri_o[*]}]
#set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {led_4bits_tri_o[*]}]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[0]}]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[0]}]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[1]}]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[1]}]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[2]}]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[2]}]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[3]}]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[3]}]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[4]}]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[4]}]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[5]}]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[5]}]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[6]}]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[6]}]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[7]}]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[7]}]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[8]}]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[8]}]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[9]}]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[9]}]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[10]}]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[10]}]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[11]}]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[11]}]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[12]}]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[12]}]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[13]}]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[13]}]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[14]}]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[14]}]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[15]}]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[15]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[0]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[0]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[1]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[1]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[2]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[2]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[3]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[3]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[4]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[4]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[5]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[5]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[6]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[6]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[7]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[7]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[8]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[8]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[9]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[9]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[10]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[10]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[11]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[11]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[12]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[12]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[13]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[13]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[14]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[14]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[15]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[15]}]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[0]}]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[0]}]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[1]}]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[1]}]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[2]}]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[2]}]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[3]}]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[3]}]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[4]}]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[4]}]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[5]}]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[5]}]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[6]}]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[6]}]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[7]}]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[7]}]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[8]}]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[8]}]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[9]}]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[9]}]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[10]}]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[10]}]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[11]}]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[11]}]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[12]}]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[12]}]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[13]}]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[13]}]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[14]}]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[14]}]
-set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[15]}]
-set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[15]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[0]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[0]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[1]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[1]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[2]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[2]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[3]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[3]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[4]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[4]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[5]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[5]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[6]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[6]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[7]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[7]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[8]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[8]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[9]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[9]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[10]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[10]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[11]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[11]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[12]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[12]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[13]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[13]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[14]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[14]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[15]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[15]}]
#set_property C_CLK_INPUT_FREQ_HZ 5000000 [get_debug_cores dbg_hub]
#set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/bootrom.v b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/bootrom.v
index fe575ec..4069059 100644
--- a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/bootrom.v
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/bootrom.v
@@ -5,7 +5,7 @@
// Contributors
//
// David Flynn (d.w.flynn@soton.ac.uk)
-// Date: 2207011724
+// Date: 2207051707
// Copyright (c) 2021-2, SoC Labs (www.soclabs.org)
//------------------------------------------------------------------------------------
module bootrom (
@@ -118,16 +118,16 @@ always @(addr_r) case(addr_r[9:2])
8'h63 : RDATA <= 32'hd1fc07d2; // 0x018c
8'h64 : RDATA <= 32'h494a6008; // 0x0190
8'h65 : RDATA <= 32'h07d2684a; // 0x0194
- 8'h66 : RDATA <= 32'h6008d1fc; // 0x0198
+ 8'h66 : RDATA <= 32'h6008d100; // 0x0198
8'h67 : RDATA <= 32'hb4104770; // 0x019c
- 8'h68 : RDATA <= 32'h4a464945; // 0x01a0
- 8'h69 : RDATA <= 32'h2c007804; // 0x01a4
- 8'h6a : RDATA <= 32'h684bd00a; // 0x01a8
- 8'h6b : RDATA <= 32'hd1fc07db; // 0x01ac
- 8'h6c : RDATA <= 32'h6853600c; // 0x01b0
- 8'h6d : RDATA <= 32'hd1fc07db; // 0x01b4
- 8'h6e : RDATA <= 32'h1c406014; // 0x01b8
- 8'h6f : RDATA <= 32'hd1f12c00; // 0x01bc
+ 8'h68 : RDATA <= 32'h4c464945; // 0x01a0
+ 8'h69 : RDATA <= 32'h2b007803; // 0x01a4
+ 8'h6a : RDATA <= 32'h684ad00a; // 0x01a8
+ 8'h6b : RDATA <= 32'hd1fc07d2; // 0x01ac
+ 8'h6c : RDATA <= 32'h6862600b; // 0x01b0
+ 8'h6d : RDATA <= 32'hd10007d2; // 0x01b4
+ 8'h6e : RDATA <= 32'h1c406023; // 0x01b8
+ 8'h6f : RDATA <= 32'hd1f12b00; // 0x01bc
8'h70 : RDATA <= 32'h4770bc10; // 0x01c0
8'h71 : RDATA <= 32'h483fb510; // 0x01c4
8'h72 : RDATA <= 32'h29006801; // 0x01c8
@@ -136,60 +136,60 @@ always @(addr_r) case(addr_r[9:2])
8'h75 : RDATA <= 32'hf3bf8f4f; // 0x01d4
8'h76 : RDATA <= 32'hf7ff8f6f; // 0x01d8
8'h77 : RDATA <= 32'hbd10ffc3; // 0x01dc
- 8'h78 : RDATA <= 32'h49364835; // 0x01e0
- 8'h79 : RDATA <= 32'h7823a438; // 0x01e4
- 8'h7a : RDATA <= 32'hd00a2b00; // 0x01e8
- 8'h7b : RDATA <= 32'h07d26842; // 0x01ec
- 8'h7c : RDATA <= 32'h6003d1fc; // 0x01f0
- 8'h7d : RDATA <= 32'h07d2684a; // 0x01f4
- 8'h7e : RDATA <= 32'h600bd1fc; // 0x01f8
- 8'h7f : RDATA <= 32'h2b001c64; // 0x01fc
- 8'h80 : RDATA <= 32'h2204d1f1; // 0x0200
- 8'h81 : RDATA <= 32'h07db6843; // 0x0204
- 8'h82 : RDATA <= 32'h6002d1fc; // 0x0208
- 8'h83 : RDATA <= 32'h07c06848; // 0x020c
- 8'h84 : RDATA <= 32'h600ad1fc; // 0x0210
+ 8'h78 : RDATA <= 32'h4c364835; // 0x01e0
+ 8'h79 : RDATA <= 32'h781aa338; // 0x01e4
+ 8'h7a : RDATA <= 32'hd00a2a00; // 0x01e8
+ 8'h7b : RDATA <= 32'h07c96841; // 0x01ec
+ 8'h7c : RDATA <= 32'h6002d1fc; // 0x01f0
+ 8'h7d : RDATA <= 32'h07c96861; // 0x01f4
+ 8'h7e : RDATA <= 32'h6022d100; // 0x01f8
+ 8'h7f : RDATA <= 32'h2a001c5b; // 0x01fc
+ 8'h80 : RDATA <= 32'h2104d1f1; // 0x0200
+ 8'h81 : RDATA <= 32'h07d26842; // 0x0204
+ 8'h82 : RDATA <= 32'h6001d1fc; // 0x0208
+ 8'h83 : RDATA <= 32'h07c06860; // 0x020c
+ 8'h84 : RDATA <= 32'h6021d100; // 0x0210
8'h85 : RDATA <= 32'hb510e7fe; // 0x0214
8'h86 : RDATA <= 32'h48272141; // 0x0218
8'h87 : RDATA <= 32'h61010149; // 0x021c
- 8'h88 : RDATA <= 32'h60822201; // 0x0220
- 8'h89 : RDATA <= 32'h608a4925; // 0x0224
- 8'h8a : RDATA <= 32'h22204b25; // 0x0228
- 8'h8b : RDATA <= 32'ha42c619a; // 0x022c
+ 8'h88 : RDATA <= 32'h60812101; // 0x0220
+ 8'h89 : RDATA <= 32'h60914a25; // 0x0224
+ 8'h8a : RDATA <= 32'h21204b25; // 0x0228
+ 8'h8b : RDATA <= 32'ha42c6199; // 0x022c
8'h8c : RDATA <= 32'h2b007823; // 0x0230
- 8'h8d : RDATA <= 32'h6842d00a; // 0x0234
- 8'h8e : RDATA <= 32'hd1fc07d2; // 0x0238
- 8'h8f : RDATA <= 32'h684a6003; // 0x023c
- 8'h90 : RDATA <= 32'hd1fc07d2; // 0x0240
- 8'h91 : RDATA <= 32'h1c64600b; // 0x0244
+ 8'h8d : RDATA <= 32'h6841d00a; // 0x0234
+ 8'h8e : RDATA <= 32'hd1fc07c9; // 0x0238
+ 8'h8f : RDATA <= 32'h68516003; // 0x023c
+ 8'h90 : RDATA <= 32'hd10007c9; // 0x0240
+ 8'h91 : RDATA <= 32'h1c646013; // 0x0244
8'h92 : RDATA <= 32'hd1f12b00; // 0x0248
8'h93 : RDATA <= 32'h7823a42c; // 0x024c
8'h94 : RDATA <= 32'hd00a2b00; // 0x0250
- 8'h95 : RDATA <= 32'h07d26842; // 0x0254
+ 8'h95 : RDATA <= 32'h07c96841; // 0x0254
8'h96 : RDATA <= 32'h6003d1fc; // 0x0258
- 8'h97 : RDATA <= 32'h07d2684a; // 0x025c
- 8'h98 : RDATA <= 32'h600bd1fc; // 0x0260
+ 8'h97 : RDATA <= 32'h07c96851; // 0x025c
+ 8'h98 : RDATA <= 32'h6013d100; // 0x0260
8'h99 : RDATA <= 32'h2b001c64; // 0x0264
- 8'h9a : RDATA <= 32'h4a16d1f1; // 0x0268
- 8'h9b : RDATA <= 32'h2b006813; // 0x026c
+ 8'h9a : RDATA <= 32'h4916d1f1; // 0x0268
+ 8'h9b : RDATA <= 32'h2b00680b; // 0x026c
8'h9c : RDATA <= 32'h2000d009; // 0x0270
- 8'h9d : RDATA <= 32'hf3bf6010; // 0x0274
+ 8'h9d : RDATA <= 32'hf3bf6008; // 0x0274
8'h9e : RDATA <= 32'hf3bf8f4f; // 0x0278
8'h9f : RDATA <= 32'hf7ff8f6f; // 0x027c
8'ha0 : RDATA <= 32'h2000ff71; // 0x0280
8'ha1 : RDATA <= 32'ha410bd10; // 0x0284
8'ha2 : RDATA <= 32'h2b007823; // 0x0288
- 8'ha3 : RDATA <= 32'h6842d00a; // 0x028c
- 8'ha4 : RDATA <= 32'hd1fc07d2; // 0x0290
- 8'ha5 : RDATA <= 32'h684a6003; // 0x0294
- 8'ha6 : RDATA <= 32'hd1fc07d2; // 0x0298
- 8'ha7 : RDATA <= 32'h1c64600b; // 0x029c
+ 8'ha3 : RDATA <= 32'h6841d00a; // 0x028c
+ 8'ha4 : RDATA <= 32'hd1fc07c9; // 0x0290
+ 8'ha5 : RDATA <= 32'h68516003; // 0x0294
+ 8'ha6 : RDATA <= 32'hd10007c9; // 0x0298
+ 8'ha7 : RDATA <= 32'h1c646013; // 0x029c
8'ha8 : RDATA <= 32'hd1f12b00; // 0x02a0
- 8'ha9 : RDATA <= 32'h68432204; // 0x02a4
- 8'haa : RDATA <= 32'hd1fc07db; // 0x02a8
- 8'hab : RDATA <= 32'h68486002; // 0x02ac
- 8'hac : RDATA <= 32'hd1fc07c0; // 0x02b0
- 8'had : RDATA <= 32'he7fe600a; // 0x02b4
+ 8'ha9 : RDATA <= 32'h68412304; // 0x02a4
+ 8'haa : RDATA <= 32'hd1fc07c9; // 0x02a8
+ 8'hab : RDATA <= 32'h68506003; // 0x02ac
+ 8'hac : RDATA <= 32'hd10007c0; // 0x02b0
+ 8'had : RDATA <= 32'he7fe6013; // 0x02b4
8'hae : RDATA <= 32'h40006000; // 0x02b8
8'haf : RDATA <= 32'h4000e000; // 0x02bc
8'hb0 : RDATA <= 32'h40011000; // 0x02c0
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/tb_cmsdk_mcu.v b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/tb_cmsdk_mcu.v
index 8f2711d..c6fec0c 100644
--- a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/tb_cmsdk_mcu.v
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/tb_cmsdk_mcu.v
@@ -381,7 +381,7 @@ wire ft_clk2uart;
wire ft_rxd2uart;
wire ft_txd2uart;
- cmsdk_ft1248x1_adpio // #(.LOGFILENAME("uart2.log"))
+ cmsdk_ft1248x1_adpio // #(.ADPFILENAME("ADPFILENAME.log"))
u_ft1248_adpio(
.ft_clk_i (ft_clk_out),
.ft_ssn_i (ft_ssn_out),
--
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