diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/build_mcu_fpga_pynq_z2.tcl b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/build_mcu_fpga_pynq_z2.tcl
index c0e1c114a5b3d17e1e18108ec6bb2553678ae7cb..450ae3cc4c720ded8cf8bc7ce2b5eb96fc03db37 100644
--- a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/build_mcu_fpga_pynq_z2.tcl
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/build_mcu_fpga_pynq_z2.tcl
@@ -78,7 +78,7 @@ set_property file_type {Verilog Header} [get_files  ../../../../../../arm-AAA-ip
 
 add_files $importDir/fpga_pinmap.xdc
 
-vivado -mode tcl -source scripts/build_mcu_fpga_ip.tcl
+set_property top design_1_wrapper [current_fileset]
 
 #
 # STEP#3: save in Project mode to complete flow