diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/rtl_sim/makefile b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/rtl_sim/makefile index cf4c7e2048d4df453aa3cdd6cfed9ee62337463e..cdae0a1f386792ae5346323d159d123059cdfba5 100644 --- a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/rtl_sim/makefile +++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/rtl_sim/makefile @@ -387,7 +387,7 @@ v2html: fi @(cd ../v2html_doc; \ rm *.html; rm *.gif; rm *.gz; \ - ../tools/v2html -f ../verilog/v2html_M0.vc -ht cmsdk_mcu_system ; \ + ~/tools/v2html -f ../verilog/v2html_M0.vc -ht cmsdk_mcu_system ; \ cp -p tb_cmsdk_mcu.v.html hierarchy.html ; \ cd ../rtl_sim ; ) gtar zcvf ../v2html_doc.tgz ../v2html_doc @@ -530,6 +530,9 @@ clean : clean_all_code @if [ -e cds.lib ] ; then \ rm -rf cds.lib ; \ fi - @if [ -e ../v2html ] ; then \ - rm -rf ../v2html ; \ + @if [ -e logs ] ; then \ + rm -rf logs ; \ + fi + @if [ -e ../v2html_doc ] ; then \ + rm -rf ../v2html_doc ; \ fi diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/v2html_doc.tgz b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/v2html_doc.tgz index fe4c5b24fd13b56445d74ff8bdb51cd9826a22d7..94edc8a29c0f176ade639118a89a57abb884740b 100644 Binary files a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/v2html_doc.tgz and b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/v2html_doc.tgz differ diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/tbench_M0.vc b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/tbench_M0.vc index b694aeba3e46166d6feb3a4a6f40d951d116735a..5b3ebb122ed685b2fc0461d3c8f5dda8d7dabb22 100644 --- a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/tbench_M0.vc +++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/tbench_M0.vc @@ -51,62 +51,61 @@ // ================= Testbench path =================== --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/cmsdk_debug_tester/verilog -+incdir+../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/cmsdk_debug_tester/verilog +-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_debug_tester/verilog ++incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_debug_tester/verilog // ============= MCU Module search path ============= -y ../verilog --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/cmsdk_apb_timer/verilog --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/cmsdk_apb_uart/verilog --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/cmsdk_apb_slave_mux/verilog --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/cmsdk_apb_subsystem/verilog --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_slave_mux/verilog --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_master_mux/verilog --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_default_slave/verilog --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_gpio/verilog --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_to_apb/verilog --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_bitband/verilog --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/cmsdk_iop_gpio/verilog --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/models/clkgate --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/models/memories/ --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_to_sram/verilog --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_to_flash32/verilog --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_to_extmem16/verilog -+incdir+../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog -+incdir+../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog -+incdir+../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/models/memories/ - -//// Optional PL230 Micro DMA controller - not included in deliverable -//-y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/pl230_udma/verilog -+incdir+../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/pl230_udma/verilog -//../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/pl230_udma/verilog/pl230_defs.v +-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_timer/verilog +-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog +-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_uart/verilog +-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog +-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_slave_mux/verilog +-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_subsystem/verilog +-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_slave_mux/verilog +-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_master_mux/verilog +-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_default_slave/verilog +-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_gpio/verilog +-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_to_apb/verilog +-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_bitband/verilog +-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_iop_gpio/verilog +-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/clkgate +-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/memories/ +-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_to_sram/verilog +-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_to_flash32/verilog +-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_to_extmem16/verilog ++incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog ++incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog ++incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/memories/ + +//// Optional PL230 Micro DMA controller - configure in local ../verilog/pl230_defs.v file +//-y ../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel1/verilog ++incdir+../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel1/verilog ../verilog/pl230_defs.v -../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/pl230_udma/verilog/pl230_ahb_ctrl.v -../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/pl230_udma/verilog/pl230_apb_regs.v -../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/pl230_udma/verilog/pl230_dma_data.v -../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/pl230_udma/verilog/pl230_udma.v -../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/pl230_udma/verilog/pl230_undefs.v +../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel1/verilog/pl230_ahb_ctrl.v +../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel1/verilog/pl230_apb_regs.v +../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel1/verilog/pl230_dma_data.v +../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel1/verilog/pl230_udma.v +../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel1/verilog/pl230_undefs.v // ============= Cortex-M0 Module search path ============= --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/cores/at510_cortexm0_r0p0_03rel2/logical/cortexm0/verilog --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/cores/at510_cortexm0_r0p0_03rel2/logical/cortexm0_dap/verilog --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/cores/at510_cortexm0_r0p0_03rel2/logical/cortexm0_integration/verilog --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/cores/at510_cortexm0_r0p0_03rel2/logical/models/cells --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/cores/at510_cortexm0_r0p0_03rel2/logical/models/wrappers --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/cores/at510_cortexm0_r0p0_03rel2/logical/ualdis/verilog +-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/cortexm0/verilog +-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/cortexm0_dap/verilog +-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/cortexm0_integration/verilog +-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/models/cells +-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/models/wrappers +-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/ualdis/verilog // ============= Cortex-M0 Include file search path ============= -+incdir+../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/cores/at510_cortexm0_r0p0_03rel2/logical/cortexm0/verilog -+incdir+../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/cores/at510_cortexm0_r0p0_03rel2/logical/cortexm0_dap/verilog -+incdir+../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/cores/at510_cortexm0_r0p0_03rel2/logical/cortexm0_integration/verilog -+incdir+../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/cores/at510_cortexm0_r0p0_03rel2/logical/models/cells -+incdir+../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/cores/at510_cortexm0_r0p0_03rel2/logical/models/wrappers -+incdir+../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/cores/at510_cortexm0_r0p0_03rel2/logical/ualdis/verilog ++incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/cortexm0/verilog ++incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/cortexm0_dap/verilog ++incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/cortexm0_integration/verilog ++incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/models/cells ++incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/models/wrappers ++incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/ualdis/verilog @@ -122,10 +121,10 @@ //+define+ARM_CMSDK_ASSERT_ON // ============= Verification components ============= --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/models/protocol_checkers/AhbLitePC/verilog/ -+incdir+../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/models/protocol_checkers/AhbLitePC/verilog/ --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/models/protocol_checkers/ApbPC/verilog/ -+incdir+../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/models/protocol_checkers/ApbPC/verilog/ +-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/protocol_checkers/AhbLitePC/verilog/ ++incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/protocol_checkers/AhbLitePC/verilog/ +-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/protocol_checkers/ApbPC/verilog/ ++incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/protocol_checkers/ApbPC/verilog/ ///+incdir+/arm/tools/accellera/ovl/releases/ovl_v2p6_Oct2011/std_ovl ///-y /arm/tools/accellera/ovl/releases/ovl_v2p6_Oct2011/std_ovl diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/v2html_M0.vc b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/v2html_M0.vc index 027e9071e005cb5811c70849af11b3726d9473df..3c7894ec54ed1bfbfc036b065b3201a580b9754c 100644 --- a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/v2html_M0.vc +++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/v2html_M0.vc @@ -51,55 +51,55 @@ // ================= Testbench path =================== --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/cmsdk_debug_tester/verilog -+incdir+../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/cmsdk_debug_tester/verilog +-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_debug_tester/verilog ++incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_debug_tester/verilog // ============= MCU Module search path ============= -y ../verilog --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/cmsdk_apb_timer/verilog --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/cmsdk_apb_uart/verilog --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/cmsdk_apb_slave_mux/verilog --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/cmsdk_apb_subsystem/verilog --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_slave_mux/verilog --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_master_mux/verilog --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_default_slave/verilog --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_gpio/verilog --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_to_apb/verilog --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_bitband/verilog --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/cmsdk_iop_gpio/verilog --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/models/clkgate --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/models/memories/ --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_to_sram/verilog --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_to_flash32/verilog --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_to_extmem16/verilog -+incdir+../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog -+incdir+../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog -+incdir+../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/models/memories/ +-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_timer/verilog +-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog +-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_uart/verilog +-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog +-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_slave_mux/verilog +-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_subsystem/verilog +-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_slave_mux/verilog +-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_master_mux/verilog +-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_default_slave/verilog +-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_gpio/verilog +-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_to_apb/verilog +-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_bitband/verilog +-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_iop_gpio/verilog +-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/clkgate +-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/memories/ +-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_to_sram/verilog +-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_to_flash32/verilog +-y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_to_extmem16/verilog ++incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog ++incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog ++incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/memories/ -//// Optional PL230 Micro DMA controller - not included in deliverable -//-y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/pl230_udma/verilog -+incdir+../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/pl230_udma/verilog -//../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/pl230_udma/verilog/pl230_defs.v +//// Optional PL230 Micro DMA controller - configure in local ../verilog/pl230_defs.v file +//-y ../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel1/verilog ++incdir+../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel1/verilog ../verilog/pl230_defs.v -../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/pl230_udma/verilog/pl230_ahb_ctrl.v -../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/pl230_udma/verilog/pl230_apb_regs.v -../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/pl230_udma/verilog/pl230_dma_data.v -../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/pl230_udma/verilog/pl230_udma.v -../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/logical/pl230_udma/verilog/pl230_undefs.v +../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel1/verilog/pl230_ahb_ctrl.v +../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel1/verilog/pl230_apb_regs.v +../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel1/verilog/pl230_dma_data.v +../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel1/verilog/pl230_udma.v +../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel1/verilog/pl230_undefs.v // ============= Cortex-M0 Module search path ============= - --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/cores/at510_cortexm0_r0p0_03rel2/logical/cortexm0_integration/verilog --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/cores/at510_cortexm0_r0p0_03rel2/logical/models/cells --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/cores/at510_cortexm0_r0p0_03rel2/logical/models/wrappers --y ../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/cores/at510_cortexm0_r0p0_03rel2/logical/ualdis/verilog +// guts of core not exposed, periphery only +-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/cortexm0_integration/verilog +-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/models/cells +-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/models/wrappers +-y ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/ualdis/verilog // ============= Cortex-M0 Include file search path ============= +// guts of core not exposed, periphery only -+incdir+../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/cores/at510_cortexm0_r0p0_03rel2/logical/cortexm0_integration/verilog -+incdir+../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/cores/at510_cortexm0_r0p0_03rel2/logical/models/cells -+incdir+../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/cores/at510_cortexm0_r0p0_03rel2/logical/models/wrappers -+incdir+../../../../../../arm-ip-installed/AT514-BU-98000-r0p1-00rel0/BP200-BU-00000-r1p1-00rel0/cores/at510_cortexm0_r0p0_03rel2/logical/ualdis/verilog ++incdi+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/cortexm0_integration/verilog ++incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/models/cells ++incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/models/wrappers ++incdir+../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical/ualdis/verilog