diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/build_fpga.scr b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/build_fpga.scr
new file mode 100755
index 0000000000000000000000000000000000000000..34c09f2d9c6bc28b02ac59f4667b86a12480da17
--- /dev/null
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/build_fpga.scr
@@ -0,0 +1,9 @@
+echo 'run' $0
+echo 'target' $1
+#set argv [list $1 $1]
+#set argc 1
+rm target_fpga
+ln -sf target_fpga_$1 target_fpga
+vivado -mode batch -source scripts/build_mcu_fpga_batch.tcl
+rm -R vivado/built_mcu_fpga_$1
+mv -f vivado/built_mcu_fpga vivado/built_mcu_fpga_$1
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/build_mcu_fpga_batch.tcl b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/build_mcu_fpga_batch.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..c884fbea34ad4199fe7e86ef4b49e9395d5375d4
--- /dev/null
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/build_mcu_fpga_batch.tcl
@@ -0,0 +1,106 @@
+# build_mcu_fpga_batch.tcl
+#
+# cmsdk_mcu sample design 
+# A Vivado script that demonstrates a very simple RTL-to-bitstream non-project batch flow
+#
+# NOTE:  typical usage would be "vivado -mode tcl -source build_mcu_fpga_batch.tcl" 
+#
+# STEP#0: define output directory area.
+#
+
+##if {$argc < 1} {
+#puts  "target_fpga arg must be \[ac701 \| arm_mps3 \| pynz_z2 \| zcu104\]"
+#}
+#set target [lindex $argv 0]
+#puts "target requested : $target"
+#set target_dir target_fpga
+#append target_dir $target
+#puts "target directory : $target_dir"
+
+set outputDir ./vivado/built_mcu_fpga
+file mkdir $outputDir
+#
+# STEP#1: setup design sources and constraints
+#
+
+# local search path for configurations
+set search_path ../verilog
+
+set cortexm0_vlog    ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical
+source scripts/rtl_source_cm0.tcl
+
+set search_path [ concat $search_path $cortexm0_vlog/cortexm0_integration/verilog ]
+read_verilog  [ glob $cortexm0_vlog/cortexm0_integration/verilog/*.v ]
+read_verilog  [ glob $cortexm0_vlog/models/cells/*.v ]
+
+# Arm unmodified CMSDK RTL
+set cmsdk_vlog    ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0
+source scripts/rtl_source_cmsdk.tcl
+
+set search_path [ concat $search_path $cmsdk_vlog/logical/models/memories ]
+read_verilog  $cmsdk_vlog/logical/models/memories/cmsdk_ahb_memory_models_defs.v
+read_verilog  $cmsdk_vlog/logical/models/memories/cmsdk_ahb_rom.v
+read_verilog  $cmsdk_vlog/logical/models/memories/cmsdk_fpga_rom.v
+read_verilog  $cmsdk_vlog/logical/models/memories/cmsdk_ahb_ram.v
+read_verilog  $cmsdk_vlog/logical/models/memories/cmsdk_fpga_sram.v
+
+# ADP, FT1248 and streamio IP
+source scripts/rtl_source_soclabs_ip.tcl
+
+# FPGA-specific pads
+source scripts/rtl_source_fpga_ip.tcl
+
+# soclabs modified mcu system 
+set soc_vlog ../verilog
+read_verilog  $soc_vlog/cmsdk_mcu_defs.v
+read_verilog  $soc_vlog/ahb_bootrom.v
+read_verilog  $soc_vlog/bootrom.v
+read_verilog  $soc_vlog/cmsdk_ahb_cs_rom_table.v
+read_verilog  $soc_vlog/cmsdk_apb_usrt.v
+read_verilog  $soc_vlog/cmsdk_mcu_addr_decode.v
+read_verilog  $soc_vlog/cmsdk_mcu_clkctrl.v
+read_verilog  $soc_vlog/cmsdk_mcu_pin_mux.v
+read_verilog  $soc_vlog/cmsdk_mcu_stclkctrl.v
+read_verilog  $soc_vlog/cmsdk_mcu_sysctrl.v
+read_verilog  $soc_vlog/cmsdk_mcu_system.v
+read_verilog  $soc_vlog/cmsdk_mcu_chip.v
+
+# FPGA specific timing constraints
+read_xdc target_fpga/fpga_timing.xdc
+
+# FPGA board specific pin constraints
+read_xdc target_fpga/fpga_pinmap.xdc
+
+#
+# STEP#2: run synthesis, report utilization and timing estimates, write checkpoint design
+#
+source target_fpga/fpga_synth.tcl
+
+write_checkpoint -force $outputDir/post_synth
+report_timing_summary -file $outputDir/post_synth_timing_summary.rpt
+report_power -file $outputDir/post_synth_power.rpt
+#
+# STEP#3: run placement and logic optimzation, report utilization and timing estimates, write checkpoint design
+#
+opt_design
+place_design
+phys_opt_design
+write_checkpoint -force $outputDir/post_place
+report_timing_summary -file $outputDir/post_place_timing_summary.rpt
+#
+# STEP#4: run router, report actual utilization and timing, write checkpoint design, run drc, write verilog and xdc out
+#
+route_design
+write_checkpoint -force $outputDir/post_route
+report_timing_summary -file $outputDir/post_route_timing_summary.rpt
+report_timing -sort_by group -max_paths 100 -path_type summary -file $outputDir/post_route_timing.rpt
+report_clock_utilization -file $outputDir/clock_util.rpt
+report_utilization -file $outputDir/post_route_util.rpt
+report_power -file $outputDir/post_route_power.rpt
+report_drc -file $outputDir/post_imp_drc.rpt
+write_verilog -force $outputDir/cmsdk_mcu_impl_netlist.v
+write_xdc -no_fixed_only -force $outputDir/cmsdk_mcu_impl.xdc
+#
+# STEP#5: generate a bitstream
+# 
+write_bitstream -force $outputDir/cmsdk_mcu.bit
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/rtl_source_cm0.tcl b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/rtl_source_cm0.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..b76287f3995fc4ff1584a546bf0c82dc5d4c3217
--- /dev/null
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/rtl_source_cm0.tcl
@@ -0,0 +1,17 @@
+### Cortex-M0 rtl source build
+set search_path [ concat $search_path $cortexm0_vlog/cortexm0/verilog ]
+read_verilog  [ glob $cortexm0_vlog/cortexm0/verilog/*.v ]
+set search_path [ concat $search_path $cortexm0_vlog/cortexm0_dap/verilog ]
+##read_verilog  [ glob $cortexm0_vlog/cortexm0_dap/verilog/*.v ]
+read_verilog $cortexm0_vlog/cortexm0_dap/verilog/cm0_dap_ap_cdc.v
+read_verilog $cortexm0_vlog/cortexm0_dap/verilog/cm0_dap_ap_mast.v
+read_verilog $cortexm0_vlog/cortexm0_dap/verilog/cm0_dap_dp_cdc.v
+read_verilog $cortexm0_vlog/cortexm0_dap/verilog/cm0_dap_dp_jtag.v
+###read_verilog $cortexm0_vlog/cortexm0_dap/verilog/cm0_dap_dp_sw_defs.v
+read_verilog $cortexm0_vlog/cortexm0_dap/verilog/cm0_dap_dp.v
+###read_verilog $cortexm0_vlog/cortexm0_dap/verilog/cm0_dap_ap_mast_defs.v
+read_verilog $cortexm0_vlog/cortexm0_dap/verilog/cm0_dap_ap.v
+###read_verilog $cortexm0_vlog/cortexm0_dap/verilog/cm0_dap_dp_jtag_defs.v
+read_verilog $cortexm0_vlog/cortexm0_dap/verilog/cm0_dap_dp_pwr.v
+read_verilog $cortexm0_vlog/cortexm0_dap/verilog/cm0_dap_dp_sw.v
+read_verilog $cortexm0_vlog/cortexm0_dap/verilog/CORTEXM0DAP.v
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/rtl_source_cmsdk.tcl b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/rtl_source_cmsdk.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..82e06a0c38457014fd00edff9454fefae614f4cf
--- /dev/null
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/rtl_source_cmsdk.tcl
@@ -0,0 +1,18 @@
+### CMSDK rtl source build
+###read_verilog  [ glob $cmsdk_vlog/logical/cmsdk_ahb_gpio/verilog/*.v ]
+read_verilog  $cmsdk_vlog/logical/cmsdk_ahb_gpio/verilog/cmsdk_ahb_to_iop.v
+read_verilog  $cmsdk_vlog/logical/cmsdk_ahb_gpio/verilog/cmsdk_ahb_gpio.v
+read_verilog  $cmsdk_vlog/logical/cmsdk_iop_gpio/verilog/cmsdk_iop_gpio.v
+read_verilog  [ glob $cmsdk_vlog/logical/cmsdk_apb_timer/verilog/*.v ]
+read_verilog  [ glob $cmsdk_vlog/logical/cmsdk_apb_dualtimers/verilog/*.v ]
+read_verilog  [ glob $cmsdk_vlog/logical/cmsdk_apb_watchdog/verilog/*.v ]
+read_verilog  [ glob $cmsdk_vlog/logical/cmsdk_apb_uart/verilog/*.v ]
+read_verilog  $cmsdk_vlog/logical/cmsdk_ahb_default_slave/verilog/cmsdk_ahb_default_slave.v
+read_verilog  [ glob $cmsdk_vlog/logical/cmsdk_ahb_slave_mux/verilog/*.v ]
+read_verilog  [ glob $cmsdk_vlog/logical/cmsdk_ahb_to_apb/verilog/*.v ]
+read_verilog  [ glob $cmsdk_vlog/logical/cmsdk_apb_slave_mux/verilog/*.v ]
+read_verilog  [ glob $cmsdk_vlog/logical/cmsdk_apb_subsystem/verilog/*.v ]
+read_verilog  [ glob $cmsdk_vlog/logical/cmsdk_ahb_bitband/verilog/*.v ]
+read_verilog  [ glob $cmsdk_vlog/logical/cmsdk_ahb_master_mux/verilog/*.v ]
+read_verilog  $cmsdk_vlog/logical/models/clkgate/cmsdk_clock_gate.v
+read_verilog  $cmsdk_vlog/logical/cmsdk_ahb_to_sram/verilog/cmsdk_ahb_to_sram.v
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/rtl_source_fpga_ip.tcl b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/rtl_source_fpga_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..376d757658bf7dc98669ac9c626075f3126f64c0
--- /dev/null
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/rtl_source_fpga_ip.tcl
@@ -0,0 +1,9 @@
+# rtl_source_fpga_ip.tcl
+#
+
+set fpgalib_vlog ../../../../../FPGALIB
+read_verilog  $fpgalib_vlog/pads/verilog/PAD_INOUT8MA_NOE.v
+read_verilog  $fpgalib_vlog/pads/verilog/PAD_VDDIO.v
+read_verilog  $fpgalib_vlog/pads/verilog/PAD_VSSIO.v
+read_verilog  $fpgalib_vlog/pads/verilog/PAD_VDDSOC.v
+read_verilog  $fpgalib_vlog/pads/verilog/PAD_VSS.v
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/rtl_source_soclabs_ip.tcl b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/rtl_source_soclabs_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..a661717b3f1593e6f4733a14831e72d568ffea3c
--- /dev/null
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/rtl_source_soclabs_ip.tcl
@@ -0,0 +1,7 @@
+# rtl_source_soclabs_ip.tcl
+#
+
+set iplib_vlog   ../../../../../IPLIB
+read_verilog  $iplib_vlog/FT1248_streamio_v1_0/ft1248_streamio_v1_0.v
+read_verilog  $iplib_vlog/ADPcontrol_v1_0/ADPcontrol_v1_0.v
+read_verilog  $iplib_vlog/ADPcontrol_v1_0/ADPmanager.v
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_ac701/fpga_pinmap.xdc b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_ac701/fpga_pinmap.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..b8889af48409d7409031d5229f5949e72f9dc5ef
--- /dev/null
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_ac701/fpga_pinmap.xdc
@@ -0,0 +1,983 @@
+##################################################################################
+##                                                                              ##
+## AC701 Master XDC                                                             ##
+##                                                                              ##
+##################################################################################
+
+set_property CFGBVS VCCO [current_design]
+
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+
+##set_property PACKAGE_PIN AB22 [get_ports No]
+##set_property IOSTANDARD LVCMOS25 [get_ports No]
+##set_property PACKAGE_PIN AE25 [get_ports FMC1_HPC_HA02_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA02_P]
+##set_property PACKAGE_PIN AE26 [get_ports FMC1_HPC_HA02_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA02_N]
+##set_property PACKAGE_PIN AC22 [get_ports FMC1_HPC_HA03_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA03_P]
+##set_property PACKAGE_PIN AC23 [get_ports FMC1_HPC_HA03_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA03_N]
+##set_property PACKAGE_PIN AF24 [get_ports FMC1_HPC_HA04_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA04_P]
+##set_property PACKAGE_PIN AF25 [get_ports FMC1_HPC_HA04_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA04_N]
+##set_property PACKAGE_PIN AD25 [get_ports FMC1_HPC_HA05_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA05_P]
+##set_property PACKAGE_PIN AD26 [get_ports FMC1_HPC_HA05_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA05_N]
+##set_property PACKAGE_PIN AE23 [get_ports FMC1_HPC_HA06_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA06_P]
+##set_property PACKAGE_PIN AF23 [get_ports FMC1_HPC_HA06_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA06_N]
+##set_property PACKAGE_PIN AD23 [get_ports FMC1_HPC_HA07_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA07_P]
+##set_property PACKAGE_PIN AD24 [get_ports FMC1_HPC_HA07_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA07_N]
+##set_property PACKAGE_PIN AD21 [get_ports FMC1_HPC_HA08_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA08_P]
+##set_property PACKAGE_PIN AE21 [get_ports FMC1_HPC_HA08_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA08_N]
+##set_property PACKAGE_PIN AF19 [get_ports FMC1_HPC_HA09_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA09_P]
+##set_property PACKAGE_PIN AF20 [get_ports FMC1_HPC_HA09_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA09_N]
+##set_property PACKAGE_PIN AE22 [get_ports FMC1_HPC_HA10_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA10_P]
+##set_property PACKAGE_PIN AF22 [get_ports FMC1_HPC_HA10_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA10_N]
+##set_property PACKAGE_PIN AD20 [get_ports FMC1_HPC_HA11_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA11_P]
+##set_property PACKAGE_PIN AE20 [get_ports FMC1_HPC_HA11_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA11_N]
+##set_property PACKAGE_PIN AB21 [get_ports FMC1_HPC_HA01_CC_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA01_CC_P]
+##set_property PACKAGE_PIN AC21 [get_ports FMC1_HPC_HA01_CC_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA01_CC_N]
+##set_property PACKAGE_PIN AA20 [get_ports FMC1_HPC_HA17_CC_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA17_CC_P]
+##set_property PACKAGE_PIN AB20 [get_ports FMC1_HPC_HA17_CC_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA17_CC_N]
+##set_property PACKAGE_PIN AA19 [get_ports FMC1_HPC_HA00_CC_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA00_CC_P]
+##set_property PACKAGE_PIN AB19 [get_ports FMC1_HPC_HA00_CC_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA00_CC_N]
+##set_property PACKAGE_PIN AC19 [get_ports FMC1_HPC_HA12_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA12_P]
+##set_property PACKAGE_PIN AD19 [get_ports FMC1_HPC_HA12_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA12_N]
+##set_property PACKAGE_PIN AC18 [get_ports FMC1_HPC_HA13_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA13_P]
+##set_property PACKAGE_PIN AD18 [get_ports FMC1_HPC_HA13_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA13_N]
+##set_property PACKAGE_PIN AE18 [get_ports FMC1_HPC_HA14_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA14_P]
+##set_property PACKAGE_PIN AF18 [get_ports FMC1_HPC_HA14_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA14_N]
+##set_property PACKAGE_PIN Y18 [get_ports FMC1_HPC_HA15_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA15_P]
+##set_property PACKAGE_PIN AA18 [get_ports FMC1_HPC_HA15_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA15_N]
+##set_property PACKAGE_PIN AE17 [get_ports FMC1_HPC_HA16_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA16_P]
+##set_property PACKAGE_PIN AF17 [get_ports FMC1_HPC_HA16_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA16_N]
+##set_property PACKAGE_PIN AA17 [get_ports FMC1_HPC_HA18_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA18_P]
+##set_property PACKAGE_PIN AB17 [get_ports FMC1_HPC_HA18_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA18_N]
+##set_property PACKAGE_PIN AC17 [get_ports FMC1_HPC_HA19_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA19_P]
+##set_property PACKAGE_PIN AD17 [get_ports FMC1_HPC_HA19_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA19_N]
+##set_property PACKAGE_PIN Y16 [get_ports FMC1_HPC_HA20_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA20_P]
+##set_property PACKAGE_PIN Y17 [get_ports FMC1_HPC_HA20_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA20_N]
+##set_property PACKAGE_PIN AB16 [get_ports FMC1_HPC_HA21_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA21_P]
+##set_property PACKAGE_PIN AC16 [get_ports FMC1_HPC_HA21_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA21_N]
+##set_property PACKAGE_PIN Y15 [get_ports FMC1_HPC_HA22_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA22_P]
+##set_property PACKAGE_PIN AA15 [get_ports FMC1_HPC_HA22_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA22_N]
+##set_property PACKAGE_PIN W14 [get_ports FMC1_HPC_HA23_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA23_P]
+##set_property PACKAGE_PIN W15 [get_ports FMC1_HPC_HA23_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA23_N]
+##set_property PACKAGE_PIN W16 [get_ports No]
+##set_property IOSTANDARD LVCMOS25 [get_ports No]
+##set_property PACKAGE_PIN U24 [get_ports HDMI_R_D21]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D21]
+##set_property PACKAGE_PIN U25 [get_ports HDMI_R_D16]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D16]
+##set_property PACKAGE_PIN U26 [get_ports HDMI_R_D11]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D11]
+##set_property PACKAGE_PIN V26 [get_ports HDMI_R_D7]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D7]
+##set_property PACKAGE_PIN W26 [get_ports HDMI_R_D8]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D8]
+##set_property PACKAGE_PIN AB26 [get_ports HDMI_R_DE]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_DE]
+##set_property PACKAGE_PIN AC26 [get_ports HDMI_R_VSYNC]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_VSYNC]
+##set_property PACKAGE_PIN W25 [get_ports HDMI_R_D9]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D9]
+##set_property PACKAGE_PIN Y26 [get_ports HDMI_R_D6]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D6]
+##set_property PACKAGE_PIN Y25 [get_ports HDMI_R_D5]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D5]
+##set_property PACKAGE_PIN AA25 [get_ports HDMI_R_D29]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D29]
+##set_property PACKAGE_PIN V24 [get_ports HDMI_R_D17]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D17]
+##set_property PACKAGE_PIN W24 [get_ports HDMI_R_D10]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D10]
+##set_property PACKAGE_PIN AA24 [get_ports HDMI_R_D4]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D4]
+##set_property PACKAGE_PIN AB25 [get_ports HDMI_R_D30]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D30]
+##set_property PACKAGE_PIN AA22 [get_ports HDMI_R_HSYNC]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_HSYNC]
+##set_property PACKAGE_PIN AA23 [get_ports HDMI_R_D28]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D28]
+##set_property PACKAGE_PIN AB24 [get_ports HDMI_R_D32]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D32]
+##set_property PACKAGE_PIN AC24 [get_ports HDMI_R_D31]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D31]
+##set_property PACKAGE_PIN V23 [get_ports HDMI_R_D23]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D23]
+##set_property PACKAGE_PIN W23 [get_ports HDMI_R_D19]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D19]
+##set_property PACKAGE_PIN Y22 [get_ports HDMI_R_D33]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D33]
+##set_property PACKAGE_PIN Y23 [get_ports HDMI_R_D34]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D34]
+##set_property INTERNAL_VREF 0.90 [get_iobanks 13]
+##set_property PACKAGE_PIN U22 [get_ports PHY_TX_CLK]
+##set_property IOSTANDARD HSTL_I_18 [get_ports PHY_TX_CLK]
+##set_property PACKAGE_PIN V22 [get_ports HDMI_R_D35]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D35]
+##set_property PACKAGE_PIN U21 [get_ports PHY_RX_CLK]
+##set_property IOSTANDARD HSTL_I_18 [get_ports PHY_RX_CLK]
+##set_property PACKAGE_PIN V21 [get_ports HDMI_R_CLK]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_CLK]
+##set_property PACKAGE_PIN W21 [get_ports HDMI_INT]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_INT]
+##set_property PACKAGE_PIN Y21 [get_ports HDMI_R_SPDIF]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_SPDIF]
+##set_property PACKAGE_PIN T20 [get_ports HDMI_SPDIF_OUT_LS]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_SPDIF_OUT_LS]
+##set_property PACKAGE_PIN U20 [get_ports HDMI_R_D18]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D18]
+##set_property PACKAGE_PIN W20 [get_ports HDMI_R_D20]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D20]
+##set_property PACKAGE_PIN Y20 [get_ports HDMI_R_D22]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D22]
+##set_property PACKAGE_PIN T19 [get_ports USB_UART_TX]
+##set_property IOSTANDARD LVCMOS18 [get_ports USB_UART_TX]
+##set_property PACKAGE_PIN U19 [get_ports USB_UART_RX]
+##set_property IOSTANDARD LVCMOS18 [get_ports USB_UART_RX]
+##set_property PACKAGE_PIN V19 [get_ports USB_UART_RTS]
+##set_property IOSTANDARD LVCMOS18 [get_ports USB_UART_RTS]
+##set_property PACKAGE_PIN W19 [get_ports USB_UART_CTS]
+##set_property IOSTANDARD LVCMOS18 [get_ports USB_UART_CTS]
+##set_property PACKAGE_PIN V18 [get_ports PHY_RESET_B]
+##set_property IOSTANDARD LVCMOS18 [get_ports PHY_RESET_B]
+##set_property PACKAGE_PIN W18 [get_ports PHY_MDC]
+##set_property IOSTANDARD LVCMOS18 [get_ports PHY_MDC]
+##set_property PACKAGE_PIN T14 [get_ports PHY_MDIO]
+##set_property IOSTANDARD LVCMOS18 [get_ports PHY_MDIO]
+##set_property PACKAGE_PIN T15 [get_ports PHY_TX_CTRL]
+##set_property IOSTANDARD HSTL_I_18 [get_ports PHY_TX_CTRL]
+##set_property PACKAGE_PIN T17 [get_ports PHY_TXD3]
+##set_property IOSTANDARD HSTL_I_18 [get_ports PHY_TXD3]
+##set_property PACKAGE_PIN T18 [get_ports PHY_TXD2]
+##set_property IOSTANDARD HSTL_I_18 [get_ports PHY_TXD2]
+##set_property PACKAGE_PIN U15 [get_ports PHY_TXD1]
+##set_property IOSTANDARD HSTL_I_18 [get_ports PHY_TXD1]
+##set_property PACKAGE_PIN U16 [get_ports PHY_TXD0]
+##set_property IOSTANDARD HSTL_I_18 [get_ports PHY_TXD0]
+##set_property PACKAGE_PIN U14 [get_ports PHY_RX_CTRL]
+##set_property IOSTANDARD HSTL_I_18 [get_ports PHY_RX_CTRL]
+##set_property PACKAGE_PIN V14 [get_ports PHY_RXD3]
+##set_property IOSTANDARD HSTL_I_18 [get_ports PHY_RXD3]
+##set_property PACKAGE_PIN V16 [get_ports PHY_RXD2]
+##set_property IOSTANDARD HSTL_I_18 [get_ports PHY_RXD2]
+##set_property PACKAGE_PIN V17 [get_ports PHY_RXD1]
+##set_property IOSTANDARD HSTL_I_18 [get_ports PHY_RXD1]
+##set_property PACKAGE_PIN U17 [get_ports PHY_RXD0]
+##set_property IOSTANDARD HSTL_I_18 [get_ports PHY_RXD0]
+##set_property PACKAGE_PIN M19 [get_ports SI5324_INT_ALM_B]
+##set_property IOSTANDARD LVCMOS33 [get_ports SI5324_INT_ALM_B]
+##set_property PACKAGE_PIN R14 [get_ports FLASH_D0]
+##set_property IOSTANDARD LVCMOS33 [get_ports FLASH_D0]
+##set_property PACKAGE_PIN R15 [get_ports FLASH_D1]
+##set_property IOSTANDARD LVCMOS33 [get_ports FLASH_D1]
+##set_property PACKAGE_PIN P14 [get_ports FLASH_D2]
+##set_property IOSTANDARD LVCMOS33 [get_ports FLASH_D2]
+##set_property PACKAGE_PIN N14 [get_ports FLASH_D3]
+##set_property IOSTANDARD LVCMOS33 [get_ports FLASH_D3]
+##set_property PACKAGE_PIN P15 [get_ports CTRL2_PWRGOOD]
+##set_property IOSTANDARD LVCMOS33 [get_ports CTRL2_PWRGOOD]
+##set_property PACKAGE_PIN P16 [get_ports FPGA_EMCCLK]
+##set_property IOSTANDARD LVCMOS33 [get_ports FPGA_EMCCLK]
+##set_property PACKAGE_PIN N16 [get_ports FMC1_HPC_PRSNT_M2C_B]
+##set_property IOSTANDARD LVCMOS33 [get_ports FMC1_HPC_PRSNT_M2C_B]
+##set_property PACKAGE_PIN N17 [get_ports FMC1_HPC_PG_M2C]
+##set_property IOSTANDARD LVCMOS33 [get_ports FMC1_HPC_PG_M2C]
+##set_property PACKAGE_PIN R16 [get_ports FMC_VADJ_ON_B]
+##set_property IOSTANDARD LVCMOS33 [get_ports FMC_VADJ_ON_B]
+##set_property PACKAGE_PIN R17 [get_ports IIC_MUX_RESET_B]
+##set_property IOSTANDARD LVCMOS33 [get_ports IIC_MUX_RESET_B]
+##set_property PACKAGE_PIN P18 [get_ports QSPI_IC_CS_B]
+##set_property IOSTANDARD LVCMOS33 [get_ports QSPI_IC_CS_B]
+##set_property PACKAGE_PIN N18 [get_ports IIC_SCL_MAIN]
+##set_property IOSTANDARD LVCMOS33 [get_ports IIC_SCL_MAIN]
+##set_property PACKAGE_PIN K25 [get_ports IIC_SDA_MAIN]
+##set_property IOSTANDARD LVCMOS33 [get_ports IIC_SDA_MAIN]
+##set_property PACKAGE_PIN K26 [get_ports PCIE_WAKE_B]
+##set_property IOSTANDARD LVCMOS33 [get_ports PCIE_WAKE_B]
+##set_property PACKAGE_PIN M20 [get_ports PCIE_PERST]
+##set_property IOSTANDARD LVCMOS33 [get_ports PCIE_PERST]
+##set_property PACKAGE_PIN L20 [get_ports LCD_E_LS]
+##set_property IOSTANDARD LVCMOS33 [get_ports LCD_E_LS]
+##set_property PACKAGE_PIN L24 [get_ports LCD_RW_LS]
+##set_property IOSTANDARD LVCMOS33 [get_ports LCD_RW_LS]
+##set_property PACKAGE_PIN L25 [get_ports LCD_DB4_LS]
+##set_property IOSTANDARD LVCMOS33 [get_ports LCD_DB4_LS]
+##set_property PACKAGE_PIN M24 [get_ports LCD_DB5_LS]
+##set_property IOSTANDARD LVCMOS33 [get_ports LCD_DB5_LS]
+##set_property PACKAGE_PIN M25 [get_ports LCD_DB6_LS]
+##set_property IOSTANDARD LVCMOS33 [get_ports LCD_DB6_LS]
+##set_property PACKAGE_PIN L22 [get_ports LCD_DB7_LS]
+##set_property IOSTANDARD LVCMOS33 [get_ports LCD_DB7_LS]
+##set_property PACKAGE_PIN L23 [get_ports LCD_RS_LS]
+##set_property IOSTANDARD LVCMOS33 [get_ports LCD_RS_LS]
+##set_property PACKAGE_PIN M21 [get_ports USER_CLOCK_P]
+##set_property IOSTANDARD LVDS_25 [get_ports USER_CLOCK_P]
+##set_property PACKAGE_PIN M22 [get_ports USER_CLOCK_N]
+##set_property IOSTANDARD LVDS_25 [get_ports USER_CLOCK_N]
+##set_property PACKAGE_PIN N21 [get_ports ROTARY_PUSH]
+##set_property IOSTANDARD LVCMOS33 [get_ports ROTARY_PUSH]
+##set_property PACKAGE_PIN N22 [get_ports ROTARY_INCA]
+##set_property IOSTANDARD LVCMOS33 [get_ports ROTARY_INCA]
+##set_property PACKAGE_PIN P20 [get_ports ROTARY_INCB]
+##set_property IOSTANDARD LVCMOS33 [get_ports ROTARY_INCB]
+##set_property PACKAGE_PIN P21 [get_ports SDIO_CD_DAT3]
+##set_property IOSTANDARD LVCMOS33 [get_ports SDIO_CD_DAT3]
+##set_property PACKAGE_PIN N23 [get_ports SDIO_CMD]
+##set_property IOSTANDARD LVCMOS33 [get_ports SDIO_CMD]
+##set_property PACKAGE_PIN N24 [get_ports SDIO_CLK]
+##set_property IOSTANDARD LVCMOS33 [get_ports SDIO_CLK]
+##set_property PACKAGE_PIN P19 [get_ports SDIO_DAT0]
+##set_property IOSTANDARD LVCMOS33 [get_ports SDIO_DAT0]
+##set_property PACKAGE_PIN N19 [get_ports SDIO_DAT1]
+##set_property IOSTANDARD LVCMOS33 [get_ports SDIO_DAT1]
+##set_property PACKAGE_PIN P23 [get_ports SDIO_DAT2]
+##set_property IOSTANDARD LVCMOS33 [get_ports SDIO_DAT2]
+##set_property PACKAGE_PIN P24 [get_ports SDIO_SDDET]
+##set_property IOSTANDARD LVCMOS33 [get_ports SDIO_SDDET]
+##set_property PACKAGE_PIN R20 [get_ports SDIO_SDWP]
+##set_property IOSTANDARD LVCMOS33 [get_ports SDIO_SDWP]
+##set_property PACKAGE_PIN R21 [get_ports PMBUS_CLK_LS]
+##set_property IOSTANDARD LVCMOS33 [get_ports PMBUS_CLK_LS]
+##set_property PACKAGE_PIN R25 [get_ports PMBUS_DATA_LS]
+##set_property IOSTANDARD LVCMOS33 [get_ports PMBUS_DATA_LS]
+##set_property PACKAGE_PIN P25 [get_ports PMBUS_CTRL_LS]
+##set_property IOSTANDARD LVCMOS33 [get_ports PMBUS_CTRL_LS]
+##set_property PACKAGE_PIN N26 [get_ports PMBUS_ALERT_LS]
+##set_property IOSTANDARD LVCMOS33 [get_ports PMBUS_ALERT_LS]
+##set_property PACKAGE_PIN M26 [get_ports GPIO_LED_0]
+##set_property IOSTANDARD LVCMOS33 [get_ports GPIO_LED_0]
+##set_property PACKAGE_PIN T24 [get_ports GPIO_LED_1]
+##set_property IOSTANDARD LVCMOS33 [get_ports GPIO_LED_1]
+##set_property PACKAGE_PIN T25 [get_ports GPIO_LED_2]
+##set_property IOSTANDARD LVCMOS33 [get_ports GPIO_LED_2]
+##set_property PACKAGE_PIN R26 [get_ports GPIO_LED_3]
+##set_property IOSTANDARD LVCMOS33 [get_ports GPIO_LED_3]
+##set_property PACKAGE_PIN P26 [get_ports PMOD_0]
+##set_property IOSTANDARD LVCMOS33 [get_ports PMOD_0]
+##set_property PACKAGE_PIN T22 [get_ports PMOD_1]
+##set_property IOSTANDARD LVCMOS33 [get_ports PMOD_1]
+##set_property PACKAGE_PIN R22 [get_ports PMOD_2]
+##set_property IOSTANDARD LVCMOS33 [get_ports PMOD_2]
+##set_property PACKAGE_PIN T23 [get_ports PMOD_3]
+##set_property IOSTANDARD LVCMOS33 [get_ports PMOD_3]
+##set_property PACKAGE_PIN R23 [get_ports SFP_LOS]
+##set_property IOSTANDARD LVCMOS33 [get_ports SFP_LOS]
+##set_property PACKAGE_PIN R18 [get_ports SFP_TX_DISABLE]
+##set_property IOSTANDARD LVCMOS33 [get_ports SFP_TX_DISABLE]
+##set_property PACKAGE_PIN K18 [get_ports XADC_GPIO_2]
+##set_property IOSTANDARD LVCMOS25 [get_ports XADC_GPIO_2]
+##set_property PACKAGE_PIN K15 [get_ports XADC_VAUX0_R_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports XADC_VAUX0_R_P]
+##set_property PACKAGE_PIN J16 [get_ports XADC_VAUX0_R_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports XADC_VAUX0_R_N]
+##set_property PACKAGE_PIN J14 [get_ports XADC_VAUX8_R_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports XADC_VAUX8_R_P]
+##set_property PACKAGE_PIN J15 [get_ports XADC_VAUX8_R_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports XADC_VAUX8_R_N]
+##set_property PACKAGE_PIN K16 [get_ports XADC_AD1_R_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports XADC_AD1_R_P]
+##set_property PACKAGE_PIN K17 [get_ports XADC_AD1_R_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports XADC_AD1_R_N]
+##set_property PACKAGE_PIN M14 [get_ports FMC1_HPC_LA19_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA19_P]
+##set_property PACKAGE_PIN L14 [get_ports FMC1_HPC_LA19_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA19_N]
+##set_property PACKAGE_PIN M15 [get_ports XADC_AD9_R_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports XADC_AD9_R_P]
+##set_property PACKAGE_PIN L15 [get_ports XADC_AD9_R_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports XADC_AD9_R_N]
+##set_property PACKAGE_PIN M16 [get_ports FMC1_HPC_LA20_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA20_P]
+##set_property PACKAGE_PIN M17 [get_ports FMC1_HPC_LA20_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA20_N]
+##set_property PACKAGE_PIN J19 [get_ports FMC1_HPC_LA21_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA21_P]
+##set_property PACKAGE_PIN H19 [get_ports FMC1_HPC_LA21_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA21_N]
+##set_property PACKAGE_PIN L17 [get_ports FMC1_HPC_LA22_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA22_P]
+##set_property PACKAGE_PIN L18 [get_ports FMC1_HPC_LA22_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA22_N]
+##set_property PACKAGE_PIN K20 [get_ports FMC1_HPC_LA23_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA23_P]
+##set_property PACKAGE_PIN J20 [get_ports FMC1_HPC_LA23_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA23_N]
+##set_property PACKAGE_PIN J18 [get_ports FMC1_HPC_LA24_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA24_P]
+##set_property PACKAGE_PIN H18 [get_ports FMC1_HPC_LA24_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA24_N]
+##set_property PACKAGE_PIN G20 [get_ports FMC1_HPC_LA18_CC_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA18_CC_P]
+##set_property PACKAGE_PIN G21 [get_ports FMC1_HPC_LA18_CC_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA18_CC_N]
+##set_property PACKAGE_PIN K21 [get_ports FMC1_HPC_LA17_CC_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA17_CC_P]
+##set_property PACKAGE_PIN J21 [get_ports FMC1_HPC_LA17_CC_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA17_CC_N]
+##set_property PACKAGE_PIN H21 [get_ports FMC1_HPC_CLK1_M2C_P]
+##set_property IOSTANDARD LVDS_25 [get_ports FMC1_HPC_CLK1_M2C_P]
+##set_property PACKAGE_PIN H22 [get_ports FMC1_HPC_CLK1_M2C_N]
+##set_property IOSTANDARD LVDS_25 [get_ports FMC1_HPC_CLK1_M2C_N]
+##set_property PACKAGE_PIN J23 [get_ports USER_SMA_CLOCK_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports USER_SMA_CLOCK_P]
+##set_property PACKAGE_PIN H23 [get_ports USER_SMA_CLOCK_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports USER_SMA_CLOCK_N]
+##set_property PACKAGE_PIN G22 [get_ports FMC1_HPC_LA25_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA25_P]
+##set_property PACKAGE_PIN F22 [get_ports FMC1_HPC_LA25_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA25_N]
+##set_property PACKAGE_PIN J24 [get_ports FMC1_HPC_LA26_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA26_P]
+##set_property PACKAGE_PIN H24 [get_ports FMC1_HPC_LA26_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA26_N]
+##set_property PACKAGE_PIN F23 [get_ports FMC1_HPC_LA27_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA27_P]
+##set_property PACKAGE_PIN E23 [get_ports FMC1_HPC_LA27_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA27_N]
+##set_property PACKAGE_PIN K22 [get_ports FMC1_HPC_LA28_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA28_P]
+##set_property PACKAGE_PIN K23 [get_ports FMC1_HPC_LA28_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA28_N]
+##set_property PACKAGE_PIN G24 [get_ports FMC1_HPC_LA29_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA29_P]
+##set_property PACKAGE_PIN F24 [get_ports FMC1_HPC_LA29_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA29_N]
+##set_property PACKAGE_PIN E25 [get_ports FMC1_HPC_LA30_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA30_P]
+##set_property PACKAGE_PIN D25 [get_ports FMC1_HPC_LA30_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA30_N]
+##set_property PACKAGE_PIN E26 [get_ports FMC1_HPC_LA31_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA31_P]
+##set_property PACKAGE_PIN D26 [get_ports FMC1_HPC_LA31_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA31_N]
+##set_property PACKAGE_PIN H26 [get_ports FMC1_HPC_LA32_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA32_P]
+##set_property PACKAGE_PIN G26 [get_ports FMC1_HPC_LA32_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA32_N]
+##set_property PACKAGE_PIN G25 [get_ports FMC1_HPC_LA33_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA33_P]
+##set_property PACKAGE_PIN F25 [get_ports FMC1_HPC_LA33_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA33_N]
+##set_property PACKAGE_PIN J25 [get_ports SM_FAN_TACH]
+##set_property IOSTANDARD LVCMOS25 [get_ports SM_FAN_TACH]
+##set_property PACKAGE_PIN J26 [get_ports SM_FAN_PWM]
+##set_property IOSTANDARD LVCMOS25 [get_ports SM_FAN_PWM]
+##set_property PACKAGE_PIN L19 [get_ports XADC_GPIO_3]
+##set_property IOSTANDARD LVCMOS25 [get_ports XADC_GPIO_3]
+##set_property PACKAGE_PIN H17 [get_ports XADC_GPIO_0]
+##set_property IOSTANDARD LVCMOS25 [get_ports XADC_GPIO_0]
+##set_property PACKAGE_PIN H14 [get_ports FMC1_HPC_LA02_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA02_P]
+##set_property PACKAGE_PIN H15 [get_ports FMC1_HPC_LA02_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA02_N]
+##set_property PACKAGE_PIN G17 [get_ports FMC1_HPC_LA03_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA03_P]
+##set_property PACKAGE_PIN F17 [get_ports FMC1_HPC_LA03_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA03_N]
+##set_property PACKAGE_PIN F18 [get_ports FMC1_HPC_LA04_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA04_P]
+##set_property PACKAGE_PIN F19 [get_ports FMC1_HPC_LA04_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA04_N]
+##set_property PACKAGE_PIN G15 [get_ports FMC1_HPC_LA05_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA05_P]
+##set_property PACKAGE_PIN F15 [get_ports FMC1_HPC_LA05_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA05_N]
+##set_property PACKAGE_PIN G19 [get_ports FMC1_HPC_LA06_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA06_P]
+##set_property PACKAGE_PIN F20 [get_ports FMC1_HPC_LA06_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA06_N]
+##set_property PACKAGE_PIN H16 [get_ports FMC1_HPC_LA07_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA07_P]
+##set_property PACKAGE_PIN G16 [get_ports FMC1_HPC_LA07_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA07_N]
+##set_property PACKAGE_PIN C17 [get_ports FMC1_HPC_LA08_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA08_P]
+##set_property PACKAGE_PIN B17 [get_ports FMC1_HPC_LA08_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA08_N]
+##set_property PACKAGE_PIN E16 [get_ports FMC1_HPC_LA09_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA09_P]
+##set_property PACKAGE_PIN D16 [get_ports FMC1_HPC_LA09_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA09_N]
+##set_property PACKAGE_PIN A17 [get_ports FMC1_HPC_LA10_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA10_P]
+##set_property PACKAGE_PIN A18 [get_ports FMC1_HPC_LA10_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA10_N]
+##set_property PACKAGE_PIN B19 [get_ports FMC1_HPC_LA11_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA11_P]
+##set_property PACKAGE_PIN A19 [get_ports FMC1_HPC_LA11_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA11_N]
+##set_property PACKAGE_PIN E17 [get_ports FMC1_HPC_LA01_CC_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA01_CC_P]
+##set_property PACKAGE_PIN E18 [get_ports FMC1_HPC_LA01_CC_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA01_CC_N]
+##set_property PACKAGE_PIN D18 [get_ports FMC1_HPC_LA00_CC_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA00_CC_P]
+##set_property PACKAGE_PIN C18 [get_ports FMC1_HPC_LA00_CC_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA00_CC_N]
+##set_property PACKAGE_PIN D19 [get_ports FMC1_HPC_CLK0_M2C_P]
+##set_property IOSTANDARD LVDS_25 [get_ports FMC1_HPC_CLK0_M2C_P]
+##set_property PACKAGE_PIN C19 [get_ports FMC1_HPC_CLK0_M2C_N]
+##set_property IOSTANDARD LVDS_25 [get_ports FMC1_HPC_CLK0_M2C_N]
+##set_property PACKAGE_PIN E20 [get_ports FMC1_HPC_LA12_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA12_P]
+##set_property PACKAGE_PIN D20 [get_ports FMC1_HPC_LA12_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA12_N]
+##set_property PACKAGE_PIN B20 [get_ports FMC1_HPC_LA13_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA13_P]
+##set_property PACKAGE_PIN A20 [get_ports FMC1_HPC_LA13_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA13_N]
+##set_property PACKAGE_PIN C21 [get_ports FMC1_HPC_LA14_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA14_P]
+##set_property PACKAGE_PIN B21 [get_ports FMC1_HPC_LA14_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA14_N]
+##set_property PACKAGE_PIN B22 [get_ports FMC1_HPC_LA15_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA15_P]
+##set_property PACKAGE_PIN A22 [get_ports FMC1_HPC_LA15_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA15_N]
+##set_property PACKAGE_PIN E21 [get_ports FMC1_HPC_LA16_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA16_P]
+##set_property PACKAGE_PIN D21 [get_ports FMC1_HPC_LA16_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA16_N]
+##set_property PACKAGE_PIN C22 [get_ports No]
+##set_property IOSTANDARD LVCMOS25 [get_ports No]
+##set_property PACKAGE_PIN C23 [get_ports No]
+##set_property IOSTANDARD LVCMOS25 [get_ports No]
+##set_property PACKAGE_PIN B25 [get_ports XADC_MUX_ADDR0_LS]
+##set_property IOSTANDARD LVCMOS25 [get_ports XADC_MUX_ADDR0_LS]
+##set_property PACKAGE_PIN A25 [get_ports XADC_MUX_ADDR1_LS]
+##set_property IOSTANDARD LVCMOS25 [get_ports XADC_MUX_ADDR1_LS]
+##set_property PACKAGE_PIN A23 [get_ports XADC_MUX_ADDR2_LS]
+##set_property IOSTANDARD LVCMOS25 [get_ports XADC_MUX_ADDR2_LS]
+##set_property PACKAGE_PIN A24 [get_ports PCIE_MGT_CLK_SEL0]
+##set_property IOSTANDARD LVCMOS25 [get_ports PCIE_MGT_CLK_SEL0]
+##set_property PACKAGE_PIN C26 [get_ports PCIE_MGT_CLK_SEL1]
+##set_property IOSTANDARD LVCMOS25 [get_ports PCIE_MGT_CLK_SEL1]
+##set_property PACKAGE_PIN B26 [get_ports SFP_MGT_CLK_SEL0]
+##set_property IOSTANDARD LVCMOS25 [get_ports SFP_MGT_CLK_SEL0]
+##set_property PACKAGE_PIN C24 [get_ports SFP_MGT_CLK_SEL1]
+##set_property IOSTANDARD LVCMOS25 [get_ports SFP_MGT_CLK_SEL1]
+##set_property PACKAGE_PIN B24 [get_ports SI5324_RST_LS_B]
+##set_property IOSTANDARD LVCMOS25 [get_ports SI5324_RST_LS_B]
+##set_property PACKAGE_PIN D23 [get_ports REC_CLOCK_C_P]
+##set_property IOSTANDARD LVDS_25 [get_ports REC_CLOCK_C_P]
+##set_property PACKAGE_PIN D24 [get_ports REC_CLOCK_C_N]
+##set_property IOSTANDARD LVDS_25 [get_ports REC_CLOCK_C_N]
+##set_property PACKAGE_PIN E22 [get_ports XADC_GPIO_1]
+##set_property IOSTANDARD LVCMOS25 [get_ports XADC_GPIO_1]
+##set_property PACKAGE_PIN V4 [get_ports No]
+##set_property IOSTANDARD LVCMOS15 [get_ports No]
+##set_property PACKAGE_PIN V1 [get_ports DDR3_D31]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D31]
+##set_property PACKAGE_PIN W1 [get_ports DDR3_D30]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D30]
+##set_property PACKAGE_PIN W5 [get_ports DDR3_D29]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D29]
+##set_property PACKAGE_PIN W4 [get_ports DDR3_D28]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D28]
+##set_property PACKAGE_PIN V3 [get_ports DDR3_DQS3_P]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS3_P]
+##set_property PACKAGE_PIN V2 [get_ports DDR3_DQS3_N]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS3_N]
+##set_property PACKAGE_PIN V6 [get_ports DDR3_D27]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D27]
+##set_property PACKAGE_PIN W6 [get_ports DDR3_D26]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D26]
+##set_property PACKAGE_PIN W3 [get_ports DDR3_D25]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D25]
+##set_property PACKAGE_PIN Y3 [get_ports DDR3_D24]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D24]
+##set_property PACKAGE_PIN U7 [get_ports DDR3_DM3]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_DM3]
+##set_property PACKAGE_PIN V7 [get_ports VTTVREF]
+##set_property IOSTANDARD SSTL15 [get_ports VTTVREF]
+##set_property PACKAGE_PIN AB1 [get_ports DDR3_D23]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D23]
+##set_property PACKAGE_PIN AC1 [get_ports DDR3_D22]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D22]
+##set_property PACKAGE_PIN Y2 [get_ports DDR3_D21]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D21]
+##set_property PACKAGE_PIN Y1 [get_ports DDR3_D20]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D20]
+##set_property PACKAGE_PIN AD1 [get_ports DDR3_DQS2_P]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS2_P]
+##set_property PACKAGE_PIN AE1 [get_ports DDR3_DQS2_N]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS2_N]
+##set_property PACKAGE_PIN AE2 [get_ports DDR3_D19]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D19]
+##set_property PACKAGE_PIN AF2 [get_ports DDR3_D18]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D18]
+##set_property PACKAGE_PIN AB2 [get_ports DDR3_D17]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D17]
+##set_property PACKAGE_PIN AC2 [get_ports DDR3_D16]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D16]
+##set_property PACKAGE_PIN AA3 [get_ports DDR3_DM2]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_DM2]
+##set_property PACKAGE_PIN AA2 [get_ports No]
+##set_property IOSTANDARD SSTL15 [get_ports No]
+##set_property PACKAGE_PIN AA4 [get_ports DDR3_D15]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D15]
+##set_property PACKAGE_PIN AB4 [get_ports DDR3_D14]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D14]
+##set_property PACKAGE_PIN AC3 [get_ports DDR3_D13]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D13]
+##set_property PACKAGE_PIN AD3 [get_ports DDR3_D12]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D12]
+##set_property PACKAGE_PIN AD5 [get_ports DDR3_DQS1_P]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS1_P]
+##set_property PACKAGE_PIN AE5 [get_ports DDR3_DQS1_N]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS1_N]
+##set_property PACKAGE_PIN AE3 [get_ports DDR3_D11]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D11]
+##set_property PACKAGE_PIN AF3 [get_ports DDR3_D10]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D10]
+##set_property PACKAGE_PIN AF5 [get_ports DDR3_D9]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D9]
+##set_property PACKAGE_PIN AF4 [get_ports DDR3_D8]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D8]
+##set_property PACKAGE_PIN AC4 [get_ports DDR3_DM1]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_DM1]
+##set_property PACKAGE_PIN AD4 [get_ports No]
+##set_property IOSTANDARD SSTL15 [get_ports No]
+##set_property PACKAGE_PIN Y7 [get_ports DDR3_D7]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D7]
+##set_property PACKAGE_PIN AA7 [get_ports VTTVREF]
+##set_property IOSTANDARD SSTL15 [get_ports VTTVREF]
+##set_property PACKAGE_PIN Y6 [get_ports DDR3_D6]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D6]
+##set_property PACKAGE_PIN Y5 [get_ports DDR3_D5]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D5]
+##set_property PACKAGE_PIN V8 [get_ports DDR3_DQS0_P]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_DQS0_P]
+##set_property PACKAGE_PIN W8 [get_ports DDR3_DQS0_N]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_DQS0_N]
+##set_property PACKAGE_PIN AA5 [get_ports DDR3_D4]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D4]
+##set_property PACKAGE_PIN AB5 [get_ports DDR3_D3]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D3]
+##set_property PACKAGE_PIN Y8 [get_ports DDR3_D2]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D2]
+##set_property PACKAGE_PIN AA8 [get_ports DDR3_D1]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D1]
+##set_property PACKAGE_PIN AB6 [get_ports DDR3_D0]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D0]
+##set_property PACKAGE_PIN AC6 [get_ports DDR3_DM0]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_DM0]
+##set_property PACKAGE_PIN V9 [get_ports No]
+##set_property IOSTANDARD SSTL15 [get_ports No]
+##set_property PACKAGE_PIN N8 [get_ports DDR3_RESET_B]
+##set_property IOSTANDARD LVCMOS15 [get_ports DDR3_RESET_B]
+##set_property PACKAGE_PIN K3 [get_ports DDR3_A9]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_A9]
+##set_property PACKAGE_PIN J3 [get_ports DDR3_A1]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_A1]
+##set_property PACKAGE_PIN M7 [get_ports DDR3_A5]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_A5]
+##set_property PACKAGE_PIN L7 [get_ports DDR3_A12]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_A12]
+##set_property PACKAGE_PIN M4 [get_ports DDR3_A0]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_A0]
+##set_property PACKAGE_PIN L4 [get_ports DDR3_A3]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_A3]
+##set_property PACKAGE_PIN L5 [get_ports DDR3_A11]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_A11]
+##set_property PACKAGE_PIN K5 [get_ports DDR3_A4]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_A4]
+##set_property PACKAGE_PIN N7 [get_ports DDR3_A10]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_A10]
+##set_property PACKAGE_PIN N6 [get_ports DDR3_A13]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_A13]
+##set_property PACKAGE_PIN M6 [get_ports DDR3_A7]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_A7]
+##set_property PACKAGE_PIN M5 [get_ports VTTVREF]
+##set_property IOSTANDARD SSTL15 [get_ports VTTVREF]
+##set_property PACKAGE_PIN K1 [get_ports DDR3_A6]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_A6]
+##set_property PACKAGE_PIN J1 [get_ports DDR3_A2]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_A2]
+##set_property PACKAGE_PIN L3 [get_ports DDR3_A14]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_A14]
+##set_property PACKAGE_PIN K2 [get_ports DDR3_A15]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_A15]
+##set_property PACKAGE_PIN N1 [get_ports DDR3_BA0]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_BA0]
+##set_property PACKAGE_PIN M1 [get_ports DDR3_BA1]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_BA1]
+##set_property PACKAGE_PIN H2 [get_ports DDR3_BA2]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_BA2]
+##set_property PACKAGE_PIN H1 [get_ports DDR3_A8]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_A8]
+##set_property PACKAGE_PIN M2 [get_ports DDR3_CLK0_P]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_CLK0_P]
+##set_property PACKAGE_PIN L2 [get_ports DDR3_CLK0_N]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_CLK0_N]
+##set_property PACKAGE_PIN N3 [get_ports DDR3_CLK1_P]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_CLK1_P]
+##set_property PACKAGE_PIN N2 [get_ports DDR3_CLK1_N]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_CLK1_N]
+##set_property PACKAGE_PIN R3 [get_ports SYSCLK_P]
+##set_property IOSTANDARD LVDS_25 [get_ports SYSCLK_P]
+##set_property PACKAGE_PIN P3 [get_ports SYSCLK_N]
+##set_property IOSTANDARD LVDS_25 [get_ports SYSCLK_N]
+##set_property PACKAGE_PIN P4 [get_ports DDR3_CKE0]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_CKE0]
+##set_property PACKAGE_PIN N4 [get_ports DDR3_CKE1]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_CKE1]
+##set_property PACKAGE_PIN R1 [get_ports DDR3_WE_B]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_WE_B]
+##set_property PACKAGE_PIN P1 [get_ports DDR3_RAS_B]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_RAS_B]
+##set_property PACKAGE_PIN T4 [get_ports DDR3_CAS_B]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_CAS_B]
+##set_property PACKAGE_PIN T3 [get_ports DDR3_S0_B]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_S0_B]
+##set_property PACKAGE_PIN T2 [get_ports DDR3_S1_B]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_S1_B]
+##set_property PACKAGE_PIN R2 [get_ports DDR3_ODT0]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_ODT0]
+##set_property PACKAGE_PIN U2 [get_ports DDR3_ODT1]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_ODT1]
+##set_property PACKAGE_PIN U1 [get_ports DDR3_TEMP_EVENT]
+##set_property IOSTANDARD LVCMOS15 [get_ports DDR3_TEMP_EVENT]
+##set_property PACKAGE_PIN P6 [get_ports GPIO_SW_N]
+##set_property IOSTANDARD LVCMOS15 [get_ports GPIO_SW_N]
+##set_property PACKAGE_PIN P5 [get_ports VTTVREF]
+##set_property IOSTANDARD SSTL15 [get_ports VTTVREF]
+##set_property PACKAGE_PIN T5 [get_ports GPIO_SW_S]
+##set_property IOSTANDARD SSTL15 [get_ports GPIO_SW_S]
+##set_property PACKAGE_PIN R5 [get_ports GPIO_SW_W]
+##set_property IOSTANDARD SSTL15 [get_ports GPIO_SW_W]
+##set_property PACKAGE_PIN U6 [get_ports GPIO_SW_C]
+##set_property IOSTANDARD SSTL15 [get_ports GPIO_SW_C]
+##set_property PACKAGE_PIN U5 [get_ports GPIO_SW_E]
+##set_property IOSTANDARD SSTL15 [get_ports GPIO_SW_E]
+##set_property PACKAGE_PIN R8 [get_ports GPIO_DIP_SW0]
+##set_property IOSTANDARD SSTL15 [get_ports GPIO_DIP_SW0]
+##set_property PACKAGE_PIN P8 [get_ports GPIO_DIP_SW1]
+##set_property IOSTANDARD SSTL15 [get_ports GPIO_DIP_SW1]
+##set_property PACKAGE_PIN R7 [get_ports GPIO_DIP_SW2]
+##set_property IOSTANDARD SSTL15 [get_ports GPIO_DIP_SW2]
+##set_property PACKAGE_PIN R6 [get_ports GPIO_DIP_SW3]
+##set_property IOSTANDARD SSTL15 [get_ports GPIO_DIP_SW3]
+##set_property PACKAGE_PIN T8 [get_ports USER_SMA_GPIO_P]
+##set_property IOSTANDARD LVDS_25 [get_ports USER_SMA_GPIO_P]
+##set_property PACKAGE_PIN T7 [get_ports USER_SMA_GPIO_N]
+##set_property IOSTANDARD LVDS_25 [get_ports USER_SMA_GPIO_N]
+##set_property PACKAGE_PIN U4 [get_ports CPU_RESET]
+##set_property IOSTANDARD LVCMOS15 [get_ports CPU_RESET]
+##set_property PACKAGE_PIN J8 [get_ports No]
+##set_property IOSTANDARD SSTL15 [get_ports No]
+##set_property PACKAGE_PIN E6 [get_ports DDR3_D63]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D63]
+##set_property PACKAGE_PIN D6 [get_ports DDR3_D62]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D62]
+##set_property PACKAGE_PIN H8 [get_ports DDR3_D61]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D61]
+##set_property PACKAGE_PIN G8 [get_ports DDR3_D60]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D60]
+##set_property PACKAGE_PIN H7 [get_ports DDR3_DQS7_P]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS7_P]
+##set_property PACKAGE_PIN G7 [get_ports DDR3_DQS7_N]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS7_N]
+##set_property PACKAGE_PIN F8 [get_ports DDR3_D59]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D59]
+##set_property PACKAGE_PIN F7 [get_ports DDR3_D58]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D58]
+##set_property PACKAGE_PIN H6 [get_ports DDR3_D57]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D57]
+##set_property PACKAGE_PIN G6 [get_ports DDR3_D56]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D56]
+##set_property PACKAGE_PIN H9 [get_ports DDR3_DM7]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_DM7]
+##set_property PACKAGE_PIN G9 [get_ports VTTVREF]
+##set_property IOSTANDARD SSTL15 [get_ports VTTVREF]
+##set_property PACKAGE_PIN J6 [get_ports DDR3_D55]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D55]
+##set_property PACKAGE_PIN J5 [get_ports DDR3_D54]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D54]
+##set_property PACKAGE_PIN L8 [get_ports DDR3_D53]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D53]
+##set_property PACKAGE_PIN K8 [get_ports DDR3_D52]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D52]
+##set_property PACKAGE_PIN J4 [get_ports DDR3_DQS6_P]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS6_P]
+##set_property PACKAGE_PIN H4 [get_ports DDR3_DQS6_N]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS6_N]
+##set_property PACKAGE_PIN K7 [get_ports DDR3_D51]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D51]
+##set_property PACKAGE_PIN K6 [get_ports DDR3_D50]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D50]
+##set_property PACKAGE_PIN G4 [get_ports DDR3_D49]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D49]
+##set_property PACKAGE_PIN F4 [get_ports DDR3_D48]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D48]
+##set_property PACKAGE_PIN G5 [get_ports DDR3_DM6]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_DM6]
+##set_property PACKAGE_PIN F5 [get_ports No]
+##set_property IOSTANDARD SSTL15 [get_ports No]
+##set_property PACKAGE_PIN E5 [get_ports DDR3_D47]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D47]
+##set_property PACKAGE_PIN D5 [get_ports DDR3_D46]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D46]
+##set_property PACKAGE_PIN D4 [get_ports DDR3_D45]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D45]
+##set_property PACKAGE_PIN C4 [get_ports DDR3_D44]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D44]
+##set_property PACKAGE_PIN B5 [get_ports DDR3_DQS5_P]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS5_P]
+##set_property PACKAGE_PIN A5 [get_ports DDR3_DQS5_N]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS5_N]
+##set_property PACKAGE_PIN B4 [get_ports DDR3_D43]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D43]
+##set_property PACKAGE_PIN A4 [get_ports DDR3_D42]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D42]
+##set_property PACKAGE_PIN D3 [get_ports DDR3_D41]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D41]
+##set_property PACKAGE_PIN C3 [get_ports DDR3_D40]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D40]
+##set_property PACKAGE_PIN F3 [get_ports DDR3_DM5]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_DM5]
+##set_property PACKAGE_PIN E3 [get_ports No]
+##set_property IOSTANDARD SSTL15 [get_ports No]
+##set_property PACKAGE_PIN C2 [get_ports DDR3_D39]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D39]
+##set_property PACKAGE_PIN B2 [get_ports VTTVREF]
+##set_property IOSTANDARD SSTL15 [get_ports VTTVREF]
+##set_property PACKAGE_PIN A3 [get_ports DDR3_D38]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D38]
+##set_property PACKAGE_PIN A2 [get_ports DDR3_D37]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D37]
+##set_property PACKAGE_PIN C1 [get_ports DDR3_DQS4_P]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS4_P]
+##set_property PACKAGE_PIN B1 [get_ports DDR3_DQS4_N]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS4_N]
+##set_property PACKAGE_PIN F2 [get_ports DDR3_D36]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D36]
+##set_property PACKAGE_PIN E2 [get_ports DDR3_D35]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D35]
+##set_property PACKAGE_PIN E1 [get_ports DDR3_D34]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D34]
+##set_property PACKAGE_PIN D1 [get_ports DDR3_D33]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D33]
+##set_property PACKAGE_PIN G2 [get_ports DDR3_D32]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D32]
+##set_property PACKAGE_PIN G1 [get_ports DDR3_DM4]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_DM4]
+##set_property PACKAGE_PIN H3 [get_ports No]
+##set_property IOSTANDARD SSTL15 [get_ports No]
+##set_property PACKAGE_PIN AB13 [get_ports SFP_MGT_CLK0_N]
+##set_property IOSTANDARD LVDS_25 [get_ports SFP_MGT_CLK0_N]
+##set_property PACKAGE_PIN AA13 [get_ports SFP_MGT_CLK0_P]
+##set_property IOSTANDARD LVDS_25 [get_ports SFP_MGT_CLK0_P]
+##set_property PACKAGE_PIN AF15 [get_ports MGTRREF_213]
+##set_property IOSTANDARD LVDS_25 [get_ports MGTRREF_213]
+##set_property PACKAGE_PIN AA11 [get_ports SFP_MGT_CLK1_P]
+##set_property IOSTANDARD LVDS_25 [get_ports SFP_MGT_CLK1_P]
+##set_property PACKAGE_PIN AB11 [get_ports SFP_MGT_CLK1_N]
+##set_property IOSTANDARD LVDS_25 [get_ports SFP_MGT_CLK1_N]
+##set_property PACKAGE_PIN E11 [get_ports PCIE_CLK_QO_N]
+##set_property IOSTANDARD LVDS_25 [get_ports PCIE_CLK_QO_N]
+##set_property PACKAGE_PIN F11 [get_ports PCIE_CLK_QO_P]
+##set_property IOSTANDARD LVDS_25 [get_ports PCIE_CLK_QO_P]
+##set_property PACKAGE_PIN A15 [get_ports MGTRREF_216]
+##set_property IOSTANDARD LVDS_25 [get_ports MGTRREF_216]
+##set_property PACKAGE_PIN F13 [get_ports No]
+##set_property IOSTANDARD LVDS_25 [get_ports No]
+##set_property PACKAGE_PIN E13 [get_ports No]
+##set_property IOSTANDARD LVDS_25 [get_ports No]
+
+
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[0]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[1]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[2]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[3]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[4]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[5]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[6]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[7]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[8]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[9]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[10]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[11]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[12]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[13]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[14]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[15]} ]
+
+set_property PULLUP true [get_ports {P0[0]} ]
+set_property PULLUP true [get_ports {P0[1]} ]
+set_property PULLUP true [get_ports {P0[2]} ]
+set_property PULLUP true [get_ports {P0[3]} ]
+set_property PULLUP true [get_ports {P0[4]} ]
+set_property PULLUP true [get_ports {P0[5]} ]
+set_property PULLUP true [get_ports {P0[6]} ]
+set_property PULLUP true [get_ports {P0[7]} ]
+set_property PULLUP true [get_ports {P0[8]} ]
+set_property PULLUP true [get_ports {P0[9]} ]
+set_property PULLUP true [get_ports {P0[10]} ]
+set_property PULLUP true [get_ports {P0[11]} ]
+set_property PULLUP true [get_ports {P0[12]} ]
+set_property PULLUP true [get_ports {P0[13]} ]
+set_property PULLUP true [get_ports {P0[14]} ]
+set_property PULLUP true [get_ports {P0[15]} ]
+
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[0]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[1]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[2]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[3]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[4]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[5]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[6]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[7]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[8]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[9]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[10]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[11]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[12]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[13]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[14]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[15]} ]
+
+set_property PULLUP true [get_ports {P1[0]} ]
+set_property PULLUP true [get_ports {P1[1]} ]
+set_property PULLUP true [get_ports {P1[2]} ]
+set_property PULLUP true [get_ports {P1[3]} ]
+set_property PULLUP true [get_ports {P1[4]} ]
+set_property PULLUP true [get_ports {P1[5]} ]
+set_property PULLUP true [get_ports {P1[6]} ]
+set_property PULLUP true [get_ports {P1[7]} ]
+set_property PULLUP true [get_ports {P1[8]} ]
+set_property PULLUP true [get_ports {P1[9]} ]
+set_property PULLUP true [get_ports {P1[10]} ]
+set_property PULLUP true [get_ports {P1[11]} ]
+set_property PULLUP true [get_ports {P1[12]} ]
+set_property PULLUP true [get_ports {P1[13]} ]
+set_property PULLUP true [get_ports {P1[14]} ]
+set_property PULLUP true [get_ports {P1[15]} ]
+
+set_property PULLDOWN true [get_ports {SWDIOTMS} ]
+set_property PULLDOWN true [get_ports {SWCLKTCK} ]
+
+#PMODA pin0 to FTCLK
+set_property PACKAGE_PIN T22 [get_ports {P1[1]}]
+
+#PMODA pin1 to FTSSN
+set_property PACKAGE_PIN T23 [get_ports {P1[3]}]
+
+#PMODA pin2 to FTMISO
+set_property PACKAGE_PIN P26 [get_ports {P1[0]}]
+
+#PMODA pin3 to FTMIOSIO
+set_property PACKAGE_PIN R22 [get_ports {P1[2]}]
+
+#PMODB pin1 to SWDIOTMS
+##set_property PACKAGE_PIN G6 [get_ports SWDIOTMS]
+
+#PMODB pin4 to SWCLKTCK
+##set_property PACKAGE_PIN H7 [get_ports SWCLKTCK]
+##set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets uPAD_SWDCLK_I/IOBUF3V3/O]
+
+#PMODA pin4 : UART2RXD
+#PMODA pin4 : UART2TXD
+
+
+# LED0 to P0[0]
+set_property PACKAGE_PIN M26 [get_ports {P0[0]}]
+# LED1 to P0[1]
+set_property PACKAGE_PIN T24 [get_ports {P0[1]}]
+# LED2 to P0[2]
+set_property PACKAGE_PIN T25 [get_ports {P0[2]}]
+# LED3 to P0[3]
+set_property PACKAGE_PIN R26 [get_ports {P0[3]}]
+
+# SW0 to NRST (Down for active low)
+set_property PACKAGE_PIN R8 [get_ports NRST]
+
+# USR CLOCK P (need dvider)
+##set_property IOSTANDARD LVCMOS18 [get_ports XTAL1 ]
+#set_property PACKAGE_PIN M21 [get_ports XTAL1]
+#set_property PACKAGE_PIN R17 [get_ports XTAL2]
+
+#Board ref clock - 200MHz (need dvider)
+#set_property PACKAGE_PIN R3 [get_ports XTAL1]
+#set_property PACKAGE_PIN P3 [get_ports XTAL2]
+#Board user clock - 200MHz (need dvider)
+set_property PACKAGE_PIN M21 [get_ports XTAL1]
+set_property PACKAGE_PIN M22 [get_ports XTAL2]
+
+
+## auto mapped - to remap
+set_property PACKAGE_PIN R20 [get_ports {P0[10]}]
+set_property PACKAGE_PIN P24 [get_ports {P0[11]}]
+set_property PACKAGE_PIN P23 [get_ports {P0[12]}]
+set_property PACKAGE_PIN N19 [get_ports {P0[13]}]
+set_property PACKAGE_PIN P19 [get_ports {P0[14]}]
+set_property PACKAGE_PIN N24 [get_ports {P0[15]}]
+set_property PACKAGE_PIN R18 [get_ports {P0[4]}]
+set_property PACKAGE_PIN R23 [get_ports {P0[5]}]
+set_property PACKAGE_PIN N26 [get_ports {P0[6]}]
+set_property PACKAGE_PIN P25 [get_ports {P0[7]}]
+set_property PACKAGE_PIN R25 [get_ports {P0[8]}]
+set_property PACKAGE_PIN R21 [get_ports {P0[9]}]
+set_property PACKAGE_PIN M25 [get_ports {P1[10]}]
+set_property PACKAGE_PIN M24 [get_ports {P1[11]}]
+set_property PACKAGE_PIN L25 [get_ports {P1[12]}]
+set_property PACKAGE_PIN L24 [get_ports {P1[13]}]
+set_property PACKAGE_PIN L20 [get_ports {P1[14]}]
+set_property PACKAGE_PIN M20 [get_ports {P1[15]}]
+set_property PACKAGE_PIN N23 [get_ports {P1[4]}]
+set_property PACKAGE_PIN P21 [get_ports {P1[5]}]
+set_property PACKAGE_PIN P20 [get_ports {P1[6]}]
+set_property PACKAGE_PIN N22 [get_ports {P1[7]}]
+set_property PACKAGE_PIN N21 [get_ports {P1[8]}]
+set_property PACKAGE_PIN L23 [get_ports {P1[9]}]
+set_property PACKAGE_PIN L22 [get_ports SWCLKTCK]
+set_property PACKAGE_PIN K26 [get_ports SWDIOTMS]
+set_property PACKAGE_PIN K25 [get_ports VDD]
+set_property PACKAGE_PIN N18 [get_ports VDDIO]
+set_property PACKAGE_PIN P18 [get_ports VSS]
+set_property PACKAGE_PIN R17 [get_ports VSSIO]
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_ac701/fpga_synth.tcl b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_ac701/fpga_synth.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..a13e2b6e4b167fed62c60f4aa382e932b1b9593a
--- /dev/null
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_ac701/fpga_synth.tcl
@@ -0,0 +1,40 @@
+
+synth_design -top cmsdk_mcu_chip -part xc7a200tfbg676-2
+
+write_verilog -force $outputDir/cmsdk_mcu_synth_netlist.v
+
+# # Create interface ports
+# 
+# disconnect_net -net XTAL1 -objects {uPAD_XTAL_I/XTAL1}
+# disconnect_net -net XTAL2 -objects {uPAD_XTAL_O/XTAL2}
+# #disconnect_net -net xtal_clk_in] [get_pins XTAL1 uPAD_XTAL1_PAD/IOBUF3V3/I]]
+
+# set sys_diff_clock [ create_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_diff_clock ]
+# set_property -dict [ list \
+#  CONFIG.FREQ_HZ {200000000} \
+#  ] $sys_diff_clock
+
+#  set reset [ create_bd_port -dir I -type rst reset ]
+#  set_property -dict [ list \
+#   CONFIG.POLARITY {ACTIVE_HIGH} \
+# ] $reset
+
+# # Create instance: clk_wiz_20M, and set properties
+# set clk_wiz_20M [ create_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_20M ]
+# set_property -dict [ list \
+#  CONFIG.CLKOUT1_JITTER {155.788} \
+#  CONFIG.CLKOUT1_PHASE_ERROR {94.329} \
+#  CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {20.000} \
+#  CONFIG.CLK_IN1_BOARD_INTERFACE {sys_diff_clock} \
+#  CONFIG.MMCM_CLKFBOUT_MULT_F {4.250} \
+#  CONFIG.MMCM_CLKOUT0_DIVIDE_F {42.500} \
+#  CONFIG.RESET_BOARD_INTERFACE {reset} \
+#  CONFIG.USE_BOARD_FLOW {false} \
+#] $clk_wiz_20M
+
+# # Create interface connections
+# connect_net -intf_net sys_diff_clock_1 [get_ports sys_diff_clock] [get_pins clk_wiz_20M/CLK_IN1_D]
+
+# # Create port connections
+# connect_net -net clk_wiz_0_clk_out1 [get_pins xtal_clk_in] [get_bd_pins clk_wiz_20M/clk_out1]
+# connect_net -net reset_1 [get_bd_ports reset] [get_bd_pins clk_wiz_20M/reset]
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_ac701/fpga_timing.xdc b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_ac701/fpga_timing.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..cb4cef44a99ecc3e62b7c6d18c03ca623885f6a8
--- /dev/null
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_ac701/fpga_timing.xdc
@@ -0,0 +1,95 @@
+##################################################################################
+##                                                                              ##
+## ZYNQ timing XDC                                                              ##
+##                                                                              ##
+##################################################################################
+
+create_clock -name CLK -period 30 [get_ports XTAL1]
+create_clock -name VCLK -period 30 -waveform {5 20}
+
+create_clock -name SWCLK -period 60 [get_ports SWCLKTCK]
+create_clock -name VSWCLK -period 60 -waveform {5 35}
+
+set_clock_groups -name async_clk_swclock -asynchronous \
+-group [get_clocks -include_generated_clocks CLK] \
+-group [get_clocks -include_generated_clocks VSWCLK]
+
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports {dip_switch_4bits_tri_i[*]}]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports {dip_switch_4bits_tri_i[*]}]
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_2]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports PMOD0_2]
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_3]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports PMOD0_3]
+#set_output_delay -clock [get_clocks clk_pl_0] -min -add_delay 5.000 [get_ports {led_4bits_tri_o[*]}]
+#set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {led_4bits_tri_o[*]}]
+
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P0[0]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[0]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P0[1]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[1]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P0[2]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[2]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P0[3]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[3]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P0[4]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[4]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P0[5]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[5]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P0[6]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[6]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P0[7]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[7]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P0[8]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[8]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P0[9]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[9]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P0[10]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[10]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P0[11]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[11]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P0[12]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[12]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P0[13]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[13]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P0[14]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[14]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P0[15]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[15]}]
+
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P1[0]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[0]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P1[1]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[1]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P1[2]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[2]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P1[3]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[3]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P1[4]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[4]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P1[5]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[5]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P1[6]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[6]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P1[7]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[7]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P1[8]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[8]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P1[9]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[9]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P1[10]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[10]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P1[11]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[11]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P1[12]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[12]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P1[13]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[13]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P1[14]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[14]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P1[15]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[15]}]
+
+set_property C_CLK_INPUT_FREQ_HZ 5000000 [get_debug_cores dbg_hub]
+set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+connect_debug_port dbg_hub/clk [get_nets clk]
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_arm_mps3/fpga_pinmap.xdc b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_arm_mps3/fpga_pinmap.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..5fbe61eb28f3d716824d54418909d555a4f29ad4
--- /dev/null
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_arm_mps3/fpga_pinmap.xdc
@@ -0,0 +1,915 @@
+# -----------------------------------------------------------------------------
+# Purpose : Main timing constraints and pin list for MPS3
+# -----------------------------------------------------------------------------
+
+####################################################################################
+# Pin Assigment
+####################################################################################
+
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_* ETH_* USB_* CLCD_* USER_nLED* USER_SW* USER_nPB* HDMI_* CS_* SH_ADC* UART_*}]
+
+set_property IOSTANDARD LVCMOS18 [get_ports {OSCCLK[5]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {OSCCLK[4]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {OSCCLK[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {OSCCLK[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {OSCCLK[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {OSCCLK[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[23]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[22]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[21]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[20]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[19]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[18]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[17]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[16]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[15]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[14]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[13]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[12]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[11]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[10]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[9]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[8]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[7]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[6]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[5]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[4]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_SD[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_SD[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_SD[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_SD[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports MMB_DE]
+set_property IOSTANDARD LVCMOS18 [get_ports MMB_HS]
+set_property IOSTANDARD LVCMOS18 [get_ports MMB_IDCLK]
+set_property IOSTANDARD LVCMOS18 [get_ports MMB_SCK]
+set_property IOSTANDARD LVCMOS18 [get_ports MMB_VS]
+set_property IOSTANDARD LVCMOS18 [get_ports MMB_WS]
+set_property IOSTANDARD LVCMOS18 [get_ports {EMMC_DAT[7]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {EMMC_DAT[6]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {EMMC_DAT[5]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {EMMC_DAT[4]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {EMMC_DAT[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {EMMC_DAT[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {EMMC_DAT[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {EMMC_DAT[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports EMMC_CLK]
+set_property IOSTANDARD LVCMOS18 [get_ports EMMC_CMD]
+set_property IOSTANDARD LVCMOS18 [get_ports EMMC_DS]
+set_property IOSTANDARD LVCMOS18 [get_ports EMMC_nRST]
+# not used
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports {CLK_BIDIR_P[3]}]
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports {CLK_BIDIR_N[3]}]
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports {CLK_BIDIR_P[2]}]
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports {CLK_BIDIR_N[2]}]
+
+set_property IOSTANDARD LVCMOS18 [get_ports AUD_LRCK]
+set_property PACKAGE_PIN Y30 [get_ports AUD_LRCK]
+set_property IOSTANDARD LVCMOS18 [get_ports AUD_MCLK]
+set_property PACKAGE_PIN AB29 [get_ports AUD_MCLK]
+set_property IOSTANDARD LVCMOS18 [get_ports AUD_nRST]
+set_property PACKAGE_PIN AA27 [get_ports AUD_nRST]
+set_property IOSTANDARD LVCMOS18 [get_ports AUD_SCL]
+set_property PACKAGE_PIN AA28 [get_ports AUD_SCL]
+set_property IOSTANDARD LVCMOS18 [get_ports AUD_SCLK]
+set_property PACKAGE_PIN AB30 [get_ports AUD_SCLK]
+set_property IOSTANDARD LVCMOS18 [get_ports AUD_SDA]
+set_property PACKAGE_PIN AA29 [get_ports AUD_SDA]
+set_property IOSTANDARD LVCMOS18 [get_ports AUD_SDIN]
+set_property PACKAGE_PIN AA30 [get_ports AUD_SDIN]
+set_property IOSTANDARD LVCMOS18 [get_ports AUD_SDOUT]
+set_property PACKAGE_PIN Y27 [get_ports AUD_SDOUT]
+set_property IOSTANDARD LVCMOS33 [get_ports CB_nPOR]
+set_property PACKAGE_PIN AU22 [get_ports CB_nPOR]
+set_property IOSTANDARD LVCMOS33 [get_ports CB_nRST]
+set_property PACKAGE_PIN AV23 [get_ports CB_nRST]
+set_property IOSTANDARD LVCMOS33 [get_ports CB_RUN]
+set_property PACKAGE_PIN AR25 [get_ports CB_RUN]
+set_property IOSTANDARD LVCMOS33 [get_ports CFG_CLK]
+set_property PACKAGE_PIN AT20 [get_ports CFG_CLK]
+set_property IOSTANDARD LVCMOS33 [get_ports CFG_DATAIN]
+set_property PACKAGE_PIN AT19 [get_ports CFG_DATAIN]
+set_property IOSTANDARD LVCMOS33 [get_ports CFG_DATAOUT]
+set_property PACKAGE_PIN AV18 [get_ports CFG_DATAOUT]
+set_property IOSTANDARD LVCMOS33 [get_ports CFG_LOAD]
+set_property PACKAGE_PIN AW18 [get_ports CFG_LOAD]
+set_property IOSTANDARD LVCMOS33 [get_ports CFG_nRST]
+set_property PACKAGE_PIN AR20 [get_ports CFG_nRST]
+set_property IOSTANDARD LVCMOS33 [get_ports CFG_WnR]
+set_property PACKAGE_PIN AT18 [get_ports CFG_WnR]
+set_property PACKAGE_PIN AJ16 [get_ports CLCD_BL]
+set_property PACKAGE_PIN AP15 [get_ports CLCD_CS]
+set_property PACKAGE_PIN AN17 [get_ports {CLCD_PD[10]}]
+set_property PACKAGE_PIN AP16 [get_ports {CLCD_PD[11]}]
+set_property PACKAGE_PIN AP18 [get_ports {CLCD_PD[12]}]
+set_property PACKAGE_PIN AR18 [get_ports {CLCD_PD[13]}]
+set_property PACKAGE_PIN AM16 [get_ports {CLCD_PD[14]}]
+set_property PACKAGE_PIN AN16 [get_ports {CLCD_PD[15]}]
+set_property PACKAGE_PIN AR17 [get_ports {CLCD_PD[16]}]
+set_property PACKAGE_PIN AR16 [get_ports {CLCD_PD[17]}]
+set_property PACKAGE_PIN AM15 [get_ports CLCD_RD]
+set_property PACKAGE_PIN AN14 [get_ports CLCD_RS]
+set_property PACKAGE_PIN AK18 [get_ports CLCD_RST]
+#set_property PACKAGE_PIN AN18 [get_ports CLCD_SDI]
+#set_property PACKAGE_PIN AH16 [get_ports CLCD_SDO]
+set_property PACKAGE_PIN AJ14 [get_ports CLCD_TINT]
+set_property PACKAGE_PIN AL17 [get_ports CLCD_TNC]
+set_property PACKAGE_PIN AL18 [get_ports CLCD_TSCL]
+set_property PACKAGE_PIN AJ15 [get_ports CLCD_TSDA]
+set_property PACKAGE_PIN AP14 [get_ports CLCD_WR_SCL]
+# not used
+# set_property PACKAGE_PIN N28 [get_ports {CLK_BIDIR_P[2]}]
+# set_property PACKAGE_PIN N29 [get_ports {CLK_BIDIR_N[2]}]
+# set_property PACKAGE_PIN E32 [get_ports {CLK_BIDIR_P[3]}]
+# set_property PACKAGE_PIN D33 [get_ports {CLK_BIDIR_N[3]}]
+# set_property PACKAGE_PIN G31 [get_ports {CLK_M2C_P[0]}]
+# set_property PACKAGE_PIN F32 [get_ports {CLK_M2C_N[0]}]
+# set_property PACKAGE_PIN E31 [get_ports {CLK_M2C_P[1]}]
+# set_property PACKAGE_PIN D31 [get_ports {CLK_M2C_N[1]}]
+set_property PACKAGE_PIN BB39 [get_ports CS_nDET]
+set_property PACKAGE_PIN BB36 [get_ports CS_nSRST]
+set_property PACKAGE_PIN BB37 [get_ports CS_nTRST]
+set_property PACKAGE_PIN AW33 [get_ports CS_T_CLK]
+set_property PACKAGE_PIN AY35 [get_ports CS_T_CTL]
+set_property PACKAGE_PIN AW34 [get_ports {CS_T_D[0]}]
+set_property PACKAGE_PIN AT34 [get_ports {CS_T_D[1]}]
+set_property PACKAGE_PIN AU34 [get_ports {CS_T_D[2]}]
+set_property PACKAGE_PIN AV36 [get_ports {CS_T_D[3]}]
+set_property PACKAGE_PIN AW36 [get_ports {CS_T_D[4]}]
+set_property PACKAGE_PIN AT35 [get_ports {CS_T_D[5]}]
+set_property PACKAGE_PIN AU35 [get_ports {CS_T_D[6]}]
+set_property PACKAGE_PIN AU36 [get_ports {CS_T_D[7]}]
+set_property PACKAGE_PIN AV37 [get_ports {CS_T_D[8]}]
+set_property PACKAGE_PIN AW35 [get_ports {CS_T_D[9]}]
+set_property PACKAGE_PIN AY36 [get_ports {CS_T_D[10]}]
+set_property PACKAGE_PIN AY37 [get_ports {CS_T_D[11]}]
+set_property PACKAGE_PIN BB34 [get_ports {CS_T_D[12]}]
+set_property PACKAGE_PIN BB35 [get_ports {CS_T_D[13]}]
+set_property PACKAGE_PIN BA37 [get_ports {CS_T_D[14]}]
+set_property PACKAGE_PIN BA38 [get_ports {CS_T_D[15]}]
+set_property PACKAGE_PIN AV33 [get_ports CS_TCK]
+set_property PACKAGE_PIN BA35 [get_ports CS_TDI]
+set_property PACKAGE_PIN AW38 [get_ports CS_TDO]
+set_property PACKAGE_PIN AY38 [get_ports CS_TMS]
+# not used
+#set_property IOSTANDARD POD12_DCI [get_ports {DDR_CHIPID[0]}]
+#set_property PACKAGE_PIN J19 [get_ports {DDR_CHIPID[0]}]
+#set_property IOSTANDARD POD12_DCI [get_ports {DDR_CHIPID[1]}]
+#set_property PACKAGE_PIN G20 [get_ports {DDR_CHIPID[1]}]
+#set_property IOSTANDARD POD12_DCI [get_ports DDR_nALERT]
+#set_property PACKAGE_PIN P15 [get_ports DDR_nALERT]
+#set_property IOSTANDARD POD12_DCI [get_ports DDR_nEVENT]
+#set_property PACKAGE_PIN C17 [get_ports DDR_nEVENT]
+# set_property IOSTANDARD POD12_DCI [get_ports DDR_PARITY]
+# set_property PACKAGE_PIN D18 [get_ports DDR_PARITY]
+# set_property IOSTANDARD POD12_DCI [get_ports DDR_SCL]
+# set_property PACKAGE_PIN N21 [get_ports DDR_SCL]
+# set_property IOSTANDARD POD12_DCI [get_ports DDR_SDA]
+# set_property PACKAGE_PIN P21 [get_ports DDR_SDA]
+# set_property PACKAGE_PIN AC42 [get_ports {DP_M2C_N[0]}]
+# set_property PACKAGE_PIN AJ42 [get_ports {DP_M2C_N[1]}]
+# set_property PACKAGE_PIN AE42 [get_ports {DP_M2C_N[2]}]
+# set_property PACKAGE_PIN W42 [get_ports {DP_M2C_N[3]}]
+# set_property PACKAGE_PIN R42 [get_ports {DP_M2C_N[4]}]
+# set_property PACKAGE_PIN L42 [get_ports {DP_M2C_N[5]}]
+# set_property PACKAGE_PIN N42 [get_ports {DP_M2C_N[6]}]
+# set_property PACKAGE_PIN U42 [get_ports {DP_M2C_N[7]}]
+# set_property PACKAGE_PIN AA42 [get_ports {DP_M2C_N[8]}]
+# set_property PACKAGE_PIN AG42 [get_ports {DP_M2C_N[9]}]
+# set_property PACKAGE_PIN AC41 [get_ports {DP_M2C_P[0]}]
+# set_property PACKAGE_PIN AJ41 [get_ports {DP_M2C_P[1]}]
+# set_property PACKAGE_PIN AE41 [get_ports {DP_M2C_P[2]}]
+# set_property PACKAGE_PIN W41 [get_ports {DP_M2C_P[3]}]
+# set_property PACKAGE_PIN R41 [get_ports {DP_M2C_P[4]}]
+# set_property PACKAGE_PIN L41 [get_ports {DP_M2C_P[5]}]
+# set_property PACKAGE_PIN N41 [get_ports {DP_M2C_P[6]}]
+# set_property PACKAGE_PIN U41 [get_ports {DP_M2C_P[7]}]
+# set_property PACKAGE_PIN AA41 [get_ports {DP_M2C_P[8]}]
+# set_property PACKAGE_PIN AG41 [get_ports {DP_M2C_P[9]}]
+set_property PACKAGE_PIN AG34 [get_ports HDMI_CSCL]
+set_property PACKAGE_PIN AE33 [get_ports HDMI_CSDA]
+set_property PACKAGE_PIN AF33 [get_ports HDMI_INT]
+set_property PACKAGE_PIN W29 [get_ports EMMC_CLK]
+set_property PACKAGE_PIN AC34 [get_ports EMMC_CMD]
+set_property PACKAGE_PIN Y32 [get_ports {EMMC_DAT[0]}]
+set_property PACKAGE_PIN Y33 [get_ports {EMMC_DAT[1]}]
+set_property PACKAGE_PIN W33 [get_ports {EMMC_DAT[2]}]
+set_property PACKAGE_PIN W34 [get_ports {EMMC_DAT[3]}]
+set_property PACKAGE_PIN AA34 [get_ports {EMMC_DAT[4]}]
+set_property PACKAGE_PIN AB34 [get_ports {EMMC_DAT[5]}]
+set_property PACKAGE_PIN W31 [get_ports {EMMC_DAT[6]}]
+set_property PACKAGE_PIN Y31 [get_ports {EMMC_DAT[7]}]
+set_property PACKAGE_PIN AE32 [get_ports EMMC_DS]
+set_property PACKAGE_PIN W30 [get_ports EMMC_nRST]
+set_property PACKAGE_PIN AK23 [get_ports ETH_INT]
+set_property PACKAGE_PIN AL24 [get_ports ETH_nCS]
+set_property PACKAGE_PIN AJ23 [get_ports ETH_nOE]
+# not used
+# set_property PACKAGE_PIN AV38 [get_ports FMC_CLK_DIR]
+# set_property PACKAGE_PIN AL42 [get_ports FMC_nPRSNT]
+# set_property PACKAGE_PIN BB40 [get_ports {HA_N[2]}]
+# set_property PACKAGE_PIN BA41 [get_ports {HA_N[3]}]
+# set_property PACKAGE_PIN AY40 [get_ports {HA_N[4]}]
+# set_property PACKAGE_PIN AU42 [get_ports {HA_N[5]}]
+# set_property PACKAGE_PIN AY42 [get_ports {HA_N[6]}]
+# set_property PACKAGE_PIN AW41 [get_ports {HA_N[7]}]
+# set_property PACKAGE_PIN AU37 [get_ports {HA_N[8]}]
+# set_property PACKAGE_PIN AT42 [get_ports {HA_N[9]}]
+# set_property PACKAGE_PIN AT38 [get_ports {HA_N[10]}]
+# set_property PACKAGE_PIN AV42 [get_ports {HA_N[11]}]
+# set_property PACKAGE_PIN AR37 [get_ports {HA_N[12]}]
+# set_property PACKAGE_PIN AN42 [get_ports {HA_N[13]}]
+# set_property PACKAGE_PIN AP38 [get_ports {HA_N[14]}]
+# set_property PACKAGE_PIN AN37 [get_ports {HA_N[15]}]
+# set_property PACKAGE_PIN AM42 [get_ports {HA_N[16]}]
+# set_property PACKAGE_PIN AR41 [get_ports {HA_N[18]}]
+# set_property PACKAGE_PIN AM39 [get_ports {HA_N[19]}]
+# set_property PACKAGE_PIN AR40 [get_ports {HA_N[20]}]
+# set_property PACKAGE_PIN AM40 [get_ports {HA_N[21]}]
+# set_property PACKAGE_PIN AK38 [get_ports {HA_N[22]}]
+# set_property PACKAGE_PIN AL38 [get_ports {HA_N[23]}]
+# set_property PACKAGE_PIN AT39 [get_ports {HA_P[0]}]
+# set_property PACKAGE_PIN AT40 [get_ports {HA_N[0]}]
+# set_property PACKAGE_PIN AU39 [get_ports {HA_P[1]}]
+# set_property PACKAGE_PIN AU40 [get_ports {HA_N[1]}]
+# set_property PACKAGE_PIN BA39 [get_ports {HA_P[2]}]
+# set_property PACKAGE_PIN BA40 [get_ports {HA_P[3]}]
+# set_property PACKAGE_PIN AW39 [get_ports {HA_P[4]}]
+# set_property PACKAGE_PIN AU41 [get_ports {HA_P[5]}]
+# set_property PACKAGE_PIN AY41 [get_ports {HA_P[6]}]
+# set_property PACKAGE_PIN AW40 [get_ports {HA_P[7]}]
+# set_property PACKAGE_PIN AT37 [get_ports {HA_P[8]}]
+# set_property PACKAGE_PIN AR42 [get_ports {HA_P[9]}]
+# set_property PACKAGE_PIN AR38 [get_ports {HA_P[10]}]
+# set_property PACKAGE_PIN AV41 [get_ports {HA_P[11]}]
+# set_property PACKAGE_PIN AR36 [get_ports {HA_P[12]}]
+# set_property PACKAGE_PIN AN41 [get_ports {HA_P[13]}]
+# set_property PACKAGE_PIN AN38 [get_ports {HA_P[14]}]
+# set_property PACKAGE_PIN AM37 [get_ports {HA_P[15]}]
+# set_property PACKAGE_PIN AM41 [get_ports {HA_P[16]}]
+# set_property PACKAGE_PIN AN39 [get_ports {HA_P[17]}]
+# set_property PACKAGE_PIN AP39 [get_ports {HA_N[17]}]
+# set_property PACKAGE_PIN AP41 [get_ports {HA_P[18]}]
+# set_property PACKAGE_PIN AL39 [get_ports {HA_P[19]}]
+# set_property PACKAGE_PIN AP40 [get_ports {HA_P[20]}]
+# set_property PACKAGE_PIN AL40 [get_ports {HA_P[21]}]
+# set_property PACKAGE_PIN AK37 [get_ports {HA_P[22]}]
+# set_property PACKAGE_PIN AL37 [get_ports {HA_P[23]}]
+# set_property PACKAGE_PIN T32 [get_ports {HB_N[1]}]
+# set_property PACKAGE_PIN V33 [get_ports {HB_N[2]}]
+# set_property PACKAGE_PIN V29 [get_ports {HB_N[3]}]
+# set_property PACKAGE_PIN T30 [get_ports {HB_N[4]}]
+# set_property PACKAGE_PIN T34 [get_ports {HB_N[5]}]
+# set_property PACKAGE_PIN R32 [get_ports {HB_N[7]}]
+# set_property PACKAGE_PIN P29 [get_ports {HB_N[8]}]
+# set_property PACKAGE_PIN P30 [get_ports {HB_N[9]}]
+# set_property PACKAGE_PIN K28 [get_ports {HB_N[10]}]
+# set_property PACKAGE_PIN L29 [get_ports {HB_N[11]}]
+# set_property PACKAGE_PIN K31 [get_ports {HB_N[12]}]
+# set_property PACKAGE_PIN L33 [get_ports {HB_N[13]}]
+# set_property PACKAGE_PIN U31 [get_ports {HB_N[14]}]
+# set_property PACKAGE_PIN N33 [get_ports {HB_N[15]}]
+# set_property PACKAGE_PIN L34 [get_ports {HB_N[16]}]
+# set_property PACKAGE_PIN R28 [get_ports {HB_N[18]}]
+# set_property PACKAGE_PIN N27 [get_ports {HB_N[19]}]
+# set_property PACKAGE_PIN U34 [get_ports {HB_N[20]}]
+# set_property PACKAGE_PIN N34 [get_ports {HB_N[21]}]
+# set_property PACKAGE_PIN N31 [get_ports {HB_P[0]}]
+# set_property PACKAGE_PIN M31 [get_ports {HB_N[0]}]
+# set_property PACKAGE_PIN U32 [get_ports {HB_P[1]}]
+# set_property PACKAGE_PIN V32 [get_ports {HB_P[2]}]
+# set_property PACKAGE_PIN V28 [get_ports {HB_P[3]}]
+# set_property PACKAGE_PIN U30 [get_ports {HB_P[4]}]
+# set_property PACKAGE_PIN T33 [get_ports {HB_P[5]}]
+# set_property PACKAGE_PIN M30 [get_ports {HB_P[6]}]
+# set_property PACKAGE_PIN L30 [get_ports {HB_N[6]}]
+# set_property PACKAGE_PIN R31 [get_ports {HB_P[7]}]
+# set_property PACKAGE_PIN P28 [get_ports {HB_P[8]}]
+# set_property PACKAGE_PIN R30 [get_ports {HB_P[9]}]
+# set_property PACKAGE_PIN L28 [get_ports {HB_P[10]}]
+# set_property PACKAGE_PIN M29 [get_ports {HB_P[11]}]
+# set_property PACKAGE_PIN K30 [get_ports {HB_P[12]}]
+# set_property PACKAGE_PIN L32 [get_ports {HB_P[13]}]
+# set_property PACKAGE_PIN V31 [get_ports {HB_P[14]}]
+# set_property PACKAGE_PIN P33 [get_ports {HB_P[15]}]
+# set_property PACKAGE_PIN M34 [get_ports {HB_P[16]}]
+# set_property PACKAGE_PIN N32 [get_ports {HB_P[17]}]
+# set_property PACKAGE_PIN M32 [get_ports {HB_N[17]}]
+# set_property PACKAGE_PIN T28 [get_ports {HB_P[18]}]
+# set_property PACKAGE_PIN N26 [get_ports {HB_P[19]}]
+# set_property PACKAGE_PIN V34 [get_ports {HB_P[20]}]
+# set_property PACKAGE_PIN P34 [get_ports {HB_P[21]}]
+# set_property IOSTANDARD LVCMOS33 [get_ports {CLK_CFG}]
+# set_property PACKAGE_PIN AT27 [get_ports {CLK_CFG}]
+# set_property IOSTANDARD LVCMOS33 [get_ports {IOFPGA_CSIB}]
+# set_property PACKAGE_PIN BA27 [get_ports {IOFPGA_CSIB}]
+# set_property IOSTANDARD LVCMOS33 [get_ports {IOFPGA_D[4]}]
+# set_property PACKAGE_PIN AV26 [get_ports {IOFPGA_D[4]}]
+# set_property IOSTANDARD LVCMOS33 [get_ports {IOFPGA_D[5]}]
+# set_property PACKAGE_PIN AV27 [get_ports {IOFPGA_D[5]}]
+# set_property IOSTANDARD LVCMOS33 [get_ports {IOFPGA_D[6]}]
+# set_property PACKAGE_PIN AU29 [get_ports {IOFPGA_D[6]}]
+# set_property IOSTANDARD LVCMOS33 [get_ports {IOFPGA_D[7]}]
+# set_property PACKAGE_PIN AV29 [get_ports {IOFPGA_D[7]}]
+set_property IOSTANDARD LVCMOS18 [get_ports IOFPGA_NRST]
+set_property PACKAGE_PIN AV31 [get_ports IOFPGA_NRST]
+set_property IOSTANDARD LVCMOS18 [get_ports IOFPGA_NSPIR]
+set_property PACKAGE_PIN AV32 [get_ports IOFPGA_NSPIR]
+set_property IOSTANDARD LVCMOS33 [get_ports IOFPGA_SYSWDT]
+set_property PACKAGE_PIN AU20 [get_ports IOFPGA_SYSWDT]
+# not used
+# set_property PACKAGE_PIN AN27 [get_ports {LA_N[2]}]
+# set_property PACKAGE_PIN AP30 [get_ports {LA_N[3]}]
+# set_property PACKAGE_PIN AN29 [get_ports {LA_N[4]}]
+# set_property PACKAGE_PIN AR35 [get_ports {LA_N[5]}]
+# set_property PACKAGE_PIN AR33 [get_ports {LA_N[6]}]
+# set_property PACKAGE_PIN AN32 [get_ports {LA_N[7]}]
+# set_property PACKAGE_PIN AP31 [get_ports {LA_N[8]}]
+# set_property PACKAGE_PIN AN34 [get_ports {LA_N[9]}]
+# set_property PACKAGE_PIN AL35 [get_ports {LA_N[10]}]
+# set_property PACKAGE_PIN AM36 [get_ports {LA_N[11]}]
+# set_property PACKAGE_PIN AP34 [get_ports {LA_N[12]}]
+# set_property PACKAGE_PIN AL32 [get_ports {LA_N[13]}]
+# set_property PACKAGE_PIN AK36 [get_ports {LA_N[14]}]
+# set_property PACKAGE_PIN AJ34 [get_ports {LA_N[15]}]
+# set_property PACKAGE_PIN AL33 [get_ports {LA_N[16]}]
+# set_property PACKAGE_PIN AJ29 [get_ports {LA_N[19]}]
+# set_property PACKAGE_PIN AJ33 [get_ports {LA_N[20]}]
+# set_property PACKAGE_PIN AH29 [get_ports {LA_N[21]}]
+# set_property PACKAGE_PIN AH31 [get_ports {LA_N[22]}]
+# set_property PACKAGE_PIN AG30 [get_ports {LA_N[23]}]
+# set_property PACKAGE_PIN G32 [get_ports {LA_N[24]}]
+# set_property PACKAGE_PIN H34 [get_ports {LA_N[25]}]
+# set_property PACKAGE_PIN H31 [get_ports {LA_N[26]}]
+# set_property PACKAGE_PIN K33 [get_ports {LA_N[27]}]
+# set_property PACKAGE_PIN H29 [get_ports {LA_N[28]}]
+# set_property PACKAGE_PIN H33 [get_ports {LA_N[29]}]
+# set_property PACKAGE_PIN F34 [get_ports {LA_N[30]}]
+# set_property PACKAGE_PIN E33 [get_ports {LA_N[31]}]
+# set_property PACKAGE_PIN C34 [get_ports {LA_N[32]}]
+# set_property PACKAGE_PIN G30 [get_ports {LA_N[33]}]
+# set_property PACKAGE_PIN AM29 [get_ports {LA_P[0]}]
+# set_property PACKAGE_PIN AM30 [get_ports {LA_N[0]}]
+# set_property PACKAGE_PIN AL29 [get_ports {LA_P[1]}]
+# set_property PACKAGE_PIN AL30 [get_ports {LA_N[1]}]
+# set_property PACKAGE_PIN AM27 [get_ports {LA_P[2]}]
+# set_property PACKAGE_PIN AP29 [get_ports {LA_P[3]}]
+# set_property PACKAGE_PIN AN28 [get_ports {LA_P[4]}]
+# set_property PACKAGE_PIN AP35 [get_ports {LA_P[5]}]
+# set_property PACKAGE_PIN AP33 [get_ports {LA_P[6]}]
+# set_property PACKAGE_PIN AM32 [get_ports {LA_P[7]}]
+# set_property PACKAGE_PIN AN31 [get_ports {LA_P[8]}]
+# set_property PACKAGE_PIN AM34 [get_ports {LA_P[9]}]
+# set_property PACKAGE_PIN AL34 [get_ports {LA_P[10]}]
+# set_property PACKAGE_PIN AM35 [get_ports {LA_P[11]}]
+# set_property PACKAGE_PIN AN33 [get_ports {LA_P[12]}]
+# set_property PACKAGE_PIN AK32 [get_ports {LA_P[13]}]
+# set_property PACKAGE_PIN AK35 [get_ports {LA_P[14]}]
+# set_property PACKAGE_PIN AH34 [get_ports {LA_P[15]}]
+# set_property PACKAGE_PIN AK33 [get_ports {LA_P[16]}]
+# set_property PACKAGE_PIN AK30 [get_ports {LA_P[17]}]
+# set_property PACKAGE_PIN AK31 [get_ports {LA_N[17]}]
+# set_property PACKAGE_PIN AJ30 [get_ports {LA_P[18]}]
+# set_property PACKAGE_PIN AJ31 [get_ports {LA_N[18]}]
+# set_property PACKAGE_PIN AJ28 [get_ports {LA_P[19]}]
+# set_property PACKAGE_PIN AH33 [get_ports {LA_P[20]}]
+# set_property PACKAGE_PIN AH28 [get_ports {LA_P[21]}]
+# set_property PACKAGE_PIN AG31 [get_ports {LA_P[22]}]
+# set_property PACKAGE_PIN AG29 [get_ports {LA_P[23]}]
+# set_property PACKAGE_PIN H32 [get_ports {LA_P[24]}]
+# set_property PACKAGE_PIN J34 [get_ports {LA_P[25]}]
+# set_property PACKAGE_PIN J30 [get_ports {LA_P[26]}]
+# set_property PACKAGE_PIN K32 [get_ports {LA_P[27]}]
+# set_property PACKAGE_PIN J29 [get_ports {LA_P[28]}]
+# set_property PACKAGE_PIN J33 [get_ports {LA_P[29]}]
+# set_property PACKAGE_PIN G34 [get_ports {LA_P[30]}]
+# set_property PACKAGE_PIN F33 [get_ports {LA_P[31]}]
+# set_property PACKAGE_PIN D34 [get_ports {LA_P[32]}]
+# set_property PACKAGE_PIN G29 [get_ports {LA_P[33]}]
+set_property PACKAGE_PIN AM17 [get_ports {MMB_DATA[0]}]
+set_property PACKAGE_PIN AL14 [get_ports {MMB_DATA[1]}]
+set_property PACKAGE_PIN AK15 [get_ports {MMB_DATA[2]}]
+set_property PACKAGE_PIN AK17 [get_ports {MMB_DATA[3]}]
+set_property PACKAGE_PIN AM14 [get_ports {MMB_DATA[4]}]
+set_property PACKAGE_PIN AN13 [get_ports {MMB_DATA[5]}]
+set_property PACKAGE_PIN AM11 [get_ports {MMB_DATA[6]}]
+set_property PACKAGE_PIN AN11 [get_ports {MMB_DATA[7]}]
+set_property PACKAGE_PIN AR13 [get_ports {MMB_DATA[8]}]
+set_property PACKAGE_PIN AR12 [get_ports {MMB_DATA[9]}]
+set_property PACKAGE_PIN AL10 [get_ports {MMB_DATA[10]}]
+set_property PACKAGE_PIN AM10 [get_ports {MMB_DATA[11]}]
+set_property PACKAGE_PIN AM12 [get_ports {MMB_DATA[12]}]
+set_property PACKAGE_PIN AN12 [get_ports {MMB_DATA[13]}]
+set_property PACKAGE_PIN AP13 [get_ports {MMB_DATA[14]}]
+set_property PACKAGE_PIN AK13 [get_ports {MMB_DATA[15]}]
+set_property PACKAGE_PIN AK12 [get_ports {MMB_DATA[16]}]
+set_property PACKAGE_PIN AK11 [get_ports {MMB_DATA[17]}]
+set_property PACKAGE_PIN AK10 [get_ports {MMB_DATA[18]}]
+set_property PACKAGE_PIN AH13 [get_ports {MMB_DATA[19]}]
+set_property PACKAGE_PIN AJ13 [get_ports {MMB_DATA[20]}]
+set_property PACKAGE_PIN AJ11 [get_ports {MMB_DATA[21]}]
+set_property PACKAGE_PIN AJ10 [get_ports {MMB_DATA[22]}]
+set_property PACKAGE_PIN AH12 [get_ports {MMB_DATA[23]}]
+set_property PACKAGE_PIN AH11 [get_ports MMB_DE]
+set_property PACKAGE_PIN AG12 [get_ports MMB_HS]
+set_property PACKAGE_PIN AH14 [get_ports MMB_IDCLK]
+set_property PACKAGE_PIN AF29 [get_ports MMB_SCK]
+set_property PACKAGE_PIN AC28 [get_ports {MMB_SD[0]}]
+set_property PACKAGE_PIN AC29 [get_ports {MMB_SD[1]}]
+set_property PACKAGE_PIN AE27 [get_ports {MMB_SD[2]}]
+set_property PACKAGE_PIN AF34 [get_ports {MMB_SD[3]}]
+set_property PACKAGE_PIN AG11 [get_ports MMB_VS]
+set_property PACKAGE_PIN AF30 [get_ports MMB_WS]
+set_property PACKAGE_PIN AL15 [get_ports {OSCCLK[0]}]
+set_property PACKAGE_PIN AK16 [get_ports {OSCCLK[1]}]
+set_property PACKAGE_PIN AY32 [get_ports {OSCCLK[2]}]
+set_property PACKAGE_PIN AY30 [get_ports {OSCCLK[3]}]
+set_property PACKAGE_PIN AC31 [get_ports {OSCCLK[4]}]
+set_property PACKAGE_PIN AC32 [get_ports {OSCCLK[5]}]
+set_property PACKAGE_PIN AT29 [get_ports PB_IRQ]
+
+set_property IOSTANDARD LVCMOS33 [get_ports QSPI_D0]
+set_property PACKAGE_PIN AU24 [get_ports QSPI_D0]
+set_property IOSTANDARD LVCMOS33 [get_ports QSPI_D1]
+set_property PACKAGE_PIN AV24 [get_ports QSPI_D1]
+set_property IOSTANDARD LVCMOS33 [get_ports QSPI_D2]
+set_property PACKAGE_PIN AV21 [get_ports QSPI_D2]
+set_property IOSTANDARD LVCMOS33 [get_ports QSPI_D3]
+set_property PACKAGE_PIN AV22 [get_ports QSPI_D3]
+set_property IOSTANDARD LVCMOS33 [get_ports QSPI_nCS]
+set_property PACKAGE_PIN AT24 [get_ports QSPI_nCS]
+set_property IOSTANDARD LVCMOS33 [get_ports QSPI_SCLK]
+set_property PACKAGE_PIN AT25 [get_ports QSPI_SCLK]
+# not used
+# set_property PACKAGE_PIN AL13 [get_ports SATA_CLK_P]
+# set_property PACKAGE_PIN AL12 [get_ports SATA_CLK_N]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[0]}]
+set_property PACKAGE_PIN AW14 [get_ports {SH0_IO[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[1]}]
+set_property PACKAGE_PIN AW13 [get_ports {SH0_IO[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[2]}]
+set_property PACKAGE_PIN AW15 [get_ports {SH0_IO[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[3]}]
+set_property PACKAGE_PIN AY15 [get_ports {SH0_IO[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[4]}]
+set_property PACKAGE_PIN AY13 [get_ports {SH0_IO[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[5]}]
+set_property PACKAGE_PIN AY12 [get_ports {SH0_IO[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[6]}]
+set_property PACKAGE_PIN BA15 [get_ports {SH0_IO[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[7]}]
+set_property PACKAGE_PIN BB14 [get_ports {SH0_IO[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[8]}]
+set_property PACKAGE_PIN BA12 [get_ports {SH0_IO[8]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[9]}]
+set_property PACKAGE_PIN BB12 [get_ports {SH0_IO[9]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[10]}]
+set_property PACKAGE_PIN BA14 [get_ports {SH0_IO[10]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[11]}]
+set_property PACKAGE_PIN BA13 [get_ports {SH0_IO[11]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[12]}]
+set_property PACKAGE_PIN BB15 [get_ports {SH0_IO[12]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[13]}]
+set_property PACKAGE_PIN AU12 [get_ports {SH0_IO[13]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[14]}]
+set_property PACKAGE_PIN AV12 [get_ports {SH0_IO[14]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[15]}]
+set_property PACKAGE_PIN AV17 [get_ports {SH0_IO[15]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[16]}]
+set_property PACKAGE_PIN AV16 [get_ports {SH0_IO[16]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[17]}]
+set_property PACKAGE_PIN AT14 [get_ports {SH0_IO[17]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[0]}]
+set_property PACKAGE_PIN AT17 [get_ports {SH1_IO[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[1]}]
+set_property PACKAGE_PIN AU17 [get_ports {SH1_IO[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[2]}]
+set_property PACKAGE_PIN AV19 [get_ports {SH1_IO[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[3]}]
+set_property PACKAGE_PIN AW19 [get_ports {SH1_IO[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[4]}]
+set_property PACKAGE_PIN AW20 [get_ports {SH1_IO[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[5]}]
+set_property PACKAGE_PIN BA19 [get_ports {SH1_IO[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[6]}]
+set_property PACKAGE_PIN BA18 [get_ports {SH1_IO[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[7]}]
+set_property PACKAGE_PIN AY20 [get_ports {SH1_IO[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[8]}]
+set_property PACKAGE_PIN BA20 [get_ports {SH1_IO[8]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[9]}]
+set_property PACKAGE_PIN BA17 [get_ports {SH1_IO[9]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[10]}]
+set_property PACKAGE_PIN BB17 [get_ports {SH1_IO[10]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[11]}]
+set_property PACKAGE_PIN BB20 [get_ports {SH1_IO[11]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[12]}]
+set_property PACKAGE_PIN BB19 [get_ports {SH1_IO[12]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[13]}]
+set_property PACKAGE_PIN AW16 [get_ports {SH1_IO[13]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[14]}]
+set_property PACKAGE_PIN AY16 [get_ports {SH1_IO[14]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[15]}]
+set_property PACKAGE_PIN AY18 [get_ports {SH1_IO[15]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[16]}]
+set_property PACKAGE_PIN AY17 [get_ports {SH1_IO[16]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[17]}]
+set_property PACKAGE_PIN BB16 [get_ports {SH1_IO[17]}]
+set_property PACKAGE_PIN AL25 [get_ports SH_ADC_CK]
+set_property PACKAGE_PIN AM25 [get_ports SH_ADC_CS]
+set_property PACKAGE_PIN AP25 [get_ports SH_ADC_DI]
+set_property PACKAGE_PIN AP26 [get_ports SH_ADC_DO]
+set_property IOSTANDARD LVCMOS33 [get_ports SH_nRST]
+set_property PACKAGE_PIN AU14 [get_ports SH_nRST]
+set_property PACKAGE_PIN AK20 [get_ports {SMBF_ADDR[0]}]
+set_property PACKAGE_PIN AK21 [get_ports {SMBF_ADDR[1]}]
+set_property PACKAGE_PIN AJ18 [get_ports {SMBF_ADDR[2]}]
+set_property PACKAGE_PIN AJ19 [get_ports {SMBF_ADDR[3]}]
+set_property PACKAGE_PIN AH21 [get_ports {SMBF_ADDR[4]}]
+set_property PACKAGE_PIN AJ21 [get_ports {SMBF_ADDR[5]}]
+set_property PACKAGE_PIN AH19 [get_ports {SMBF_ADDR[6]}]
+set_property PACKAGE_PIN AK22 [get_ports {SMBF_DATA[0]}]
+set_property PACKAGE_PIN AL22 [get_ports {SMBF_DATA[1]}]
+set_property PACKAGE_PIN AL19 [get_ports {SMBF_DATA[2]}]
+set_property PACKAGE_PIN AL20 [get_ports {SMBF_DATA[3]}]
+set_property PACKAGE_PIN AH18 [get_ports {SMBF_DATA[4]}]
+set_property PACKAGE_PIN AM19 [get_ports {SMBF_DATA[5]}]
+set_property PACKAGE_PIN AN19 [get_ports {SMBF_DATA[6]}]
+set_property PACKAGE_PIN AP19 [get_ports {SMBF_DATA[7]}]
+set_property PACKAGE_PIN AP20 [get_ports {SMBF_DATA[8]}]
+set_property PACKAGE_PIN AM20 [get_ports {SMBF_DATA[9]}]
+set_property PACKAGE_PIN AN21 [get_ports {SMBF_DATA[10]}]
+set_property PACKAGE_PIN AP21 [get_ports {SMBF_DATA[11]}]
+set_property PACKAGE_PIN AR22 [get_ports {SMBF_DATA[12]}]
+set_property PACKAGE_PIN AM21 [get_ports {SMBF_DATA[13]}]
+set_property PACKAGE_PIN AM22 [get_ports {SMBF_DATA[14]}]
+set_property PACKAGE_PIN AN22 [get_ports {SMBF_DATA[15]}]
+set_property PACKAGE_PIN AJ20 [get_ports SMBF_FIFOSEL]
+set_property PACKAGE_PIN AN23 [get_ports SMBF_nOE]
+set_property PACKAGE_PIN AL23 [get_ports SMBF_nRST]
+set_property PACKAGE_PIN AP23 [get_ports SMBF_nWE]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[16]}]
+set_property PACKAGE_PIN AR26 [get_ports {SMBM_A[16]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[17]}]
+set_property PACKAGE_PIN AT22 [get_ports {SMBM_A[17]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[18]}]
+set_property PACKAGE_PIN AT23 [get_ports {SMBM_A[18]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[19]}]
+set_property PACKAGE_PIN AU21 [get_ports {SMBM_A[19]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[20]}]
+set_property PACKAGE_PIN AY22 [get_ports {SMBM_A[20]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[21]}]
+set_property PACKAGE_PIN BA22 [get_ports {SMBM_A[21]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[22]}]
+set_property PACKAGE_PIN AW21 [get_ports {SMBM_A[22]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[23]}]
+set_property PACKAGE_PIN AY21 [get_ports {SMBM_A[23]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[24]}]
+set_property PACKAGE_PIN BA23 [get_ports {SMBM_A[24]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[25]}]
+set_property PACKAGE_PIN BA24 [get_ports {SMBM_A[25]}]
+set_property IOSTANDARD LVCMOS33 [get_ports SMBM_CLK]
+set_property PACKAGE_PIN AY25 [get_ports SMBM_CLK]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[0]}]
+set_property PACKAGE_PIN BB21 [get_ports {SMBM_D[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[1]}]
+set_property PACKAGE_PIN BB22 [get_ports {SMBM_D[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[2]}]
+set_property PACKAGE_PIN AW24 [get_ports {SMBM_D[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[3]}]
+set_property PACKAGE_PIN AW25 [get_ports {SMBM_D[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[4]}]
+set_property PACKAGE_PIN AW23 [get_ports {SMBM_D[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[5]}]
+set_property PACKAGE_PIN AY23 [get_ports {SMBM_D[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[6]}]
+set_property PACKAGE_PIN BB24 [get_ports {SMBM_D[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[7]}]
+set_property PACKAGE_PIN AY27 [get_ports {SMBM_D[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[8]}]
+set_property PACKAGE_PIN AY26 [get_ports {SMBM_D[8]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[9]}]
+set_property PACKAGE_PIN AY28 [get_ports {SMBM_D[9]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[10]}]
+set_property PACKAGE_PIN BA28 [get_ports {SMBM_D[10]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[11]}]
+set_property PACKAGE_PIN BA25 [get_ports {SMBM_D[11]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[12]}]
+set_property PACKAGE_PIN BB25 [get_ports {SMBM_D[12]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[13]}]
+set_property PACKAGE_PIN AW28 [get_ports {SMBM_D[13]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[14]}]
+set_property PACKAGE_PIN AW29 [get_ports {SMBM_D[14]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[15]}]
+set_property PACKAGE_PIN BB26 [get_ports {SMBM_D[15]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_nBL[0]}]
+set_property PACKAGE_PIN AU26 [get_ports {SMBM_nBL[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_nBL[1]}]
+set_property PACKAGE_PIN AR28 [get_ports {SMBM_nBL[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_nE[1]}]
+set_property PACKAGE_PIN BB27 [get_ports {SMBM_nE[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_nE[2]}]
+set_property PACKAGE_PIN AU27 [get_ports {SMBM_nE[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_nE[3]}]
+set_property PACKAGE_PIN AV28 [get_ports {SMBM_nE[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_nE[4]}]
+set_property PACKAGE_PIN AU25 [get_ports {SMBM_nE[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports SMBM_nOE]
+set_property PACKAGE_PIN AT28 [get_ports SMBM_nOE]
+set_property IOSTANDARD LVCMOS33 [get_ports SMBM_nWAIT]
+set_property PACKAGE_PIN AP28 [get_ports SMBM_nWAIT]
+set_property IOSTANDARD LVCMOS33 [get_ports SMBM_nWE]
+set_property PACKAGE_PIN AR27 [get_ports SMBM_nWE]
+set_property PACKAGE_PIN AF28 [get_ports {UART_RX_F[0]}]
+set_property PACKAGE_PIN AE31 [get_ports {UART_RX_F[1]}]
+set_property PACKAGE_PIN AE28 [get_ports {UART_RX_F[2]}]
+set_property PACKAGE_PIN AD30 [get_ports {UART_RX_F[3]}]
+set_property PACKAGE_PIN AF27 [get_ports {UART_TX_F[0]}]
+set_property PACKAGE_PIN AE30 [get_ports {UART_TX_F[1]}]
+set_property PACKAGE_PIN AD28 [get_ports {UART_TX_F[2]}]
+set_property PACKAGE_PIN AD29 [get_ports {UART_TX_F[3]}]
+set_property PACKAGE_PIN AN26 [get_ports USB_DACK]
+set_property PACKAGE_PIN AN24 [get_ports USB_DREQ]
+set_property PACKAGE_PIN AP24 [get_ports USB_INT]
+set_property PACKAGE_PIN AM26 [get_ports USB_nCS]
+set_property IOSTANDARD LVCMOS33 [get_ports USD_CLK]
+set_property PACKAGE_PIN AU15 [get_ports USD_CLK]
+set_property IOSTANDARD LVCMOS33 [get_ports USD_CMD]
+set_property PACKAGE_PIN AU16 [get_ports USD_CMD]
+set_property IOSTANDARD LVCMOS33 [get_ports {USD_DAT[0]}]
+set_property PACKAGE_PIN AV14 [get_ports {USD_DAT[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {USD_DAT[1]}]
+set_property PACKAGE_PIN AV13 [get_ports {USD_DAT[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {USD_DAT[2]}]
+set_property PACKAGE_PIN AT13 [get_ports {USD_DAT[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {USD_DAT[3]}]
+set_property PACKAGE_PIN AT12 [get_ports {USD_DAT[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports USD_NCD]
+set_property PACKAGE_PIN AT15 [get_ports USD_NCD]
+set_property PACKAGE_PIN AU32 [get_ports {USER_nLED[0]}]
+set_property PACKAGE_PIN AU30 [get_ports {USER_nLED[1]}]
+set_property PACKAGE_PIN AU31 [get_ports {USER_nLED[2]}]
+set_property PACKAGE_PIN AR32 [get_ports {USER_nLED[3]}]
+set_property PACKAGE_PIN AT33 [get_ports {USER_nLED[4]}]
+set_property PACKAGE_PIN AW30 [get_ports {USER_nLED[5]}]
+set_property PACKAGE_PIN AW31 [get_ports {USER_nLED[6]}]
+set_property PACKAGE_PIN AR30 [get_ports {USER_nLED[7]}]
+set_property PACKAGE_PIN BB31 [get_ports {USER_nLED[8]}]
+set_property PACKAGE_PIN BB32 [get_ports {USER_nLED[9]}]
+set_property PACKAGE_PIN AT30 [get_ports {USER_nPB[0]}]
+set_property PACKAGE_PIN AT32 [get_ports {USER_nPB[1]}]
+set_property PACKAGE_PIN BA29 [get_ports {USER_SW[0]}]
+set_property PACKAGE_PIN BB29 [get_ports {USER_SW[1]}]
+set_property PACKAGE_PIN BA32 [get_ports {USER_SW[2]}]
+set_property PACKAGE_PIN BA33 [get_ports {USER_SW[3]}]
+set_property PACKAGE_PIN BA30 [get_ports {USER_SW[4]}]
+set_property PACKAGE_PIN BB30 [get_ports {USER_SW[5]}]
+set_property PACKAGE_PIN AY33 [get_ports {USER_SW[6]}]
+set_property PACKAGE_PIN AY31 [get_ports {USER_SW[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports WDOG_RREQ]
+set_property PACKAGE_PIN AU19 [get_ports WDOG_RREQ]
+
+# native DDR pin names
+
+# set_property PACKAGE_PIN A17 [get_ports {c0_ddr4_dq[37]}]
+# set_property PACKAGE_PIN F24 [get_ports {c0_ddr4_dq[54]}]
+# set_property PACKAGE_PIN F23 [get_ports {c0_ddr4_dq[55]}]
+# set_property PACKAGE_PIN B15 [get_ports {c0_ddr4_dq[28]}]
+# set_property PACKAGE_PIN D23 [get_ports {c0_ddr4_dq[52]}]
+# set_property PACKAGE_PIN D24 [get_ports {c0_ddr4_dq[53]}]
+# set_property PACKAGE_PIN C24 [get_ports {c0_ddr4_dm_dbi_n[5]}]
+# set_property PACKAGE_PIN A22 [get_ports {c0_ddr4_dq[46]}]
+# set_property PACKAGE_PIN A23 [get_ports {c0_ddr4_dq[47]}]
+# set_property PACKAGE_PIN C13 [get_ports {c0_ddr4_dq[29]}]
+# set_property PACKAGE_PIN A14 [get_ports {c0_ddr4_dq[27]}]
+# set_property PACKAGE_PIN E22 [get_ports {c0_ddr4_dqs_t[6]}]
+# set_property PACKAGE_PIN E21 [get_ports {c0_ddr4_dqs_c[6]}]
+# set_property PACKAGE_PIN G22 [get_ports {c0_ddr4_dq[50]}]
+# set_property PACKAGE_PIN G21 [get_ports {c0_ddr4_dq[51]}]
+# set_property PACKAGE_PIN H24 [get_ports {c0_ddr4_dm_dbi_n[6]}]
+# set_property PACKAGE_PIN A24 [get_ports {c0_ddr4_dq[42]}]
+# set_property PACKAGE_PIN B22 [get_ports {c0_ddr4_dqs_t[5]}]
+# set_property PACKAGE_PIN B21 [get_ports {c0_ddr4_dqs_c[5]}]
+# set_property PACKAGE_PIN B17 [get_ports {c0_ddr4_dqs_t[4]}]
+# set_property PACKAGE_PIN B16 [get_ports {c0_ddr4_dqs_c[4]}]
+# set_property PACKAGE_PIN A18 [get_ports {c0_ddr4_dq[38]}]
+# set_property PACKAGE_PIN A12 [get_ports {c0_ddr4_dq[31]}]
+# set_property PACKAGE_PIN D25 [get_ports {c0_ddr4_dq[48]}]
+# set_property PACKAGE_PIN E23 [get_ports {c0_ddr4_dq[49]}]
+# set_property PACKAGE_PIN C23 [get_ports {c0_ddr4_dq[40]}]
+# set_property PACKAGE_PIN A25 [get_ports {c0_ddr4_dq[43]}]
+# set_property PACKAGE_PIN C22 [get_ports {c0_ddr4_dq[44]}]
+# set_property PACKAGE_PIN B14 [get_ports {c0_ddr4_dq[24]}]
+# set_property PACKAGE_PIN K18 [get_ports {c0_ddr4_adr[4]}]
+# set_property PACKAGE_PIN C21 [get_ports {c0_ddr4_dq[41]}]
+# set_property PACKAGE_PIN D21 [get_ports {c0_ddr4_dq[45]}]
+# set_property PACKAGE_PIN C16 [get_ports {c0_ddr4_dq[32]}]
+# set_property PACKAGE_PIN E12 [get_ports {c0_ddr4_dq[16]}]
+# set_property PACKAGE_PIN D13 [get_ports {c0_ddr4_dq[25]}]
+# set_property PACKAGE_PIN C12 [get_ports {c0_ddr4_dqs_t[3]}]
+# set_property PACKAGE_PIN B12 [get_ports {c0_ddr4_dqs_c[3]}]
+# set_property PACKAGE_PIN E15 [get_ports {c0_ddr4_dq[18]}]
+# #set_property PACKAGE_PIN P18 [get_ports {c0_ddr4_ck_t[1]}]
+# #set_property PACKAGE_PIN N18 [get_ports {c0_ddr4_ck_c[1]}]
+# set_property PACKAGE_PIN L19 [get_ports {c0_ddr4_adr[0]}]
+# set_property PACKAGE_PIN J18 [get_ports {c0_ddr4_adr[5]}]
+# #set_property PACKAGE_PIN E20 [get_ports {c0_ddr4_cke[0]}]
+# set_property PACKAGE_PIN E20 [get_ports {c0_ddr4_cke}]
+# set_property PACKAGE_PIN D19 [get_ports c0_ddr4_act_n]
+# set_property PACKAGE_PIN F12 [get_ports {c0_ddr4_dq[17]}]
+# set_property PACKAGE_PIN F15 [get_ports {c0_ddr4_dq[19]}]
+# set_property PACKAGE_PIN L18 [get_ports {c0_ddr4_adr[2]}]
+# set_property PACKAGE_PIN K16 [get_ports {c0_ddr4_adr[3]}]
+# set_property PACKAGE_PIN J16 [get_ports {c0_ddr4_adr[1]}]
+# #set_property PACKAGE_PIN E17 [get_ports {c0_ddr4_cke[1]}]
+# set_property PACKAGE_PIN E18 [get_ports c0_ddr4_reset_n]
+# set_property PACKAGE_PIN F14 [get_ports {c0_ddr4_dqs_t[2]}]
+# set_property PACKAGE_PIN F13 [get_ports {c0_ddr4_dqs_c[2]}]
+# #set_property PACKAGE_PIN P16 [get_ports {c0_ddr4_ck_t[0]}]
+# set_property PACKAGE_PIN P16 [get_ports {c0_ddr4_ck_t}]
+# #set_property PACKAGE_PIN N16 [get_ports {c0_ddr4_ck_c[0]}]
+# set_property PACKAGE_PIN N16 [get_ports {c0_ddr4_ck_c}]
+# set_property PACKAGE_PIN F19 [get_ports {c0_ddr4_bg[0]}]
+# #set_property PACKAGE_PIN F18 [get_ports {c0_ddr4_bg[1]}]
+# #set_property PACKAGE_PIN E16 [get_ports {c0_ddr4_odt[0]}]
+# set_property PACKAGE_PIN E16 [get_ports {c0_ddr4_odt}]
+# #set_property PACKAGE_PIN F17 [get_ports {c0_ddr4_cs_n[0]}]
+# set_property PACKAGE_PIN F17 [get_ports {c0_ddr4_cs_n}]
+# #set_property PACKAGE_PIN F20 [get_ports {c0_ddr4_cs_n[1]}]
+# #set_property PACKAGE_PIN D20 [get_ports {c0_ddr4_odt[1]}]
+# set_property PACKAGE_PIN K13 [get_ports {c0_ddr4_dq[10]}]
+# set_property PACKAGE_PIN J14 [get_ports {c0_ddr4_dq[11]}]
+# set_property PACKAGE_PIN H17 [get_ports {c0_ddr4_adr[16]}]
+# set_property PACKAGE_PIN G17 [get_ports {c0_ddr4_ba[0]}]
+# set_property PACKAGE_PIN H16 [get_ports {c0_ddr4_adr[14]}]
+# set_property PACKAGE_PIN G19 [get_ports {c0_ddr4_ba[1]}]
+# set_property PACKAGE_PIN N11 [get_ports {c0_ddr4_dqs_t[0]}]
+# set_property PACKAGE_PIN M11 [get_ports {c0_ddr4_dqs_c[0]}]
+# set_property PACKAGE_PIN J15 [get_ports {c0_ddr4_dq[8]}]
+# set_property PACKAGE_PIN K15 [get_ports {c0_ddr4_dq[9]}]
+# set_property PACKAGE_PIN G16 [get_ports {c0_ddr4_adr[15]}]
+# set_property PACKAGE_PIN M10 [get_ports {c0_ddr4_dq[6]}]
+# set_property PACKAGE_PIN L10 [get_ports {c0_ddr4_dq[7]}]
+# set_property PACKAGE_PIN J11 [get_ports {c0_ddr4_dqs_t[1]}]
+# set_property PACKAGE_PIN J10 [get_ports {c0_ddr4_dqs_c[1]}]
+# set_property PACKAGE_PIN L17 [get_ports {c0_ddr4_adr[6]}]
+# set_property PACKAGE_PIN K17 [get_ports {c0_ddr4_adr[8]}]
+# set_property PACKAGE_PIN M17 [get_ports {c0_ddr4_adr[9]}]
+# set_property PACKAGE_PIN M16 [get_ports {c0_ddr4_adr[7]}]
+# set_property PACKAGE_PIN M19 [get_ports {c0_ddr4_adr[10]}]
+# set_property PACKAGE_PIN M15 [get_ports {c0_ddr4_adr[11]}]
+# set_property PACKAGE_PIN N17 [get_ports {c0_ddr4_adr[12]}]
+# set_property PACKAGE_PIN N19 [get_ports {c0_ddr4_adr[13]}]
+# set_property PACKAGE_PIN L22 [get_ports {c0_ddr4_dm_dbi_n[7]}]
+# set_property PACKAGE_PIN P11 [get_ports {c0_ddr4_dq[0]}]
+# set_property PACKAGE_PIN P10 [get_ports {c0_ddr4_dq[1]}]
+# set_property PACKAGE_PIN L12 [get_ports {c0_ddr4_dq[2]}]
+# set_property PACKAGE_PIN M12 [get_ports {c0_ddr4_dq[3]}]
+# set_property PACKAGE_PIN N13 [get_ports {c0_ddr4_dq[4]}]
+# set_property PACKAGE_PIN N12 [get_ports {c0_ddr4_dq[5]}]
+# set_property PACKAGE_PIN K11 [get_ports {c0_ddr4_dq[12]}]
+# set_property PACKAGE_PIN K10 [get_ports {c0_ddr4_dq[13]}]
+# set_property PACKAGE_PIN J13 [get_ports {c0_ddr4_dq[14]}]
+# set_property PACKAGE_PIN K12 [get_ports {c0_ddr4_dq[15]}]
+# set_property PACKAGE_PIN H12 [get_ports {c0_ddr4_dq[20]}]
+# set_property PACKAGE_PIN G12 [get_ports {c0_ddr4_dq[21]}]
+# set_property PACKAGE_PIN G15 [get_ports {c0_ddr4_dq[22]}]
+# set_property PACKAGE_PIN G14 [get_ports {c0_ddr4_dq[23]}]
+# set_property PACKAGE_PIN A13 [get_ports {c0_ddr4_dq[26]}]
+# set_property PACKAGE_PIN A15 [get_ports {c0_ddr4_dq[30]}]
+# set_property PACKAGE_PIN C19 [get_ports {c0_ddr4_dq[33]}]
+# set_property PACKAGE_PIN B19 [get_ports {c0_ddr4_dq[34]}]
+# set_property PACKAGE_PIN A20 [get_ports {c0_ddr4_dq[35]}]
+# set_property PACKAGE_PIN D16 [get_ports {c0_ddr4_dq[36]}]
+# set_property PACKAGE_PIN A19 [get_ports {c0_ddr4_dq[39]}]
+# set_property PACKAGE_PIN H22 [get_ports {c0_ddr4_dq[56]}]
+# set_property PACKAGE_PIN J23 [get_ports {c0_ddr4_dq[57]}]
+# set_property PACKAGE_PIN K20 [get_ports {c0_ddr4_dq[58]}]
+# set_property PACKAGE_PIN L20 [get_ports {c0_ddr4_dq[59]}]
+# set_property PACKAGE_PIN H21 [get_ports {c0_ddr4_dq[60]}]
+# set_property PACKAGE_PIN H23 [get_ports {c0_ddr4_dq[61]}]
+# set_property PACKAGE_PIN K23 [get_ports {c0_ddr4_dq[62]}]
+# set_property PACKAGE_PIN J21 [get_ports {c0_ddr4_dq[63]}]
+# set_property PACKAGE_PIN N14 [get_ports {c0_ddr4_dm_dbi_n[0]}]
+# set_property PACKAGE_PIN L14 [get_ports {c0_ddr4_dm_dbi_n[1]}]
+# set_property PACKAGE_PIN H14 [get_ports {c0_ddr4_dm_dbi_n[2]}]
+# set_property PACKAGE_PIN D14 [get_ports {c0_ddr4_dm_dbi_n[3]}]
+# set_property PACKAGE_PIN C18 [get_ports {c0_ddr4_dm_dbi_n[4]}]
+# set_property PACKAGE_PIN K21 [get_ports {c0_ddr4_dqs_t[7]}]
+
+#set_property CFGBVS GND [current_design]
+#set_property CONFIG_VOLTAGE 1.8 [current_design]
+
+# set_property PACKAGE_PIN H19 [get_ports c0_sys_clk_p]
+# set_property PACKAGE_PIN H18 [get_ports c0_sys_clk_n]
+
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports SATA_CLK_N]
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports SATA_CLK_P]
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports GTX_CLK_N]
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports GTX_CLK_P]
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports {CLK_M2C_P[1]}]
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports {CLK_M2C_P[0]}]
+
+# set_property PACKAGE_PIN AB31 [get_ports GTX_CLK_P]
+# set_property PACKAGE_PIN AB32 [get_ports GTX_CLK_N]
+
+# set_property PACKAGE_PIN AH39 [get_ports {DP_C2M_N[0]}]
+# set_property PACKAGE_PIN AF39 [get_ports {DP_C2M_N[1]}]
+# set_property PACKAGE_PIN AD39 [get_ports {DP_C2M_N[2]}]
+# set_property PACKAGE_PIN AB39 [get_ports {DP_C2M_N[3]}]
+# set_property PACKAGE_PIN Y39 [get_ports {DP_C2M_N[4]}]
+# set_property PACKAGE_PIN V39 [get_ports {DP_C2M_N[5]}]
+# set_property PACKAGE_PIN K39 [get_ports {DP_C2M_N[6]}]
+# set_property PACKAGE_PIN M39 [get_ports {DP_C2M_N[7]}]
+# set_property PACKAGE_PIN P39 [get_ports {DP_C2M_N[8]}]
+# set_property PACKAGE_PIN T39 [get_ports {DP_C2M_N[9]}]
+# set_property PACKAGE_PIN AH38 [get_ports {DP_C2M_P[0]}]
+# set_property PACKAGE_PIN AF38 [get_ports {DP_C2M_P[1]}]
+# set_property PACKAGE_PIN AD38 [get_ports {DP_C2M_P[2]}]
+# set_property PACKAGE_PIN AB38 [get_ports {DP_C2M_P[3]}]
+# set_property PACKAGE_PIN Y38 [get_ports {DP_C2M_P[4]}]
+# set_property PACKAGE_PIN V38 [get_ports {DP_C2M_P[5]}]
+# set_property PACKAGE_PIN K38 [get_ports {DP_C2M_P[6]}]
+# set_property PACKAGE_PIN M38 [get_ports {DP_C2M_P[7]}]
+# set_property PACKAGE_PIN P38 [get_ports {DP_C2M_P[8]}]
+# set_property PACKAGE_PIN T38 [get_ports {DP_C2M_P[9]}]
+# set_property PACKAGE_PIN AE36 [get_ports {GBTCLK_M2C_P[0]}]
+# set_property PACKAGE_PIN AE37 [get_ports {GBTCLK_M2C_N[0]}]
+# set_property PACKAGE_PIN AA36 [get_ports {GBTCLK_M2C_P[1]}]
+# set_property PACKAGE_PIN AA37 [get_ports {GBTCLK_M2C_N[1]}]
+
+# create_clock -period 15.515 -name clk_mgtrefclk0_x0y4_p [get_ports {GBTCLK_M2C_P[0]}]
+# create_clock -period 15.515 -name clk_mgtrefclk0_x0y7_p [get_ports {GBTCLK_M2C_P[1]}]
+
+# # False path constraints
+# # ----------------------------------------------------------------------------------------------------------------------
+# set_false_path -to [get_cells -hierarchical -filter {NAME =~ *bit_synchronizer*inst/i_in_meta_reg}]
+# set_false_path -to [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_*_reg}]
+# set_false_path -to [get_cells -hierarchical -filter {NAME =~ *gtwiz_userclk_tx_inst/*gtwiz_userclk_tx_active_*_reg}]
+# set_false_path -to [get_cells -hierarchical -filter {NAME =~ *gtwiz_userclk_rx_inst/*gtwiz_userclk_rx_active_*_reg}]
+
+#set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets iACLK]
+#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets CFG_CLK_IBUF_inst/O]
+# set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets iGPUCLK]
+# set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets iMCLK]
+
+set_property PULLUP true [get_ports QSPI_D0]
+set_property PULLUP true [get_ports QSPI_D1]
+set_property PULLUP true [get_ports QSPI_D2]
+set_property PULLUP true [get_ports QSPI_D3]
+
+# set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_bg[0]"]
+# set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports "c0_ddr4_bg[0]"]
+
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property CFGBVS VCCO [current_design]
+set_property BITSTREAM.CONFIG.UNUSEDPIN Pullnone [current_design]
+set_property BITSTREAM.CONFIG.PERSIST Yes [current_design]
+set_property BITSTREAM.STARTUP.MATCH_CYCLE Auto [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS True [current_design]
+set_property CONFIG_MODE S_SELECTMAP [current_design]
+
+set_property PACKAGE_PIN AR26 [get_ports NRST]
+set_property PACKAGE_PIN AR27 [get_ports {P0[0]}]
+set_property PACKAGE_PIN AW29 [get_ports {P0[10]}]
+set_property PACKAGE_PIN BA25 [get_ports {P0[11]}]
+set_property PACKAGE_PIN BB25 [get_ports {P0[12]}]
+set_property PACKAGE_PIN AY28 [get_ports {P0[13]}]
+set_property PACKAGE_PIN BA28 [get_ports {P0[14]}]
+set_property PACKAGE_PIN AY26 [get_ports {P0[15]}]
+set_property PACKAGE_PIN AR28 [get_ports {P0[1]}]
+set_property PACKAGE_PIN AT28 [get_ports {P0[2]}]
+set_property PACKAGE_PIN AU25 [get_ports {P0[3]}]
+set_property PACKAGE_PIN AU26 [get_ports {P0[4]}]
+set_property PACKAGE_PIN AU27 [get_ports {P0[5]}]
+set_property PACKAGE_PIN AV28 [get_ports {P0[6]}]
+set_property PACKAGE_PIN BB26 [get_ports {P0[7]}]
+set_property PACKAGE_PIN BB27 [get_ports {P0[8]}]
+set_property PACKAGE_PIN AW28 [get_ports {P0[9]}]
+set_property PACKAGE_PIN AW26 [get_ports {P1[0]}]
+set_property PACKAGE_PIN AY21 [get_ports {P1[10]}]
+set_property PACKAGE_PIN AY22 [get_ports {P1[11]}]
+set_property PACKAGE_PIN BA22 [get_ports {P1[12]}]
+set_property PACKAGE_PIN AT22 [get_ports {P1[13]}]
+set_property PACKAGE_PIN AT23 [get_ports {P1[14]}]
+set_property PACKAGE_PIN AR25 [get_ports {P1[15]}]
+set_property PACKAGE_PIN AY27 [get_ports {P1[1]}]
+set_property PACKAGE_PIN AW23 [get_ports {P1[2]}]
+set_property PACKAGE_PIN AY23 [get_ports {P1[3]}]
+set_property PACKAGE_PIN AW25 [get_ports {P1[4]}]
+set_property PACKAGE_PIN BB21 [get_ports {P1[5]}]
+set_property PACKAGE_PIN BB22 [get_ports {P1[6]}]
+set_property PACKAGE_PIN BA23 [get_ports {P1[7]}]
+set_property PACKAGE_PIN BA24 [get_ports {P1[8]}]
+set_property PACKAGE_PIN AW21 [get_ports {P1[9]}]
+set_property PACKAGE_PIN AW24 [get_ports SWCLKTCK]
+set_property PACKAGE_PIN AU22 [get_ports SWDIOTMS]
+set_property PACKAGE_PIN AV23 [get_ports VDD]
+set_property PACKAGE_PIN AT24 [get_ports VDDIO]
+set_property PACKAGE_PIN AT25 [get_ports VSS]
+set_property PACKAGE_PIN AV21 [get_ports VSSIO]
+set_property PACKAGE_PIN AY25 [get_ports XTAL1]
+set_property PACKAGE_PIN AV22 [get_ports XTAL2]
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_arm_mps3/fpga_synth.tcl b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_arm_mps3/fpga_synth.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..4b89d747c16fc5a7319b9e0a8f1e0f48df0fafd8
--- /dev/null
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_arm_mps3/fpga_synth.tcl
@@ -0,0 +1 @@
+synth_design -top cmsdk_mcu_chip -part xcku115-flvb1760-1-c
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_arm_mps3/fpga_timing.xdc b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_arm_mps3/fpga_timing.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..78ac5e66193d3180e0df08f400cc924f8f74e8be
--- /dev/null
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_arm_mps3/fpga_timing.xdc
@@ -0,0 +1,99 @@
+##################################################################################
+##                                                                              ##
+## Arm MPS3 Rev-C timing XDC                                                    ##
+##                                                                              ##
+##################################################################################
+
+create_clock -name CLK -period 30 [get_ports XTAL1]
+create_clock -name VCLK -period 30 -waveform {5 20}
+
+create_clock -name SWCLK -period 60 [get_ports SWCLKTCK]
+create_clock -name VSWCLK -period 60 -waveform {5 35}
+
+set_clock_groups -name async_clk_swclock -asynchronous \
+-group [get_clocks -include_generated_clocks CLK] \
+-group [get_clocks -include_generated_clocks SWCLK]
+
+set_input_delay -clock [get_clocks oscclk_0] -min -add_delay 2.800 [get_ports {USER_SW[*]}]
+set_input_delay -clock [get_clocks oscclk_0] -max -add_delay 5.800 [get_ports {USER_SW[*]}]
+set_input_delay -clock [get_clocks oscclk_0] -min -add_delay 2.800 [get_ports {USER_nPB[*]}]
+set_input_delay -clock [get_clocks oscclk_0] -max -add_delay 5.800 [get_ports {USER_nPB[*]}]
+set_input_delay -clock [get_clocks oscclk_0] -min -add_delay 2.800 [get_ports CB_nPOR]
+set_input_delay -clock [get_clocks oscclk_0] -max -add_delay 5.800 [get_ports CB_nPOR]
+set_output_delay -clock [get_clocks oscclk_0] -min -add_delay -1.200 [get_ports {USER_nLED[*]}]
+set_output_delay -clock [get_clocks oscclk_0] -max -add_delay 5.800 [get_ports {USER_nLED[*]}]
+
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports {dip_switch_4bits_tri_i[*]}]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports {dip_switch_4bits_tri_i[*]}]
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_2]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports PMOD0_2]
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_3]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports PMOD0_3]
+#set_output_delay -clock [get_clocks clk_pl_0] -min -add_delay 5.000 [get_ports {led_4bits_tri_o[*]}]
+#set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {led_4bits_tri_o[*]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[0]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[0]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[1]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[1]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[2]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[2]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[3]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[3]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[4]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[4]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[5]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[5]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[6]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[6]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[7]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[7]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[8]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[8]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[9]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[9]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[10]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[10]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P011]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[11]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[12]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[12]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P013]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[13]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[14]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[14]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P015]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[15]} ]
+
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[0]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[0]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[1]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[1]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[2]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[2]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[3]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[3]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[4]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[4]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[5]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[5]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[6]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[6]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[7]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[7]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[8]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[8]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[9]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[9]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[10]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[10]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P111]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[11]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[12]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[12]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P113]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[13]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[14]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[14]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P115]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[15]} ]
+
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_pynq_z2/fpga_pinmap.xdc b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_pynq_z2/fpga_pinmap.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..2f049a711a99e45b953e8708b31ce3c50688f720
--- /dev/null
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_pynq_z2/fpga_pinmap.xdc
@@ -0,0 +1,228 @@
+##################################################################################
+##                                                                              ##
+## TUL pynq_z2 XDC                                                              ##
+##                                                                              ##
+##################################################################################
+
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_0]
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_1]
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_2]
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_3]
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_4]
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_5]
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_6]
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_7]
+#set_property PACKAGE_PIN Y18 [get_ports PMOD0_0]
+#set_property PACKAGE_PIN Y19 [get_ports PMOD0_1]
+#set_property PACKAGE_PIN Y16 [get_ports PMOD0_2]
+#set_property PACKAGE_PIN Y17 [get_ports PMOD0_3]
+#set_property PACKAGE_PIN U18 [get_ports PMOD0_4]
+#set_property PACKAGE_PIN U19 [get_ports PMOD0_5]
+#set_property PACKAGE_PIN W18 [get_ports PMOD0_6]
+#set_property PACKAGE_PIN W19 [get_ports PMOD0_7]
+#set_property PULLUP true [get_ports PMOD0_2]
+#set_property PULLUP true [get_ports PMOD0_3]
+#set_property PULLUP true [get_ports PMOD0_4]
+#set_property PULLUP true [get_ports PMOD0_5]
+#set_property PULLUP true [get_ports PMOD0_6]
+#set_property PULLUP true [get_ports PMOD0_7]
+
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_0]
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_1]
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_2]
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_3]
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_4]
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_5]
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_6]
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_7]
+
+#PMODA pin0 : FTCLK
+#set_property PACKAGE_PIN J9  [get_ports PMOD1_0]
+#PMODA pin1 : FTSSN
+#set_property PACKAGE_PIN K9  [get_ports PMOD1_1]
+#PMODA pin2 : FTMISO
+#set_property PACKAGE_PIN K8  [get_ports PMOD1_2]
+#PMODA pin3 : FTMIOSIO
+#set_property PACKAGE_PIN L8  [get_ports PMOD1_3]
+#PMODA pin4 : UART2RXD
+#set_property PACKAGE_PIN L10 [get_ports PMOD1_4]
+#PMODA pin4 : UART2TXD
+#set_property PACKAGE_PIN M10 [get_ports PMOD1_5]
+#set_property PACKAGE_PIN M8  [get_ports PMOD1_6]
+#set_property PACKAGE_PIN M9  [get_ports PMOD1_7]
+
+#set_property PULLUP true [get_ports PMOD1_7]
+#set_property PULLUP true [get_ports PMOD1_6]
+#set_property PULLUP true [get_ports PMOD1_5]
+#set_property PULLUP true [get_ports PMOD1_4]
+#set_property PULLUP true [get_ports PMOD1_3]
+#set_property PULLUP true [get_ports PMOD1_2]
+#set_property PULLUP true [get_ports PMOD1_1]
+#set_property PULLUP true [get_ports PMOD1_0]
+
+set_property IOSTANDARD LVCMOS33 [get_ports XTAL1]
+set_property IOSTANDARD LVCMOS33 [get_ports XTAL2]
+set_property IOSTANDARD LVCMOS33 [get_ports NRST]
+set_property IOSTANDARD LVCMOS33 [get_ports SWCLKTCK]
+set_property IOSTANDARD LVCMOS33 [get_ports SWDIOTMS]
+
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[0]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[1]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[2]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[3]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[4]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[5]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[6]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[7]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[8]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[9]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[10]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[11]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[12]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[13]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[14]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[15]} ]
+
+set_property PULLUP true [get_ports {P0[0]} ]
+set_property PULLUP true [get_ports {P0[1]} ]
+set_property PULLUP true [get_ports {P0[2]} ]
+set_property PULLUP true [get_ports {P0[3]} ]
+set_property PULLUP true [get_ports {P0[4]} ]
+set_property PULLUP true [get_ports {P0[5]} ]
+set_property PULLUP true [get_ports {P0[6]} ]
+set_property PULLUP true [get_ports {P0[7]} ]
+set_property PULLUP true [get_ports {P0[8]} ]
+set_property PULLUP true [get_ports {P0[9]} ]
+set_property PULLUP true [get_ports {P0[10]} ]
+set_property PULLUP true [get_ports {P0[11]} ]
+set_property PULLUP true [get_ports {P0[12]} ]
+set_property PULLUP true [get_ports {P0[13]} ]
+set_property PULLUP true [get_ports {P0[14]} ]
+set_property PULLUP true [get_ports {P0[15]} ]
+
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[0]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[1]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[2]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[3]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[4]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[5]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[6]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[7]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[8]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[9]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[10]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[11]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[12]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[13]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[14]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[15]} ]
+
+set_property PULLUP true [get_ports {P1[0]} ]
+set_property PULLUP true [get_ports {P1[1]} ]
+set_property PULLUP true [get_ports {P1[2]} ]
+set_property PULLUP true [get_ports {P1[3]} ]
+set_property PULLUP true [get_ports {P1[4]} ]
+set_property PULLUP true [get_ports {P1[5]} ]
+set_property PULLUP true [get_ports {P1[6]} ]
+set_property PULLUP true [get_ports {P1[7]} ]
+set_property PULLUP true [get_ports {P1[8]} ]
+set_property PULLUP true [get_ports {P1[9]} ]
+set_property PULLUP true [get_ports {P1[10]} ]
+set_property PULLUP true [get_ports {P1[11]} ]
+set_property PULLUP true [get_ports {P1[12]} ]
+set_property PULLUP true [get_ports {P1[13]} ]
+set_property PULLUP true [get_ports {P1[14]} ]
+set_property PULLUP true [get_ports {P1[15]} ]
+
+
+### PMODA ###
+#set_property PACKAGE_PIN Y18 [get_ports PMOD0_0]
+#set_property PACKAGE_PIN Y19 [get_ports PMOD0_1]
+#set_property PACKAGE_PIN Y16 [get_ports PMOD0_2]
+#set_property PACKAGE_PIN Y17 [get_ports PMOD0_3]
+#set_property PACKAGE_PIN U18 [get_ports PMOD0_4]
+#set_property PACKAGE_PIN U19 [get_ports PMOD0_5]
+#set_property PACKAGE_PIN W18 [get_ports PMOD0_6]
+#set_property PACKAGE_PIN W19 [get_ports PMOD0_7]
+
+## low row, PMOD-FT1248
+#PMODAL pin1 to FTMISO
+set_property PACKAGE_PIN Y18 [get_ports {P1[0]}]
+#PMODAL pin2 to FTCLK
+set_property PACKAGE_PIN Y19 [get_ports {P1[1]}]
+#PMODAL pin3 to FTMIOSIO
+set_property PACKAGE_PIN Y16 [get_ports {P1[2]}]
+#PMODAL pin4 to FTSSN
+set_property PACKAGE_PIN Y17 [get_ports {P1[3]}]
+
+## upper row, AUP-SWD
+#PMODAU pin1 to SWDIO
+set_property PACKAGE_PIN U18 [get_ports SWDIOTMS]
+#PMODAU pin2 to CLK15MHz
+##set_property PACKAGE_PIN U19 [get_ports XTAL1]
+#PMODAU pin3 to CLK30MHz
+set_property PACKAGE_PIN W18 [get_ports XTAL1]
+#PMODAU pin1 to SWDIO
+set_property PACKAGE_PIN W19 [get_ports SWCLKTCK]
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets uPAD_XTAL_I/IOBUF3V3/O]
+
+set_property PULLDOWN [get_ports SWDIOTMS]
+set_property PULLDOWN [get_ports SWDIOTCK]
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets uPAD_SWDCLK_I/IOBUF3V3/O]
+
+### PMODB ###
+
+#set_property PACKAGE_PIN L10 [get_ports PMOD1_4]
+#set_property PACKAGE_PIN M10 [get_ports PMOD1_5]
+#set_property PACKAGE_PIN M8  [get_ports PMOD1_6]
+#set_property PACKAGE_PIN M9  [get_ports PMOD1_7]
+
+#PMODA pin4 : UART2RXD
+#PMODA pin4 : UART2TXD
+
+
+# LED0 to P0[0]
+set_property PACKAGE_PIN R14 [get_ports {P0[0]}]
+# LED1 to P0[1]
+set_property PACKAGE_PIN P14 [get_ports {P0[1]}]
+# LED2 to P0[2]
+set_property PACKAGE_PIN N16 [get_ports {P0[2]}]
+# LED3 to P0[3]
+set_property PACKAGE_PIN M14 [get_ports {P0[3]}]
+
+# SW0 to NRST (Down for active low)
+set_property PACKAGE_PIN M20 [get_ports NRST]
+
+# CLK125MHz (need dvider)
+##set_property PACKAGE_PIN H16 [get_ports XTAL1]
+
+## Vivado allocations
+set_property PACKAGE_PIN V17 [get_ports {P0[10]}]
+set_property PACKAGE_PIN R18 [get_ports {P0[11]}]
+set_property PACKAGE_PIN T17 [get_ports {P0[12]}]
+set_property PACKAGE_PIN R17 [get_ports {P0[13]}]
+set_property PACKAGE_PIN R16 [get_ports {P0[14]}]
+set_property PACKAGE_PIN W16 [get_ports {P0[15]}]
+set_property PACKAGE_PIN T19 [get_ports {P0[4]}]
+set_property PACKAGE_PIN P16 [get_ports {P0[5]}]
+set_property PACKAGE_PIN P15 [get_ports {P0[6]}]
+set_property PACKAGE_PIN P18 [get_ports {P0[7]}]
+set_property PACKAGE_PIN N17 [get_ports {P0[8]}]
+set_property PACKAGE_PIN V18 [get_ports {P0[9]}]
+set_property PACKAGE_PIN N20 [get_ports {P1[10]}]
+set_property PACKAGE_PIN P19 [get_ports {P1[11]}]
+set_property PACKAGE_PIN N18 [get_ports {P1[12]}]
+set_property PACKAGE_PIN U19 [get_ports {P1[13]}]
+set_property PACKAGE_PIN U15 [get_ports {P1[14]}]
+set_property PACKAGE_PIN U14 [get_ports {P1[15]}]
+set_property PACKAGE_PIN V16 [get_ports {P1[4]}]
+set_property PACKAGE_PIN W20 [get_ports {P1[5]}]
+set_property PACKAGE_PIN V20 [get_ports {P1[6]}]
+set_property PACKAGE_PIN U20 [get_ports {P1[7]}]
+set_property PACKAGE_PIN T20 [get_ports {P1[8]}]
+set_property PACKAGE_PIN P20 [get_ports {P1[9]}]
+set_property PACKAGE_PIN W15 [get_ports VDD]
+set_property PACKAGE_PIN V15 [get_ports VDDIO]
+set_property PACKAGE_PIN U17 [get_ports VSS]
+set_property PACKAGE_PIN T16 [get_ports VSSIO]
+set_property PACKAGE_PIN Y14 [get_ports XTAL2]
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_pynq_z2/fpga_synth.tcl b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_pynq_z2/fpga_synth.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..1a9e44eff2f8e3cc3a24a1c5e1da88ae70f62c90
--- /dev/null
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_pynq_z2/fpga_synth.tcl
@@ -0,0 +1 @@
+synth_design -top cmsdk_mcu_chip -part xc7z020clg400-1
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_pynq_z2/fpga_timing.xdc b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_pynq_z2/fpga_timing.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..879aaadbadf756cabae24bf0f3f919d9951a8e5d
--- /dev/null
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_pynq_z2/fpga_timing.xdc
@@ -0,0 +1,95 @@
+##################################################################################
+##                                                                              ##
+## ZYNQ timing XDC                                                              ##
+##                                                                              ##
+##################################################################################
+
+create_clock -name CLK -period 30 [get_ports XTAL1]
+create_clock -name VCLK -period 30 -waveform {5 20}
+
+create_clock -name SWCLK -period 60 [get_ports SWCLKTCK]
+create_clock -name VSWCLK -period 60 -waveform {5 35}
+
+set_clock_groups -name async_clk_swclock -asynchronous \
+-group [get_clocks -include_generated_clocks CLK] \
+-group [get_clocks -include_generated_clocks VSWCLK]
+
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports {dip_switch_4bits_tri_i[*]}]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 18.000 [get_ports {dip_switch_4bits_tri_i[*]}]
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_2]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 18.000 [get_ports PMOD0_2]
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_3]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 18.000 [get_ports PMOD0_3]
+#set_output_delay -clock [get_clocks clk_pl_0] -min -add_delay 5.000 [get_ports {led_4bits_tri_o[*]}]
+#set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {led_4bits_tri_o[*]}]
+
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P0[0]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[0]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P0[1]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[1]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P0[2]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[2]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P0[3]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[3]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P0[4]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[4]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P0[5]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[5]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P0[6]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[6]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P0[7]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[7]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P0[8]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[8]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P0[9]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[9]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P0[10]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[10]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P0[11]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[11]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P0[12]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[12]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P0[13]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[13]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P0[14]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[14]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P0[15]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[15]}]
+
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P1[0]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[0]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P1[1]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[1]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P1[2]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[2]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P1[3]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[3]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P1[4]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[4]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P1[5]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[5]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P1[6]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[6]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P1[7]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[7]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P1[8]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[8]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P1[9]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[9]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P1[10]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[10]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P1[11]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[11]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P1[12]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[12]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P1[13]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[13]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P1[14]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[14]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P1[15]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[15]}]
+
+#set_property C_CLK_INPUT_FREQ_HZ 5000000 [get_debug_cores dbg_hub]
+#set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+#set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+#connect_debug_port dbg_hub/clk [get_nets clk]
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_zcu104/fpga_pinmap.xdc b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_zcu104/fpga_pinmap.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..293b3a8ce410dc3dafc51457ccc084caf3779e42
--- /dev/null
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_zcu104/fpga_pinmap.xdc
@@ -0,0 +1,1077 @@
+##################################################################################
+##                                                                              ##
+## ZCU104 Rev1.0 Master XDC                                                     ##
+##                                                                              ##
+##################################################################################
+
+#Other net   PACKAGE_PIN V17      - SYSMON_DXN                Bank   0 - DXN
+#Other net   PACKAGE_PIN V18      - SYSMON_DXP                Bank   0 - DXP
+#Other net   PACKAGE_PIN R17      - SYSMON_AGND               Bank   0 - GNDADC
+#Other net   PACKAGE_PIN AA12     - 3N5824                    Bank   0 - POR_OVERRIDE
+#Other net   PACKAGE_PIN AA13     - 3N5822                    Bank   0 - PUDC_B
+#Other net   PACKAGE_PIN R18      - FPGA_SYSMON_AVCC          Bank   0 - VCCADC
+#Other net   PACKAGE_PIN U17      - SYSMON_VN_R               Bank   0 - VN
+#Other net   PACKAGE_PIN T18      - SYSMON_VP_R               Bank   0 - VP
+#Other net   PACKAGE_PIN T17      - SYSMON_AGND               Bank   0 - VREFN
+#Other net   PACKAGE_PIN U18      - SYSMON_AGND               Bank   0 - VREFP
+#set_property PACKAGE_PIN B21      [get_ports "5N7582"] ;# Bank  28 VCCO - VCC1V8   - IO_L24N_T3U_N11_28
+#set_property IOSTANDARD  LVCMOSxx [get_ports "5N7582"] ;# Bank  28 VCCO - VCC1V8   - IO_L24N_T3U_N11_28
+#set_property PACKAGE_PIN B20      [get_ports "5N7577"] ;# Bank  28 VCCO - VCC1V8   - IO_L24P_T3U_N10_28
+#set_property IOSTANDARD  LVCMOSxx [get_ports "5N7577"] ;# Bank  28 VCCO - VCC1V8   - IO_L24P_T3U_N10_28
+#set_property PACKAGE_PIN A23      [get_ports "5N7578"] ;# Bank  28 VCCO - VCC1V8   - IO_L23N_T3U_N9_28
+#set_property IOSTANDARD  LVCMOSxx [get_ports "5N7578"] ;# Bank  28 VCCO - VCC1V8   - IO_L23N_T3U_N9_28
+#set_property PACKAGE_PIN A22      [get_ports "5N7569"] ;# Bank  28 VCCO - VCC1V8   - IO_L23P_T3U_N8_28
+#set_property IOSTANDARD  LVCMOSxx [get_ports "5N7569"] ;# Bank  28 VCCO - VCC1V8   - IO_L23P_T3U_N8_28
+#set_property PACKAGE_PIN B19      [get_ports "5N7570"] ;# Bank  28 VCCO - VCC1V8   - IO_L22N_T3U_N7_DBC_AD0N_28
+#set_property IOSTANDARD  LVCMOSxx [get_ports "5N7570"] ;# Bank  28 VCCO - VCC1V8   - IO_L22N_T3U_N7_DBC_AD0N_28
+#set_property PACKAGE_PIN B18      [get_ports "5N7565"] ;# Bank  28 VCCO - VCC1V8   - IO_L22P_T3U_N6_DBC_AD0P_28
+#set_property IOSTANDARD  LVCMOSxx [get_ports "5N7565"] ;# Bank  28 VCCO - VCC1V8   - IO_L22P_T3U_N6_DBC_AD0P_28
+#set_property PACKAGE_PIN A21      [get_ports "5N7709"] ;# Bank  28 VCCO - VCC1V8   - IO_L21N_T3L_N5_AD8N_28
+#set_property IOSTANDARD  LVCMOSxx [get_ports "5N7709"] ;# Bank  28 VCCO - VCC1V8   - IO_L21N_T3L_N5_AD8N_28
+#set_property PACKAGE_PIN A18      [get_ports "5N7704"] ;# Bank  28 VCCO - VCC1V8   - IO_L19P_T3L_N0_DBC_AD9P_28
+#set_property IOSTANDARD  LVCMOSxx [get_ports "5N7704"] ;# Bank  28 VCCO - VCC1V8   - IO_L19P_T3L_N0_DBC_AD9P_28
+#set_property PACKAGE_PIN B23      [get_ports "5N7581"] ;# Bank  28 VCCO - VCC1V8   - IO_T3U_N12_28
+#set_property IOSTANDARD  LVCMOSxx [get_ports "5N7581"] ;# Bank  28 VCCO - VCC1V8   - IO_T3U_N12_28
+#set_property PACKAGE_PIN F25      [get_ports "5N7703"] ;# Bank  28 VCCO - VCC1V8   - IO_T2U_N12_28
+#set_property IOSTANDARD  LVCMOSxx [get_ports "5N7703"] ;# Bank  28 VCCO - VCC1V8   - IO_T2U_N12_28
+#set_property PACKAGE_PIN G26      [get_ports "5N7702"] ;# Bank  28 VCCO - VCC1V8   - IO_L18N_T2U_N11_AD2N_28
+#set_property IOSTANDARD  LVCMOSxx [get_ports "5N7702"] ;# Bank  28 VCCO - VCC1V8   - IO_L18N_T2U_N11_AD2N_28
+#set_property PACKAGE_PIN G25      [get_ports "5N7694"] ;# Bank  28 VCCO - VCC1V8   - IO_L18P_T2U_N10_AD2P_28
+#set_property IOSTANDARD  LVCMOSxx [get_ports "5N7694"] ;# Bank  28 VCCO - VCC1V8   - IO_L18P_T2U_N10_AD2P_28
+#set_property PACKAGE_PIN C23      [get_ports "5N7693"] ;# Bank  28 VCCO - VCC1V8   - IO_L17N_T2U_N9_AD10N_28
+#set_property IOSTANDARD  LVCMOSxx [get_ports "5N7693"] ;# Bank  28 VCCO - VCC1V8   - IO_L17N_T2U_N9_AD10N_28
+#set_property PACKAGE_PIN D22      [get_ports "5N7690"] ;# Bank  28 VCCO - VCC1V8   - IO_L17P_T2U_N8_AD10P_28
+#set_property IOSTANDARD  LVCMOSxx [get_ports "5N7690"] ;# Bank  28 VCCO - VCC1V8   - IO_L17P_T2U_N8_AD10P_28
+#set_property PACKAGE_PIN D24      [get_ports "5N7688"] ;# Bank  28 VCCO - VCC1V8   - IO_L16N_T2U_N7_QBC_AD3N_28
+#set_property IOSTANDARD  LVCMOSxx [get_ports "5N7688"] ;# Bank  28 VCCO - VCC1V8   - IO_L16N_T2U_N7_QBC_AD3N_28
+#set_property PACKAGE_PIN E24      [get_ports "5N7682"] ;# Bank  28 VCCO - VCC1V8   - IO_L16P_T2U_N6_QBC_AD3P_28
+#set_property IOSTANDARD  LVCMOSxx [get_ports "5N7682"] ;# Bank  28 VCCO - VCC1V8   - IO_L16P_T2U_N6_QBC_AD3P_28
+#set_property PACKAGE_PIN C22      [get_ports "5N7681"] ;# Bank  28 VCCO - VCC1V8   - IO_L15N_T2L_N5_AD11N_28
+#set_property IOSTANDARD  LVCMOSxx [get_ports "5N7681"] ;# Bank  28 VCCO - VCC1V8   - IO_L15N_T2L_N5_AD11N_28
+#set_property PACKAGE_PIN C21      [get_ports "5N7678"] ;# Bank  28 VCCO - VCC1V8   - IO_L15P_T2L_N4_AD11P_28
+#set_property IOSTANDARD  LVCMOSxx [get_ports "5N7678"] ;# Bank  28 VCCO - VCC1V8   - IO_L15P_T2L_N4_AD11P_28
+#set_property PACKAGE_PIN G24      [get_ports "5N7676"] ;# Bank  28 VCCO - VCC1V8   - IO_L14N_T2L_N3_GC_28
+#set_property IOSTANDARD  LVCMOSxx [get_ports "5N7676"] ;# Bank  28 VCCO - VCC1V8   - IO_L14N_T2L_N3_GC_28
+#set_property PACKAGE_PIN G23      [get_ports "5N7672"] ;# Bank  28 VCCO - VCC1V8   - IO_L14P_T2L_N2_GC_28
+#set_property IOSTANDARD  LVCMOSxx [get_ports "5N7672"] ;# Bank  28 VCCO - VCC1V8   - IO_L14P_T2L_N2_GC_28
+#set_property PACKAGE_PIN F20      [get_ports "5N7532"] ;# Bank  28 VCCO - VCC1V8   - IO_L10N_T1U_N7_QBC_AD4N_28
+#set_property IOSTANDARD  LVCMOSxx [get_ports "5N7532"] ;# Bank  28 VCCO - VCC1V8   - IO_L10N_T1U_N7_QBC_AD4N_28
+#set_property PACKAGE_PIN G20      [get_ports "5N7533"] ;# Bank  28 VCCO - VCC1V8   - IO_L10P_T1U_N6_QBC_AD4P_28
+#set_property IOSTANDARD  LVCMOSxx [get_ports "5N7533"] ;# Bank  28 VCCO - VCC1V8   - IO_L10P_T1U_N6_QBC_AD4P_28
+#set_property PACKAGE_PIN D21      [get_ports "5N7524"] ;# Bank  28 VCCO - VCC1V8   - IO_L9N_T1L_N5_AD12N_28
+#set_property IOSTANDARD  LVCMOSxx [get_ports "5N7524"] ;# Bank  28 VCCO - VCC1V8   - IO_L9N_T1L_N5_AD12N_28
+#set_property PACKAGE_PIN D20      [get_ports "5N7525"] ;# Bank  28 VCCO - VCC1V8   - IO_L9P_T1L_N4_AD12P_28
+#set_property IOSTANDARD  LVCMOSxx [get_ports "5N7525"] ;# Bank  28 VCCO - VCC1V8   - IO_L9P_T1L_N4_AD12P_28
+#set_property PACKAGE_PIN H22      [get_ports "5N7520"] ;# Bank  28 VCCO - VCC1V8   - IO_L8N_T1L_N3_AD5N_28
+#set_property IOSTANDARD  LVCMOSxx [get_ports "5N7520"] ;# Bank  28 VCCO - VCC1V8   - IO_L8N_T1L_N3_AD5N_28
+#set_property PACKAGE_PIN H21      [get_ports "5N7521"] ;# Bank  28 VCCO - VCC1V8   - IO_L8P_T1L_N2_AD5P_28
+#set_property IOSTANDARD  LVCMOSxx [get_ports "5N7521"] ;# Bank  28 VCCO - VCC1V8   - IO_L8P_T1L_N2_AD5P_28
+#set_property PACKAGE_PIN D19      [get_ports "5N7512"] ;# Bank  28 VCCO - VCC1V8   - IO_L7N_T1L_N1_QBC_AD13N_28
+#set_property IOSTANDARD  LVCMOSxx [get_ports "5N7512"] ;# Bank  28 VCCO - VCC1V8   - IO_L7N_T1L_N1_QBC_AD13N_28
+#set_property PACKAGE_PIN E19      [get_ports "5N7513"] ;# Bank  28 VCCO - VCC1V8   - IO_L7P_T1L_N0_QBC_AD13P_28
+#set_property IOSTANDARD  LVCMOSxx [get_ports "5N7513"] ;# Bank  28 VCCO - VCC1V8   - IO_L7P_T1L_N0_QBC_AD13P_28
+#set_property PACKAGE_PIN E20      [get_ports "5N7726"] ;# Bank  28 VCCO - VCC1V8   - IO_T1U_N12_28
+#set_property IOSTANDARD  LVCMOSxx [get_ports "5N7726"] ;# Bank  28 VCCO - VCC1V8   - IO_T1U_N12_28
+#set_property PACKAGE_PIN H23      [get_ports "5N7508"] ;# Bank  28 VCCO - VCC1V8   - IO_T0U_N12_VRP_28
+#set_property IOSTANDARD  LVCMOSxx [get_ports "5N7508"] ;# Bank  28 VCCO - VCC1V8   - IO_T0U_N12_VRP_28
+#set_property PACKAGE_PIN H24      [get_ports "5N7509"] ;# Bank  28 VCCO - VCC1V8   - IO_L6N_T0U_N11_AD6N_28
+#set_property IOSTANDARD  LVCMOSxx [get_ports "5N7509"] ;# Bank  28 VCCO - VCC1V8   - IO_L6N_T0U_N11_AD6N_28
+#set_property PACKAGE_PIN J24      [get_ports "5N7500"] ;# Bank  28 VCCO - VCC1V8   - IO_L6P_T0U_N10_AD6P_28
+#set_property IOSTANDARD  LVCMOSxx [get_ports "5N7500"] ;# Bank  28 VCCO - VCC1V8   - IO_L6P_T0U_N10_AD6P_28
+#set_property PACKAGE_PIN H26      [get_ports "5N7501"] ;# Bank  28 VCCO - VCC1V8   - IO_L5N_T0U_N9_AD14N_28
+#set_property IOSTANDARD  LVCMOSxx [get_ports "5N7501"] ;# Bank  28 VCCO - VCC1V8   - IO_L5N_T0U_N9_AD14N_28
+#set_property PACKAGE_PIN J25      [get_ports "5N7496"] ;# Bank  28 VCCO - VCC1V8   - IO_L5P_T0U_N8_AD14P_28
+#set_property IOSTANDARD  LVCMOSxx [get_ports "5N7496"] ;# Bank  28 VCCO - VCC1V8   - IO_L5P_T0U_N8_AD14P_28
+#set_property PACKAGE_PIN K23      [get_ports "5N7497"] ;# Bank  28 VCCO - VCC1V8   - IO_L4N_T0U_N7_DBC_AD7N_28
+#set_property IOSTANDARD  LVCMOSxx [get_ports "5N7497"] ;# Bank  28 VCCO - VCC1V8   - IO_L4N_T0U_N7_DBC_AD7N_28
+#set_property PACKAGE_PIN K22      [get_ports "5N7488"] ;# Bank  28 VCCO - VCC1V8   - IO_L4P_T0U_N6_DBC_AD7P_28
+#set_property IOSTANDARD  LVCMOSxx [get_ports "5N7488"] ;# Bank  28 VCCO - VCC1V8   - IO_L4P_T0U_N6_DBC_AD7P_28
+#set_property PACKAGE_PIN J22      [get_ports "5N7489"] ;# Bank  28 VCCO - VCC1V8   - IO_L3N_T0L_N5_AD15N_28
+#set_property IOSTANDARD  LVCMOSxx [get_ports "5N7489"] ;# Bank  28 VCCO - VCC1V8   - IO_L3N_T0L_N5_AD15N_28
+#set_property PACKAGE_PIN J21      [get_ports "5N7484"] ;# Bank  28 VCCO - VCC1V8   - IO_L3P_T0L_N4_AD15P_28
+#set_property IOSTANDARD  LVCMOSxx [get_ports "5N7484"] ;# Bank  28 VCCO - VCC1V8   - IO_L3P_T0L_N4_AD15P_28
+#set_property PACKAGE_PIN K24      [get_ports "5N7485"] ;# Bank  28 VCCO - VCC1V8   - IO_L2N_T0L_N3_28
+#set_property IOSTANDARD  LVCMOSxx [get_ports "5N7485"] ;# Bank  28 VCCO - VCC1V8   - IO_L2N_T0L_N3_28
+#set_property PACKAGE_PIN L23      [get_ports "5N7476"] ;# Bank  28 VCCO - VCC1V8   - IO_L2P_T0L_N2_28
+#set_property IOSTANDARD  LVCMOSxx [get_ports "5N7476"] ;# Bank  28 VCCO - VCC1V8   - IO_L2P_T0L_N2_28
+#set_property PACKAGE_PIN L22      [get_ports "5N7477"] ;# Bank  28 VCCO - VCC1V8   - IO_L1N_T0L_N1_DBC_28
+#set_property IOSTANDARD  LVCMOSxx [get_ports "5N7477"] ;# Bank  28 VCCO - VCC1V8   - IO_L1N_T0L_N1_DBC_28
+#set_property PACKAGE_PIN L21      [get_ports "5N7472"] ;# Bank  28 VCCO - VCC1V8   - IO_L1P_T0L_N0_DBC_28
+#set_property IOSTANDARD  LVCMOSxx [get_ports "5N7472"] ;# Bank  28 VCCO - VCC1V8   - IO_L1P_T0L_N0_DBC_28
+#Other net   PACKAGE_PIN M23      - 5N7631                    Bank  28 - VREF_28
+#set_property PACKAGE_PIN A9       [get_ports "4N9784"] ;# Bank  68 VCCO - VADJ_FMC - IO_T3U_N12_68
+#set_property IOSTANDARD  LVCMOSxx [get_ports "4N9784"] ;# Bank  68 VCCO - VADJ_FMC - IO_T3U_N12_68
+#set_property PACKAGE_PIN G13      [get_ports "4N9781"] ;# Bank  68 VCCO - VADJ_FMC - IO_T2U_N12_68
+#set_property IOSTANDARD  LVCMOSxx [get_ports "4N9781"] ;# Bank  68 VCCO - VADJ_FMC - IO_T2U_N12_68
+#set_property PACKAGE_PIN G11      [get_ports "4N9820"] ;# Bank  68 VCCO - VADJ_FMC - IO_L13N_T2L_N1_GC_QBC_68
+#set_property IOSTANDARD  LVCMOSxx [get_ports "4N9820"] ;# Bank  68 VCCO - VADJ_FMC - IO_L13N_T2L_N1_GC_QBC_68
+#set_property PACKAGE_PIN H11      [get_ports "4N9817"] ;# Bank  68 VCCO - VADJ_FMC - IO_L13P_T2L_N0_GC_QBC_68
+#set_property IOSTANDARD  LVCMOSxx [get_ports "4N9817"] ;# Bank  68 VCCO - VADJ_FMC - IO_L13P_T2L_N0_GC_QBC_68
+#set_property PACKAGE_PIN G9       [get_ports "4N9823"] ;# Bank  68 VCCO - VADJ_FMC - IO_L11N_T1U_N9_GC_68
+#set_property IOSTANDARD  LVCMOSxx [get_ports "4N9823"] ;# Bank  68 VCCO - VADJ_FMC - IO_L11N_T1U_N9_GC_68
+#set_property PACKAGE_PIN H9       [get_ports "4N9826"] ;# Bank  68 VCCO - VADJ_FMC - IO_L11P_T1U_N8_GC_68
+#set_property IOSTANDARD  LVCMOSxx [get_ports "4N9826"] ;# Bank  68 VCCO - VADJ_FMC - IO_L11P_T1U_N8_GC_68
+#set_property PACKAGE_PIN D7       [get_ports "4N9778"] ;# Bank  68 VCCO - VADJ_FMC - IO_T1U_N12_68
+#set_property IOSTANDARD  LVCMOSxx [get_ports "4N9778"] ;# Bank  68 VCCO - VADJ_FMC - IO_T1U_N12_68
+#set_property PACKAGE_PIN H14      [get_ports "VRP_68"] ;# Bank  68 VCCO - VADJ_FMC - IO_T0U_N12_VRP_68
+#set_property IOSTANDARD  LVCMOSxx [get_ports "VRP_68"] ;# Bank  68 VCCO - VADJ_FMC - IO_T0U_N12_VRP_68
+#set_property PACKAGE_PIN K13      [get_ports "4N9759"] ;# Bank  68 VCCO - VADJ_FMC - IO_L6N_T0U_N11_AD6N_68
+#set_property IOSTANDARD  LVCMOSxx [get_ports "4N9759"] ;# Bank  68 VCCO - VADJ_FMC - IO_L6N_T0U_N11_AD6N_68
+#set_property PACKAGE_PIN L14      [get_ports "4N9760"] ;# Bank  68 VCCO - VADJ_FMC - IO_L6P_T0U_N10_AD6P_68
+#set_property IOSTANDARD  LVCMOSxx [get_ports "4N9760"] ;# Bank  68 VCCO - VADJ_FMC - IO_L6P_T0U_N10_AD6P_68
+#set_property PACKAGE_PIN J14      [get_ports "4N9755"] ;# Bank  68 VCCO - VADJ_FMC - IO_L5N_T0U_N9_AD14N_68
+#set_property IOSTANDARD  LVCMOSxx [get_ports "4N9755"] ;# Bank  68 VCCO - VADJ_FMC - IO_L5N_T0U_N9_AD14N_68
+#set_property PACKAGE_PIN K14      [get_ports "4N9756"] ;# Bank  68 VCCO - VADJ_FMC - IO_L5P_T0U_N8_AD14P_68
+#set_property IOSTANDARD  LVCMOSxx [get_ports "4N9756"] ;# Bank  68 VCCO - VADJ_FMC - IO_L5P_T0U_N8_AD14P_68
+#set_property PACKAGE_PIN J11      [get_ports "4N9771"] ;# Bank  68 VCCO - VADJ_FMC - IO_L4N_T0U_N7_DBC_AD7N_68
+#set_property IOSTANDARD  LVCMOSxx [get_ports "4N9771"] ;# Bank  68 VCCO - VADJ_FMC - IO_L4N_T0U_N7_DBC_AD7N_68
+#set_property PACKAGE_PIN K12      [get_ports "4N9772"] ;# Bank  68 VCCO - VADJ_FMC - IO_L4P_T0U_N6_DBC_AD7P_68
+#set_property IOSTANDARD  LVCMOSxx [get_ports "4N9772"] ;# Bank  68 VCCO - VADJ_FMC - IO_L4P_T0U_N6_DBC_AD7P_68
+#set_property PACKAGE_PIN L11      [get_ports "4N9767"] ;# Bank  68 VCCO - VADJ_FMC - IO_L3N_T0L_N5_AD15N_68
+#set_property IOSTANDARD  LVCMOSxx [get_ports "4N9767"] ;# Bank  68 VCCO - VADJ_FMC - IO_L3N_T0L_N5_AD15N_68
+#set_property PACKAGE_PIN L12      [get_ports "4N9768"] ;# Bank  68 VCCO - VADJ_FMC - IO_L3P_T0L_N4_AD15P_68
+#set_property IOSTANDARD  LVCMOSxx [get_ports "4N9768"] ;# Bank  68 VCCO - VADJ_FMC - IO_L3P_T0L_N4_AD15P_68
+#Other net   PACKAGE_PIN J12      - 4N9503                    Bank  68 - VREF_68
+#set_property PACKAGE_PIN J20      [get_ports "7N10213"] ;# Bank  67 VCCO - VADJ_FMC - IO_T3U_N12_67
+#set_property IOSTANDARD  LVCMOSxx [get_ports "7N10213"] ;# Bank  67 VCCO - VADJ_FMC - IO_T3U_N12_67
+#set_property PACKAGE_PIN J19      [get_ports "7N10210"] ;# Bank  67 VCCO - VADJ_FMC - IO_T2U_N12_67
+#set_property IOSTANDARD  LVCMOSxx [get_ports "7N10210"] ;# Bank  67 VCCO - VADJ_FMC - IO_T2U_N12_67
+#set_property PACKAGE_PIN G16      [get_ports "FMC_LPC_LA09_N"] ;# Bank  67 VCCO - VADJ_FMC - IO_L18N_T2U_N11_AD2N_67
+#set_property PACKAGE_PIN D14      [get_ports "7N10403"] ;# Bank  67 VCCO - VADJ_FMC - IO_L11N_T1U_N9_GC_67
+#set_property IOSTANDARD  LVCMOSxx [get_ports "7N10403"] ;# Bank  67 VCCO - VADJ_FMC - IO_L11N_T1U_N9_GC_67
+#set_property PACKAGE_PIN D15      [get_ports "7N10406"] ;# Bank  67 VCCO - VADJ_FMC - IO_L11P_T1U_N8_GC_67
+#set_property IOSTANDARD  LVCMOSxx [get_ports "7N10406"] ;# Bank  67 VCCO - VADJ_FMC - IO_L11P_T1U_N8_GC_67
+#set_property PACKAGE_PIN F13      [get_ports "7N10612"] ;# Bank  67 VCCO - VADJ_FMC - IO_L10N_T1U_N7_QBC_AD4N_67
+#set_property IOSTANDARD  LVCMOSxx [get_ports "7N10612"] ;# Bank  67 VCCO - VADJ_FMC - IO_L10N_T1U_N7_QBC_AD4N_67
+#set_property PACKAGE_PIN G14      [get_ports "7N10614"] ;# Bank  67 VCCO - VADJ_FMC - IO_L10P_T1U_N6_QBC_AD4P_67
+#set_property IOSTANDARD  LVCMOSxx [get_ports "7N10614"] ;# Bank  67 VCCO - VADJ_FMC - IO_L10P_T1U_N6_QBC_AD4P_67
+#set_property PACKAGE_PIN E13      [get_ports "7N10207"] ;# Bank  67 VCCO - VADJ_FMC - IO_T1U_N12_67
+#set_property IOSTANDARD  LVCMOSxx [get_ports "7N10207"] ;# Bank  67 VCCO - VADJ_FMC - IO_T1U_N12_67
+#set_property PACKAGE_PIN C14      [get_ports "7N10204"] ;# Bank  67 VCCO - VADJ_FMC - IO_T0U_N12_VRP_67
+#set_property IOSTANDARD  LVCMOSxx [get_ports "7N10204"] ;# Bank  67 VCCO - VADJ_FMC - IO_T0U_N12_VRP_67
+#set_property PACKAGE_PIN C12      [get_ports "FMC_LPC_LA14_N"] ;# Bank  67 VCCO - VADJ_FMC - IO_L6N_T0U_N11_AD6N_67
+#set_property PACKAGE_PIN B13      [get_ports "7N10197"] ;# Bank  67 VCCO - VADJ_FMC - IO_L4N_T0U_N7_DBC_AD7N_67
+#set_property IOSTANDARD  LVCMOSxx [get_ports "7N10197"] ;# Bank  67 VCCO - VADJ_FMC - IO_L4N_T0U_N7_DBC_AD7N_67
+#set_property PACKAGE_PIN B14      [get_ports "7N10198"] ;# Bank  67 VCCO - VADJ_FMC - IO_L4P_T0U_N6_DBC_AD7P_67
+#set_property IOSTANDARD  LVCMOSxx [get_ports "7N10198"] ;# Bank  67 VCCO - VADJ_FMC - IO_L4P_T0U_N6_DBC_AD7P_67
+#set_property PACKAGE_PIN A14      [get_ports "7N10193"] ;# Bank  67 VCCO - VADJ_FMC - IO_L3N_T0L_N5_AD15N_67
+#set_property IOSTANDARD  LVCMOSxx [get_ports "7N10193"] ;# Bank  67 VCCO - VADJ_FMC - IO_L3N_T0L_N5_AD15N_67
+#set_property PACKAGE_PIN A15      [get_ports "7N10194"] ;# Bank  67 VCCO - VADJ_FMC - IO_L3P_T0L_N4_AD15P_67
+#set_property IOSTANDARD  LVCMOSxx [get_ports "7N10194"] ;# Bank  67 VCCO - VADJ_FMC - IO_L3P_T0L_N4_AD15P_67
+#set_property PACKAGE_PIN B15      [get_ports "7N10185"] ;# Bank  67 VCCO - VADJ_FMC - IO_L2N_T0L_N3_67
+#set_property IOSTANDARD  LVCMOSxx [get_ports "7N10185"] ;# Bank  67 VCCO - VADJ_FMC - IO_L2N_T0L_N3_67
+#set_property PACKAGE_PIN B16      [get_ports "7N10186"] ;# Bank  67 VCCO - VADJ_FMC - IO_L2P_T0L_N2_67
+#set_property IOSTANDARD  LVCMOSxx [get_ports "7N10186"] ;# Bank  67 VCCO - VADJ_FMC - IO_L2P_T0L_N2_67
+#set_property PACKAGE_PIN A16      [get_ports "7N10181"] ;# Bank  67 VCCO - VADJ_FMC - IO_L1N_T0L_N1_DBC_67
+#set_property IOSTANDARD  LVCMOSxx [get_ports "7N10181"] ;# Bank  67 VCCO - VADJ_FMC - IO_L1N_T0L_N1_DBC_67
+#set_property PACKAGE_PIN A17      [get_ports "7N10182"] ;# Bank  67 VCCO - VADJ_FMC - IO_L1P_T0L_N0_DBC_67
+#set_property IOSTANDARD  LVCMOSxx [get_ports "7N10182"] ;# Bank  67 VCCO - VADJ_FMC - IO_L1P_T0L_N0_DBC_67
+#Other net   PACKAGE_PIN L18      - 7N9719                    Bank  67 - VREF_67
+#set_property PACKAGE_PIN AF10     [get_ports "7N10601"] ;# Bank  66 VCCO - VCC1V2   - IO_L19N_T3L_N1_DBC_AD9N_66
+#set_property IOSTANDARD  LVCMOSxx [get_ports "7N10601"] ;# Bank  66 VCCO - VCC1V2   - IO_L19N_T3L_N1_DBC_AD9N_66
+#set_property PACKAGE_PIN AC14     [get_ports "7N10603"] ;# Bank  66 VCCO - VCC1V2   - IO_T3U_N12_66
+#set_property IOSTANDARD  LVCMOSxx [get_ports "7N10603"] ;# Bank  66 VCCO - VCC1V2   - IO_T3U_N12_66
+#set_property PACKAGE_PIN AH8      [get_ports "7N10599"] ;# Bank  66 VCCO - VCC1V2   - IO_T2U_N12_66
+#set_property IOSTANDARD  LVCMOSxx [get_ports "7N10599"] ;# Bank  66 VCCO - VCC1V2   - IO_T2U_N12_66
+#set_property PACKAGE_PIN AJ12     [get_ports "7N10597"] ;# Bank  66 VCCO - VCC1V2   - IO_L13N_T2L_N1_GC_QBC_66
+#set_property IOSTANDARD  LVCMOSxx [get_ports "7N10597"] ;# Bank  66 VCCO - VCC1V2   - IO_L13N_T2L_N1_GC_QBC_66
+#set_property PACKAGE_PIN AL13     [get_ports "7N10593"] ;# Bank  66 VCCO - VCC1V2   - IO_L7N_T1L_N1_QBC_AD13N_66
+#set_property IOSTANDARD  LVCMOSxx [get_ports "7N10593"] ;# Bank  66 VCCO - VCC1V2   - IO_L7N_T1L_N1_QBC_AD13N_66
+#set_property PACKAGE_PIN AM13     [get_ports "7N10595"] ;# Bank  66 VCCO - VCC1V2   - IO_T1U_N12_66
+#set_property IOSTANDARD  LVCMOSxx [get_ports "7N10595"] ;# Bank  66 VCCO - VCC1V2   - IO_T1U_N12_66
+#set_property PACKAGE_PIN AP8      [get_ports "VRP_66"] ;# Bank  66 VCCO - VCC1V2   - IO_T0U_N12_VRP_66
+#set_property IOSTANDARD  LVCMOSxx [get_ports "VRP_66"] ;# Bank  66 VCCO - VCC1V2   - IO_T0U_N12_VRP_66
+#set_property PACKAGE_PIN AP12     [get_ports "7N10591"] ;# Bank  66 VCCO - VCC1V2   - IO_L1N_T0L_N1_DBC_66
+#set_property IOSTANDARD  LVCMOSxx [get_ports "7N10591"] ;# Bank  66 VCCO - VCC1V2   - IO_L1N_T0L_N1_DBC_66
+#Other net   PACKAGE_PIN AB12     - 7N8282                    Bank  66 - VREF_66
+#set_property PACKAGE_PIN AE19     [get_ports "6N12439"] ;# Bank  65 VCCO - VCC1V2   - IO_L19N_T3L_N1_DBC_AD9N_65
+#set_property IOSTANDARD  LVCMOSxx [get_ports "6N12439"] ;# Bank  65 VCCO - VCC1V2   - IO_L19N_T3L_N1_DBC_AD9N_65
+#set_property PACKAGE_PIN AE22     [get_ports "6N12442"] ;# Bank  65 VCCO - VCC1V2   - IO_T3U_N12_65
+#set_property IOSTANDARD  LVCMOSxx [get_ports "6N12442"] ;# Bank  65 VCCO - VCC1V2   - IO_T3U_N12_65
+#set_property PACKAGE_PIN AF20     [get_ports "6N12436"] ;# Bank  65 VCCO - VCC1V2   - IO_T2U_N12_65
+#set_property IOSTANDARD  LVCMOSxx [get_ports "6N12436"] ;# Bank  65 VCCO - VCC1V2   - IO_T2U_N12_65
+#set_property PACKAGE_PIN AH23     [get_ports "6N12433"] ;# Bank  65 VCCO - VCC1V2   - IO_L13N_T2L_N1_GC_QBC_65
+#set_property IOSTANDARD  LVCMOSxx [get_ports "6N12433"] ;# Bank  65 VCCO - VCC1V2   - IO_L13N_T2L_N1_GC_QBC_65
+#set_property PACKAGE_PIN AL21     [get_ports "6N12427"] ;# Bank  65 VCCO - VCC1V2   - IO_L7N_T1L_N1_QBC_AD13N_65
+#set_property IOSTANDARD  LVCMOSxx [get_ports "6N12427"] ;# Bank  65 VCCO - VCC1V2   - IO_L7N_T1L_N1_QBC_AD13N_65
+#set_property PACKAGE_PIN AH19     [get_ports "6N12430"] ;# Bank  65 VCCO - VCC1V2   - IO_T1U_N12_65
+#set_property IOSTANDARD  LVCMOSxx [get_ports "6N12430"] ;# Bank  65 VCCO - VCC1V2   - IO_T1U_N12_65
+#set_property PACKAGE_PIN AM20     [get_ports "VRP_65"] ;# Bank  65 VCCO - VCC1V2   - IO_T0U_N12_VRP_65
+#set_property IOSTANDARD  LVCMOSxx [get_ports "VRP_65"] ;# Bank  65 VCCO - VCC1V2   - IO_T0U_N12_VRP_65
+#set_property PACKAGE_PIN AP20     [get_ports "6N12401"] ;# Bank  65 VCCO - VCC1V2   - IO_L1N_T0L_N1_DBC_65
+#set_property IOSTANDARD  LVCMOSxx [get_ports "6N12401"] ;# Bank  65 VCCO - VCC1V2   - IO_L1N_T0L_N1_DBC_65
+#Other net   PACKAGE_PIN AB20     - 6N11582                   Bank  65 - VREF_65
+#set_property PACKAGE_PIN AA17     [get_ports "6N12707"] ;# Bank  64 VCCO - VCC1V2   - IO_T3U_N12_64
+#set_property IOSTANDARD  LVCMOSxx [get_ports "6N12707"] ;# Bank  64 VCCO - VCC1V2   - IO_T3U_N12_64
+#set_property PACKAGE_PIN AE17     [get_ports "6N12705"] ;# Bank  64 VCCO - VCC1V2   - IO_L15P_T2L_N4_AD11P_64
+#set_property IOSTANDARD  LVCMOSxx [get_ports "6N12705"] ;# Bank  64 VCCO - VCC1V2   - IO_L15P_T2L_N4_AD11P_64
+#set_property PACKAGE_PIN AP14     [get_ports "VRP_64"] ;# Bank  64 VCCO - VCC1V2   - IO_T0U_N12_VRP_64
+#set_property PACKAGE_PIN AP15     [get_ports "6N12788"] ;# Bank  64 VCCO - VCC1V2   - IO_L5N_T0U_N9_AD14N_64
+#set_property IOSTANDARD  LVCMOSxx [get_ports "6N12788"] ;# Bank  64 VCCO - VCC1V2   - IO_L5N_T0U_N9_AD14N_64
+#set_property PACKAGE_PIN AP16     [get_ports "6N12789"] ;# Bank  64 VCCO - VCC1V2   - IO_L5P_T0U_N8_AD14P_64
+#set_property IOSTANDARD  LVCMOSxx [get_ports "6N12789"] ;# Bank  64 VCCO - VCC1V2   - IO_L5P_T0U_N8_AD14P_64
+#set_property PACKAGE_PIN AN14     [get_ports "6N12782"] ;# Bank  64 VCCO - VCC1V2   - IO_L4N_T0U_N7_DBC_AD7N_64
+#set_property IOSTANDARD  LVCMOSxx [get_ports "6N12782"] ;# Bank  64 VCCO - VCC1V2   - IO_L4N_T0U_N7_DBC_AD7N_64
+#set_property PACKAGE_PIN AM14     [get_ports "6N12783"] ;# Bank  64 VCCO - VCC1V2   - IO_L4P_T0U_N6_DBC_AD7P_64
+#set_property IOSTANDARD  LVCMOSxx [get_ports "6N12783"] ;# Bank  64 VCCO - VCC1V2   - IO_L4P_T0U_N6_DBC_AD7P_64
+#set_property PACKAGE_PIN AN18     [get_ports "6N12780"] ;# Bank  64 VCCO - VCC1V2   - IO_L3N_T0L_N5_AD15N_64
+#set_property IOSTANDARD  LVCMOSxx [get_ports "6N12780"] ;# Bank  64 VCCO - VCC1V2   - IO_L3N_T0L_N5_AD15N_64
+#set_property PACKAGE_PIN AM18     [get_ports "6N12781"] ;# Bank  64 VCCO - VCC1V2   - IO_L3P_T0L_N4_AD15P_64
+#set_property IOSTANDARD  LVCMOSxx [get_ports "6N12781"] ;# Bank  64 VCCO - VCC1V2   - IO_L3P_T0L_N4_AD15P_64
+#set_property PACKAGE_PIN AP13     [get_ports "6N12774"] ;# Bank  64 VCCO - VCC1V2   - IO_L2N_T0L_N3_64
+#set_property IOSTANDARD  LVCMOSxx [get_ports "6N12774"] ;# Bank  64 VCCO - VCC1V2   - IO_L2N_T0L_N3_64
+#set_property PACKAGE_PIN AN13     [get_ports "6N12775"] ;# Bank  64 VCCO - VCC1V2   - IO_L2P_T0L_N2_64
+#set_property IOSTANDARD  LVCMOSxx [get_ports "6N12775"] ;# Bank  64 VCCO - VCC1V2   - IO_L2P_T0L_N2_64
+#set_property PACKAGE_PIN AP17     [get_ports "6N12772"] ;# Bank  64 VCCO - VCC1V2   - IO_L1N_T0L_N1_DBC_64
+#set_property IOSTANDARD  LVCMOSxx [get_ports "6N12772"] ;# Bank  64 VCCO - VCC1V2   - IO_L1N_T0L_N1_DBC_64
+#set_property PACKAGE_PIN AP18     [get_ports "6N12773"] ;# Bank  64 VCCO - VCC1V2   - IO_L1P_T0L_N0_DBC_64
+#set_property IOSTANDARD  LVCMOSxxn [get_ports "6N12773"] ;# Bank  64 VCCO - VCC1V2   - IO_L1P_T0L_N0_DBC_64
+#Other net   PACKAGE_PIN AG16     - 6N11370                   Bank  64 - VREF_64
+#Other net   PACKAGE_PIN AD9      - MGT1V2                    Bank 224 - MGTAVTTRCAL_R
+#Other net   PACKAGE_PIN A24      - MIO0_QSPI_LWR_CLK         Bank 500 - PS_MIO0
+#Other net   PACKAGE_PIN C24      - MIO1_QSPI_LWR_DQ1         Bank 500 - PS_MIO1
+#Other net   PACKAGE_PIN F26      - 53N7803                   Bank 500 - PS_MIO10
+#Other net   PACKAGE_PIN B26      - 53N7806                   Bank 500 - PS_MIO11
+#Other net   PACKAGE_PIN C27      - 53N7809                   Bank 500 - PS_MIO12
+#Other net   PACKAGE_PIN D27      - 53N7788                   Bank 500 - PS_MIO13
+#Other net   PACKAGE_PIN A27      - 53N7844                   Bank 500 - PS_MIO14
+#Other net   PACKAGE_PIN E27      - 53N7842                   Bank 500 - PS_MIO15
+#Other net   PACKAGE_PIN A28      - MIO16_I2C1_SCL            Bank 500 - PS_MIO16
+#Other net   PACKAGE_PIN C29      - MIO17_I2C1_SDA            Bank 500 - PS_MIO17
+#Other net   PACKAGE_PIN F27      - UART0_TXD_MIO18_RXD       Bank 500 - PS_MIO18
+#Other net   PACKAGE_PIN B28      - UART0_RXD_MIO19_TXD       Bank 500 - PS_MIO19
+#Other net   PACKAGE_PIN B24      - MIO2_QSPI_LWR_DQ2         Bank 500 - PS_MIO2
+#Other net   PACKAGE_PIN E29      - UART1_RXD_MIO20_TXD       Bank 500 - PS_MIO20
+#Other net   PACKAGE_PIN C28      - UART1_TXD_MIO21_RXD       Bank 500 - PS_MIO21
+#Other net   PACKAGE_PIN F28      - 53N7824                   Bank 500 - PS_MIO22
+#Other net   PACKAGE_PIN B29      - 53N7822                   Bank 500 - PS_MIO23
+#Other net   PACKAGE_PIN E28      - MIO24_CAN_TX              Bank 500 - PS_MIO24
+#Other net   PACKAGE_PIN D29      - MIO25_CAN_RX              Bank 500 - PS_MIO25
+#Other net   PACKAGE_PIN E25      - MIO3_QSPI_LWR_DQ3         Bank 500 - PS_MIO3
+#Other net   PACKAGE_PIN A25      - MIO4_QSPI_LWR_DQ0         Bank 500 - PS_MIO4
+#Other net   PACKAGE_PIN D25      - MIO5_QSPI_LWR_CS_B        Bank 500 - PS_MIO5
+#Other net   PACKAGE_PIN A26      - 53N6816                   Bank 500 - PS_MIO6
+#Other net   PACKAGE_PIN B25      - 53N7794                   Bank 500 - PS_MIO7
+#Other net   PACKAGE_PIN D26      - 53N7797                   Bank 500 - PS_MIO8
+#Other net   PACKAGE_PIN C26      - 53N7800                   Bank 500 - PS_MIO9
+#Other net   PACKAGE_PIN AA25     - PS_SYSMON_AVCC            Bank 500 - VCC_PSADC
+#Other net   PACKAGE_PIN AA24     - PS_SYSMON_AGND            Bank 500 - GND_PSADC
+#Other net   PACKAGE_PIN A29      - 53N7791                   Bank 501 - PS_MIO26
+#Other net   PACKAGE_PIN A30      - MIO27_DP_AUX_OUT          Bank 501 - PS_MIO27
+#Other net   PACKAGE_PIN A31      - MIO28_DP_HPD              Bank 501 - PS_MIO28
+#Other net   PACKAGE_PIN A32      - MIO29_DP_OE               Bank 501 - PS_MIO29
+#Other net   PACKAGE_PIN A33      - MIO30_DP_AUX_IN           Bank 501 - PS_MIO30
+#Other net   PACKAGE_PIN B30      - 53N7736                   Bank 501 - PS_MIO31
+#Other net   PACKAGE_PIN B31      - 53N7739                   Bank 501 - PS_MIO32
+#Other net   PACKAGE_PIN B33      - 53N7742                   Bank 501 - PS_MIO33
+#Other net   PACKAGE_PIN B34      - 53N7745                   Bank 501 - PS_MIO34
+#Other net   PACKAGE_PIN C31      - 53N7748                   Bank 501 - PS_MIO35
+#Other net   PACKAGE_PIN C32      - 53N7751                   Bank 501 - PS_MIO36
+#Other net   PACKAGE_PIN C33      - 53N7754                   Bank 501 - PS_MIO37
+#Other net   PACKAGE_PIN C34      - 53N7768                   Bank 501 - PS_MIO38
+#Other net   PACKAGE_PIN D30      - 53N7771                   Bank 501 - PS_MIO39
+#Other net   PACKAGE_PIN D31      - 53N7773                   Bank 501 - PS_MIO40
+#Other net   PACKAGE_PIN D32      - 53N7775                   Bank 501 - PS_MIO41
+#Other net   PACKAGE_PIN D34      - 53N7777                   Bank 501 - PS_MIO42
+#Other net   PACKAGE_PIN E30      - 53N6798                   Bank 501 - PS_MIO43
+#Other net   PACKAGE_PIN E32      - 53N7783                   Bank 501 - PS_MIO44
+#Other net   PACKAGE_PIN E33      - MIO45_SDIO_DETECT         Bank 501 - PS_MIO45
+#Other net   PACKAGE_PIN E34      - MIO46_SDIO_DAT0_R         Bank 501 - PS_MIO46
+#Other net   PACKAGE_PIN F30      - MIO47_SDIO_DAT1_R         Bank 501 - PS_MIO47
+#Other net   PACKAGE_PIN F31      - MIO48_SDIO_DAT2_R         Bank 501 - PS_MIO48
+#Other net   PACKAGE_PIN F32      - MIO49_SDIO_DAT3_R         Bank 501 - PS_MIO49
+#Other net   PACKAGE_PIN F33      - MIO50_SDIO_CMD_R          Bank 501 - PS_MIO50
+#Other net   PACKAGE_PIN F34      - MIO51_SDIO_CLK_R          Bank 501 - PS_MIO51
+#Other net   PACKAGE_PIN G29      - MIO52_USB_CLK             Bank 502 - PS_MIO52
+#Other net   PACKAGE_PIN G30      - MIO53_USB_DIR             Bank 502 - PS_MIO53
+#Other net   PACKAGE_PIN G31      - MIO54_USB_DATA2_R         Bank 502 - PS_MIO54
+#Other net   PACKAGE_PIN G33      - MIO55_USB_NXT             Bank 502 - PS_MIO55
+#Other net   PACKAGE_PIN G34      - MIO56_USB_DATA0_R         Bank 502 - PS_MIO56
+#Other net   PACKAGE_PIN H29      - MIO57_USB_DATA1_R         Bank 502 - PS_MIO57
+#Other net   PACKAGE_PIN H31      - MIO58_USB_STP_R           Bank 502 - PS_MIO58
+#Other net   PACKAGE_PIN H32      - MIO59_USB_DATA3_R         Bank 502 - PS_MIO59
+#Other net   PACKAGE_PIN H33      - MIO60_USB_DATA4_R         Bank 502 - PS_MIO60
+#Other net   PACKAGE_PIN H34      - MIO61_USB_DATA5_R         Bank 502 - PS_MIO61
+#Other net   PACKAGE_PIN J29      - MIO62_USB_DATA6_R         Bank 502 - PS_MIO62
+#Other net   PACKAGE_PIN J30      - MIO63_USB_DATA7_R         Bank 502 - PS_MIO63
+#Other net   PACKAGE_PIN J31      - MIO64_ENET_TX_CLK         Bank 502 - PS_MIO64
+#Other net   PACKAGE_PIN J32      - MIO65_ENET_TX_D0          Bank 502 - PS_MIO65
+#Other net   PACKAGE_PIN J34      - MIO66_ENET_TX_D1          Bank 502 - PS_MIO66
+#Other net   PACKAGE_PIN K28      - MIO67_ENET_TX_D2          Bank 502 - PS_MIO67
+#Other net   PACKAGE_PIN K29      - MIO68_ENET_TX_D3          Bank 502 - PS_MIO68
+#Other net   PACKAGE_PIN K30      - MIO69_ENET_TX_CTRL        Bank 502 - PS_MIO69
+#Other net   PACKAGE_PIN K31      - MIO70_ENET_RX_CLK         Bank 502 - PS_MIO70
+#Other net   PACKAGE_PIN K32      - MIO71_ENET_RX_D0          Bank 502 - PS_MIO71
+#Other net   PACKAGE_PIN K33      - MIO72_ENET_RX_D1          Bank 502 - PS_MIO72
+#Other net   PACKAGE_PIN K34      - MIO73_ENET_RX_D2          Bank 502 - PS_MIO73
+#Other net   PACKAGE_PIN L29      - MIO74_ENET_RX_D3          Bank 502 - PS_MIO74
+#Other net   PACKAGE_PIN L30      - MIO75_ENET_RX_CTRL        Bank 502 - PS_MIO75
+#Other net   PACKAGE_PIN L33      - MIO76_ENET_MDC            Bank 502 - PS_MIO76
+#Other net   PACKAGE_PIN L34      - MIO77_ENET_MDIO           Bank 502 - PS_MIO77
+#Other net   PACKAGE_PIN N24      - PS_DONE                   Bank 503 - PS_DONE
+#Other net   PACKAGE_PIN T25      - PS_ERR_OUT                Bank 503 - PS_ERROR_OUT
+#Other net   PACKAGE_PIN R25      - PS_ERR_STATUS             Bank 503 - PS_ERROR_STATUS
+#Other net   PACKAGE_PIN P24      - PS_INIT_B                 Bank 503 - PS_INIT_B
+#Other net   PACKAGE_PIN K27      - FPGA_TCK                  Bank 503 - PS_JTAG_TCK
+#Other net   PACKAGE_PIN J27      - FPGA_TDI                  Bank 503 - PS_JTAG_TDI
+#Other net   PACKAGE_PIN G28      - FPGA_TDO_FMC_TDI          Bank 503 - PS_JTAG_TDO
+#Other net   PACKAGE_PIN H28      - FPGA_TMS                  Bank 503 - PS_JTAG_TMS
+#Other net   PACKAGE_PIN H27      - PS_MODE0                  Bank 503 - PS_MODE0
+#Other net   PACKAGE_PIN J26      - PS_MODE1                  Bank 503 - PS_MODE1
+#Other net   PACKAGE_PIN K26      - PS_MODE2                  Bank 503 - PS_MODE2
+#Other net   PACKAGE_PIN K25      - PS_MODE3                  Bank 503 - PS_MODE3
+#Other net   PACKAGE_PIN M25      - PS_PADI                   Bank 503 - PS_PADI
+#Other net   PACKAGE_PIN L25      - PS_PADO                   Bank 503 - PS_PADO
+#Other net   PACKAGE_PIN M24      - PS_POR_B                  Bank 503 - PS_POR_B
+#Other net   PACKAGE_PIN T24      - PS_PROG_B                 Bank 503 - PS_PROG_B
+#Other net   PACKAGE_PIN R24      - PS_REF_CLK                Bank 503 - PS_REF_CLK
+#Other net   PACKAGE_PIN P25      - PS_SRST_B                 Bank 503 - PS_SRST_B
+#Other net   PACKAGE_PIN AN34     - DDR4_A0                   Bank 504 - PS_DDR_A0
+#Other net   PACKAGE_PIN AM34     - DDR4_A1                   Bank 504 - PS_DDR_A1
+#Other net   PACKAGE_PIN AG31     - DDR4_A10                  Bank 504 - PS_DDR_A10
+#Other net   PACKAGE_PIN AF31     - DDR4_A11                  Bank 504 - PS_DDR_A11
+#Other net   PACKAGE_PIN AG30     - DDR4_A12                  Bank 504 - PS_DDR_A12
+#Other net   PACKAGE_PIN AF30     - DDR4_A13                  Bank 504 - PS_DDR_A13
+#Other net   PACKAGE_PIN AG29     - DDR4_A14_WE_B             Bank 504 - PS_DDR_A14
+#Other net   PACKAGE_PIN AG28     - DDR4_A15_CAS_B            Bank 504 - PS_DDR_A15
+#Other net   PACKAGE_PIN AF28     - DDR4_A16_RAS_B            Bank 504 - PS_DDR_A16
+#Other net   PACKAGE_PIN AF26     - 68N6692                   Bank 504 - PS_DDR_A17
+#Other net   PACKAGE_PIN AM33     - DDR4_A2                   Bank 504 - PS_DDR_A2
+#Other net   PACKAGE_PIN AL34     - DDR4_A3                   Bank 504 - PS_DDR_A3
+#Other net   PACKAGE_PIN AL33     - DDR4_A4                   Bank 504 - PS_DDR_A4
+#Other net   PACKAGE_PIN AK33     - DDR4_A5                   Bank 504 - PS_DDR_A5
+#Other net   PACKAGE_PIN AK30     - DDR4_A6                   Bank 504 - PS_DDR_A6
+#Other net   PACKAGE_PIN AJ30     - DDR4_A7                   Bank 504 - PS_DDR_A7
+#Other net   PACKAGE_PIN AJ31     - DDR4_A8                   Bank 504 - PS_DDR_A8
+#Other net   PACKAGE_PIN AH31     - DDR4_A9                   Bank 504 - PS_DDR_A9
+#Other net   PACKAGE_PIN AE25     - DDR4_ACT_B                Bank 504 - PS_DDR_ACT_N
+#Other net   PACKAGE_PIN AB26     - DDR4_ALERT_B              Bank 504 - PS_DDR_ALERT_N
+#Other net   PACKAGE_PIN AE27     - DDR4_BA0                  Bank 504 - PS_DDR_BA0
+#Other net   PACKAGE_PIN AE28     - DDR4_BA1                  Bank 504 - PS_DDR_BA1
+#Other net   PACKAGE_PIN AD27     - DDR4_BG0                  Bank 504 - PS_DDR_BG0
+#Other net   PACKAGE_PIN AF27     - 68N7393                   Bank 504 - PS_DDR_BG1
+#Other net   PACKAGE_PIN AL31     - DDR4_CK_T                 Bank 504 - PS_DDR_CK0
+#Other net   PACKAGE_PIN AL30     - 68N7399                   Bank 504 - PS_DDR_CK1
+#Other net   PACKAGE_PIN AN33     - DDR4_CKE                  Bank 504 - PS_DDR_CKE0
+#Other net   PACKAGE_PIN AH32     - 68N7405                   Bank 504 - PS_DDR_CKE1
+#Other net   PACKAGE_PIN AN32     - DDR4_CK_C                 Bank 504 - PS_DDR_CK_N0
+#Other net   PACKAGE_PIN AL32     - 68N7402                   Bank 504 - PS_DDR_CK_N1
+#Other net   PACKAGE_PIN AP33     - DDR4_CS_B                 Bank 504 - PS_DDR_CS_N0
+#Other net   PACKAGE_PIN AK32     - 68N7396                   Bank 504 - PS_DDR_CS_N1
+#Other net   PACKAGE_PIN AN24     - DDR4_DM0                  Bank 504 - PS_DDR_DM0
+#Other net   PACKAGE_PIN AM29     - DDR4_DM1                  Bank 504 - PS_DDR_DM1
+#Other net   PACKAGE_PIN AH24     - DDR4_DM2                  Bank 504 - PS_DDR_DM2
+#Other net   PACKAGE_PIN AJ29     - DDR4_DM3                  Bank 504 - PS_DDR_DM3
+#Other net   PACKAGE_PIN AD29     - DDR4_DM4                  Bank 504 - PS_DDR_DM4
+#Other net   PACKAGE_PIN Y29      - DDR4_DM5                  Bank 504 - PS_DDR_DM5
+#Other net   PACKAGE_PIN AC32     - DDR4_DM6                  Bank 504 - PS_DDR_DM6
+#Other net   PACKAGE_PIN Y32      - DDR4_DM7                  Bank 504 - PS_DDR_DM7
+#Other net   PACKAGE_PIN AF34     - 68N7353                   Bank 504 - PS_DDR_DM8
+#Other net   PACKAGE_PIN AP27     - DDR4_DQ0                  Bank 504 - PS_DDR_DQ0
+#Other net   PACKAGE_PIN AP25     - DDR4_DQ1                  Bank 504 - PS_DDR_DQ1
+#Other net   PACKAGE_PIN AP29     - DDR4_DQ10                 Bank 504 - PS_DDR_DQ10
+#Other net   PACKAGE_PIN AP28     - DDR4_DQ11                 Bank 504 - PS_DDR_DQ11
+#Other net   PACKAGE_PIN AM31     - DDR4_DQ12                 Bank 504 - PS_DDR_DQ12
+#Other net   PACKAGE_PIN AP31     - DDR4_DQ13                 Bank 504 - PS_DDR_DQ13
+#Other net   PACKAGE_PIN AN31     - DDR4_DQ14                 Bank 504 - PS_DDR_DQ14
+#Other net   PACKAGE_PIN AM30     - DDR4_DQ15                 Bank 504 - PS_DDR_DQ15
+#Other net   PACKAGE_PIN AF25     - DDR4_DQ16                 Bank 504 - PS_DDR_DQ16
+#Other net   PACKAGE_PIN AG25     - DDR4_DQ17                 Bank 504 - PS_DDR_DQ17
+#Other net   PACKAGE_PIN AG26     - DDR4_DQ18                 Bank 504 - PS_DDR_DQ18
+#Other net   PACKAGE_PIN AJ25     - DDR4_DQ19                 Bank 504 - PS_DDR_DQ19
+#Other net   PACKAGE_PIN AP26     - DDR4_DQ2                  Bank 504 - PS_DDR_DQ2
+#Other net   PACKAGE_PIN AG24     - DDR4_DQ20                 Bank 504 - PS_DDR_DQ20
+#Other net   PACKAGE_PIN AK25     - DDR4_DQ21                 Bank 504 - PS_DDR_DQ21
+#Other net   PACKAGE_PIN AJ24     - DDR4_DQ22                 Bank 504 - PS_DDR_DQ22
+#Other net   PACKAGE_PIN AK24     - DDR4_DQ23                 Bank 504 - PS_DDR_DQ23
+#Other net   PACKAGE_PIN AH28     - DDR4_DQ24                 Bank 504 - PS_DDR_DQ24
+#Other net   PACKAGE_PIN AH27     - DDR4_DQ25                 Bank 504 - PS_DDR_DQ25
+#Other net   PACKAGE_PIN AJ27     - DDR4_DQ26                 Bank 504 - PS_DDR_DQ26
+#Other net   PACKAGE_PIN AK27     - DDR4_DQ27                 Bank 504 - PS_DDR_DQ27
+#Other net   PACKAGE_PIN AL26     - DDR4_DQ28                 Bank 504 - PS_DDR_DQ28
+#Other net   PACKAGE_PIN AL27     - DDR4_DQ29                 Bank 504 - PS_DDR_DQ29
+#Other net   PACKAGE_PIN AM26     - DDR4_DQ3                  Bank 504 - PS_DDR_DQ3
+#Other net   PACKAGE_PIN AH29     - DDR4_DQ30                 Bank 504 - PS_DDR_DQ30
+#Other net   PACKAGE_PIN AL28     - DDR4_DQ31                 Bank 504 - PS_DDR_DQ31
+#Other net   PACKAGE_PIN AB29     - DDR4_DQ32                 Bank 504 - PS_DDR_DQ32
+#Other net   PACKAGE_PIN AB30     - DDR4_DQ33                 Bank 504 - PS_DDR_DQ33
+#Other net   PACKAGE_PIN AC29     - DDR4_DQ34                 Bank 504 - PS_DDR_DQ34
+#Other net   PACKAGE_PIN AD32     - DDR4_DQ35                 Bank 504 - PS_DDR_DQ35
+#Other net   PACKAGE_PIN AC31     - DDR4_DQ36                 Bank 504 - PS_DDR_DQ36
+#Other net   PACKAGE_PIN AE30     - DDR4_DQ37                 Bank 504 - PS_DDR_DQ37
+#Other net   PACKAGE_PIN AC28     - DDR4_DQ38                 Bank 504 - PS_DDR_DQ38
+#Other net   PACKAGE_PIN AE29     - DDR4_DQ39                 Bank 504 - PS_DDR_DQ39
+#Other net   PACKAGE_PIN AP24     - DDR4_DQ4                  Bank 504 - PS_DDR_DQ4
+#Other net   PACKAGE_PIN AC27     - DDR4_DQ40                 Bank 504 - PS_DDR_DQ40
+#Other net   PACKAGE_PIN AA27     - DDR4_DQ41                 Bank 504 - PS_DDR_DQ41
+#Other net   PACKAGE_PIN AA28     - DDR4_DQ42                 Bank 504 - PS_DDR_DQ42
+#Other net   PACKAGE_PIN AB28     - DDR4_DQ43                 Bank 504 - PS_DDR_DQ43
+#Other net   PACKAGE_PIN W27      - DDR4_DQ44                 Bank 504 - PS_DDR_DQ44
+#Other net   PACKAGE_PIN W29      - DDR4_DQ45                 Bank 504 - PS_DDR_DQ45
+#Other net   PACKAGE_PIN W28      - DDR4_DQ46                 Bank 504 - PS_DDR_DQ46
+#Other net   PACKAGE_PIN V27      - DDR4_DQ47                 Bank 504 - PS_DDR_DQ47
+#Other net   PACKAGE_PIN AA32     - DDR4_DQ48                 Bank 504 - PS_DDR_DQ48
+#Other net   PACKAGE_PIN AA33     - DDR4_DQ49                 Bank 504 - PS_DDR_DQ49
+#Other net   PACKAGE_PIN AL25     - DDR4_DQ5                  Bank 504 - PS_DDR_DQ5
+#Other net   PACKAGE_PIN AA34     - DDR4_DQ50                 Bank 504 - PS_DDR_DQ50
+#Other net   PACKAGE_PIN AE34     - DDR4_DQ51                 Bank 504 - PS_DDR_DQ51
+#Other net   PACKAGE_PIN AD34     - DDR4_DQ52                 Bank 504 - PS_DDR_DQ52
+#Other net   PACKAGE_PIN AB31     - DDR4_DQ53                 Bank 504 - PS_DDR_DQ53
+#Other net   PACKAGE_PIN AC34     - DDR4_DQ54                 Bank 504 - PS_DDR_DQ54
+#Other net   PACKAGE_PIN AC33     - DDR4_DQ55                 Bank 504 - PS_DDR_DQ55
+#Other net   PACKAGE_PIN AA30     - DDR4_DQ56                 Bank 504 - PS_DDR_DQ56
+#Other net   PACKAGE_PIN Y30      - DDR4_DQ57                 Bank 504 - PS_DDR_DQ57
+#Other net   PACKAGE_PIN AA31     - DDR4_DQ58                 Bank 504 - PS_DDR_DQ58
+#Other net   PACKAGE_PIN W30      - DDR4_DQ59                 Bank 504 - PS_DDR_DQ59
+#Other net   PACKAGE_PIN AM25     - DDR4_DQ6                  Bank 504 - PS_DDR_DQ6
+#Other net   PACKAGE_PIN Y33      - DDR4_DQ60                 Bank 504 - PS_DDR_DQ60
+#Other net   PACKAGE_PIN W33      - DDR4_DQ61                 Bank 504 - PS_DDR_DQ61
+#Other net   PACKAGE_PIN W34      - DDR4_DQ62                 Bank 504 - PS_DDR_DQ62
+#Other net   PACKAGE_PIN Y34      - DDR4_DQ63                 Bank 504 - PS_DDR_DQ63
+#Other net   PACKAGE_PIN AF32     - 68N7356                   Bank 504 - PS_DDR_DQ64
+#Other net   PACKAGE_PIN AE32     - 68N7359                   Bank 504 - PS_DDR_DQ65
+#Other net   PACKAGE_PIN AH33     - 68N7362                   Bank 504 - PS_DDR_DQ66
+#Other net   PACKAGE_PIN AE33     - 68N7364                   Bank 504 - PS_DDR_DQ67
+#Other net   PACKAGE_PIN AF33     - 68N7368                   Bank 504 - PS_DDR_DQ68
+#Other net   PACKAGE_PIN AH34     - 68N7370                   Bank 504 - PS_DDR_DQ69
+#Other net   PACKAGE_PIN AM24     - DDR4_DQ7                  Bank 504 - PS_DDR_DQ7
+#Other net   PACKAGE_PIN AJ34     - 68N7374                   Bank 504 - PS_DDR_DQ70
+#Other net   PACKAGE_PIN AK34     - 68N7376                   Bank 504 - PS_DDR_DQ71
+#Other net   PACKAGE_PIN AM28     - DDR4_DQ8                  Bank 504 - PS_DDR_DQ8
+#Other net   PACKAGE_PIN AN28     - DDR4_DQ9                  Bank 504 - PS_DDR_DQ9
+#Other net   PACKAGE_PIN AN27     - DDR4_DQS0_C               Bank 504 - PS_DDR_DQS_N0
+#Other net   PACKAGE_PIN AP30     - DDR4_DQS1_C               Bank 504 - PS_DDR_DQS_N1
+#Other net   PACKAGE_PIN AJ26     - DDR4_DQS2_C               Bank 504 - PS_DDR_DQS_N2
+#Other net   PACKAGE_PIN AK29     - DDR4_DQS3_C               Bank 504 - PS_DDR_DQS_N3
+#Other net   PACKAGE_PIN AD31     - DDR4_DQS4_C               Bank 504 - PS_DDR_DQS_N4
+#Other net   PACKAGE_PIN Y28      - DDR4_DQS5_C               Bank 504 - PS_DDR_DQS_N5
+#Other net   PACKAGE_PIN AB34     - DDR4_DQS6_C               Bank 504 - PS_DDR_DQS_N6
+#Other net   PACKAGE_PIN W32      - DDR4_DQS7_C               Bank 504 - PS_DDR_DQS_N7
+#Other net   PACKAGE_PIN AG34     - 68N7350                   Bank 504 - PS_DDR_DQS_N8
+#Other net   PACKAGE_PIN AN26     - DDR4_DQS0_T               Bank 504 - PS_DDR_DQS_P0
+#Other net   PACKAGE_PIN AN29     - DDR4_DQS1_T               Bank 504 - PS_DDR_DQS_P1
+#Other net   PACKAGE_PIN AH26     - DDR4_DQS2_T               Bank 504 - PS_DDR_DQS_P2
+#Other net   PACKAGE_PIN AK28     - DDR4_DQS3_T               Bank 504 - PS_DDR_DQS_P3
+#Other net   PACKAGE_PIN AD30     - DDR4_DQS4_T               Bank 504 - PS_DDR_DQS_P4
+#Other net   PACKAGE_PIN Y27      - DDR4_DQS5_T               Bank 504 - PS_DDR_DQS_P5
+#Other net   PACKAGE_PIN AB33     - DDR4_DQS6_T               Bank 504 - PS_DDR_DQS_P6
+#Other net   PACKAGE_PIN W31      - DDR4_DQS7_T               Bank 504 - PS_DDR_DQS_P7
+#Other net   PACKAGE_PIN AG33     - 68N7347                   Bank 504 - PS_DDR_DQS_P8
+#Other net   PACKAGE_PIN AP32     - DDR4_ODT                  Bank 504 - PS_DDR_ODT0
+#Other net   PACKAGE_PIN AJ32     - 68N7408                   Bank 504 - PS_DDR_ODT1
+#Other net   PACKAGE_PIN AA26     - DDR4_PAR                  Bank 504 - PS_DDR_PARITY
+#Other net   PACKAGE_PIN AD26     - DDR4_RESET_B              Bank 504 - PS_DDR_RAM_RST_N
+#Other net   PACKAGE_PIN AC26     - SODIMM_ZQ                 Bank 504 - PS_DDR_ZQ
+#Other net   PACKAGE_PIN U34      - 69N6524                   Bank 505 - PS_MGTRRXN0_505
+#Other net   PACKAGE_PIN T32      - 69N6530                   Bank 505 - PS_MGTRRXN1_505
+#Other net   PACKAGE_PIN R34      - GT2_USB0_RX_N             Bank 505 - PS_MGTRRXN2_505
+#Other net   PACKAGE_PIN N34      - GT3_SATA1_RX_N            Bank 505 - PS_MGTRRXN3_505
+#Other net   PACKAGE_PIN U33      - 69N6521                   Bank 505 - PS_MGTRRXP0_505
+#Other net   PACKAGE_PIN T31      - 69N6527                   Bank 505 - PS_MGTRRXP1_505
+#Other net   PACKAGE_PIN R33      - GT2_USB0_RX_P             Bank 505 - PS_MGTRRXP2_505
+#Other net   PACKAGE_PIN N33      - GT3_SATA1_RX_P            Bank 505 - PS_MGTRRXP3_505
+#Other net   PACKAGE_PIN U30      - GT0_DP_TX_N               Bank 505 - PS_MGTRTXN0_505
+#Other net   PACKAGE_PIN R30      - GT1_DP_TX_N               Bank 505 - PS_MGTRTXN1_505
+#Other net   PACKAGE_PIN P32      - GT2_USB0_TX_N             Bank 505 - PS_MGTRTXN2_505
+#Other net   PACKAGE_PIN N30      - GT3_SATA1_TX_N            Bank 505 - PS_MGTRTXN3_505
+#Other net   PACKAGE_PIN U29      - GT0_DP_TX_P               Bank 505 - PS_MGTRTXP0_505
+#Other net   PACKAGE_PIN R29      - GT1_DP_TX_P               Bank 505 - PS_MGTRTXP1_505
+#Other net   PACKAGE_PIN P31      - GT2_USB0_TX_P             Bank 505 - PS_MGTRTXP2_505
+#Other net   PACKAGE_PIN N29      - GT3_SATA1_TX_P            Bank 505 - PS_MGTRTXP3_505
+#Other net   PACKAGE_PIN T28      - 69N6536                   Bank 505 - PS_MGTREFCLK0N_505
+#Other net   PACKAGE_PIN T27      - 69N6533                   Bank 505 - PS_MGTREFCLK0P_505
+#Other net   PACKAGE_PIN P28      - GTR_REF_CLK_SATA_C_N      Bank 505 - PS_MGTREFCLK1N_505
+#Other net   PACKAGE_PIN P27      - GTR_REF_CLK_SATA_C_P      Bank 505 - PS_MGTREFCLK1P_505
+#Other net   PACKAGE_PIN M28      - GTR_REF_CLK_USB3_C_N      Bank 505 - PS_MGTREFCLK2N_505
+#Other net   PACKAGE_PIN M27      - GTR_REF_CLK_USB3_C_P      Bank 505 - PS_MGTREFCLK2P_505
+#Other net   PACKAGE_PIN M32      - GTR_REF_CLK_DP_C_N        Bank 505 - PS_MGTREFCLK3N_505
+#Other net   PACKAGE_PIN M31      - GTR_REF_CLK_DP_C_P        Bank 505 - PS_MGTREFCLK3P_505
+#Other net   PACKAGE_PIN U31      - 69N5804                   Bank 505 - PS_MGTRREF_505
+#Other net   PACKAGE_PIN AE16     - VCC1V2                    Bank  64 - VCCO_64
+#Other net   PACKAGE_PIN AH15     - VCC1V2                    Bank  64 - VCCO_64
+#Other net   PACKAGE_PIN AJ18     - VCC1V2                    Bank  64 - VCCO_64
+#Other net   PACKAGE_PIN AF19     - VCC1V2                    Bank  65 - VCCO_65
+#Other net   PACKAGE_PIN AG22     - VCC1V2                    Bank  65 - VCCO_65
+#Other net   PACKAGE_PIN AK21     - VCC1V2                    Bank  65 - VCCO_65
+#Other net   PACKAGE_PIN AF9      - VCC1V2                    Bank  66 - VCCO_66
+#Other net   PACKAGE_PIN AG12     - VCC1V2                    Bank  66 - VCCO_66
+#Other net   PACKAGE_PIN AK11     - VCC1V2                    Bank  66 - VCCO_66
+#Other net   PACKAGE_PIN E21      - VCC1V8                    Bank  28 - VCCO_28
+#Other net   PACKAGE_PIN F24      - VCC1V8                    Bank  28 - VCCO_28
+#Other net   PACKAGE_PIN H20      - VCC1V8                    Bank  28 - VCCO_28
+#Other net   PACKAGE_PIN D13      - VADJ_FMC                  Bank  67 - VCCO_67
+#Other net   PACKAGE_PIN E16      - VADJ_FMC                  Bank  67 - VCCO_67
+#Other net   PACKAGE_PIN H15      - VADJ_FMC                  Bank  67 - VCCO_67
+#Other net   PACKAGE_PIN F9       - VADJ_FMC                  Bank  68 - VCCO_68
+#Other net   PACKAGE_PIN G12      - VADJ_FMC                  Bank  68 - VCCO_68
+#Other net   PACKAGE_PIN K11      - VADJ_FMC                  Bank  68 - VCCO_68
+#Other net   PACKAGE_PIN J8       - VCC3V3                    Bank  87 - VCCO_87
+#Other net   PACKAGE_PIN N10      - VCC3V3                    Bank  87 - VCCO_87
+#Other net   PACKAGE_PIN D3       - VCC3V3                    Bank  88 - VCCO_88
+#Other net   PACKAGE_PIN E6       - VCC3V3                    Bank  88 - VCCO_88
+#Other net   PACKAGE_PIN C25      - VCC1V8                    Bank 500 - VCCO_PSIO0_500
+#Other net   PACKAGE_PIN D28      - VCC1V8                    Bank 500 - VCCO_PSIO0_500
+#Other net   PACKAGE_PIN B32      - VCC1V8                    Bank 501 - VCCO_PSIO1_501
+#Other net   PACKAGE_PIN E31      - VCC1V8                    Bank 501 - VCCO_PSIO1_501
+#Other net   PACKAGE_PIN H30      - VCC1V8                    Bank 502 - VCCO_PSIO2_502
+#Other net   PACKAGE_PIN J33      - VCC1V8                    Bank 502 - VCCO_PSIO2_502
+#Other net   PACKAGE_PIN G27      - VCC1V8                    Bank 503 - VCCO_PSIO3_503
+#Other net   PACKAGE_PIN N25      - VCC1V8                    Bank 503 - VCCO_PSIO3_503
+#Other net   PACKAGE_PIN AE26     - VCC1V2                    Bank 504 - VCCO_PSDDR_504
+#Other net   PACKAGE_PIN AE31     - VCC1V2                    Bank 504 - VCCO_PSDDR_504
+#Other net   PACKAGE_PIN AG27     - VCC1V2                    Bank 504 - VCCO_PSDDR_504
+#Other net   PACKAGE_PIN AG32     - VCC1V2                    Bank 504 - VCCO_PSDDR_504
+#Other net   PACKAGE_PIN AJ28     - VCC1V2                    Bank 504 - VCCO_PSDDR_504
+#Other net   PACKAGE_PIN AJ33     - VCC1V2                    Bank 504 - VCCO_PSDDR_504
+#Other net   PACKAGE_PIN AL29     - VCC1V2                    Bank 504 - VCCO_PSDDR_504
+#Other net   PACKAGE_PIN A1       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN A34      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN A4       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AA11     - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AA21     - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AA29     - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AA3      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AA4      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AA7      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AB1      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AB11     - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AB17     - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AB2      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AB27     - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AB32     - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AB5      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AB9      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AC11     - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AC15     - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AC20     - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AC23     - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AC3      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AC30     - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AC4      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AC7      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AD1      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AD11     - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AD13     - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AD18     - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AD2      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AD25     - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AD28     - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AD33     - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AD5      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AE10     - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AE11     - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AE21     - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AE3      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AE4      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AE7      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AE8      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AE9      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AF1      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AF14     - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AF2      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AF24     - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AF29     - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AF5      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AF7      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AG17     - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AG3      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AG4      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AG7      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AH1      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AH10     - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AH2      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AH20     - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AH25     - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AH30     - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AH5      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AH7      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AJ13     - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AJ23     - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AJ3      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AJ4      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AJ7      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AJ8      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AK1      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AK16     - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AK2      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AK26     - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AK31     - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AK5      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AK7      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AL14     - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AL19     - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AL24     - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AL3      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AL4      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AL7      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AL9      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AM1      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AM12     - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AM17     - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AM2      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AM22     - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AM27     - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AM32     - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AM5      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AM7      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AN10     - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AN15     - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AN20     - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AN25     - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AN3      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AN30     - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AN4      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AN7      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AP1      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AP2      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AP34     - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AP5      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AP7      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN B12      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN B17      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN B2       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN B22      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN B27      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN B7       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN C10      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN C15      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN C20      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN C30      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN C5       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN D18      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN D23      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN D33      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN D8       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN E11      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN E26      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN F1       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN F14      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN F19      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN F2       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN F29      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN F3       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN G17      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN G22      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN G3       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN G32      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN G4       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN G5       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN H1       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN H10      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN H2       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN H25      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN H5       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN J13      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN J18      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN J23      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN J28      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN J3       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN J4       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN J5       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN K1       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN K16      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN K2       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN K21      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN K5       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN K6       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN K7       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN L19      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN L24      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN L26      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN L27      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN L28      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN L3       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN L31      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN L32      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN L4       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN L7       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN L9       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN M1       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN M14      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN M16      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN M18      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN M2       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN M20      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN M22      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN M26      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN M29      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN M30      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN M33      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN M34      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN M5       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN M7       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN N15      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN N17      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN N19      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN N21      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN N23      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN N26      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN N28      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN N3       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN N32      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN N4       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN N7       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN P1       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN P10      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN P11      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN P14      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN P16      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN P18      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN P2       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN P20      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN P22      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN P26      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN P30      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN P33      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN P34      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN P5       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN P7       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN P8       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN P9       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN R11      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN R13      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN R15      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN R19      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN R21      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN R26      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN R28      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN R3       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN R31      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN R32      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN R4       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN R7       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN T1       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN T11      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN T14      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN T16      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN T2       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN T20      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN T23      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN T26      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN T30      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN T33      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN T34      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN T5       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN T9       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN U11      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN U12      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN U15      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN U19      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN U21      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN U24      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN U26      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN U27      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN U28      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN U3       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN U32      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN U4       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN U7       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN V1       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN V11      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN V14      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN V16      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN V2       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN V20      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN V28      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN V29      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN V30      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN V31      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN V32      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN V33      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN V34      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN V5       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN V9       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN W11      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN W13      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN W15      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN W17      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN W19      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN W23      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN W3       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN W4       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN W7       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN Y1       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN Y11      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN Y12      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN Y14      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN Y16      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN Y18      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN Y2       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN Y20      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN Y26      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN Y31      - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN Y5       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN Y9       - GND                       Bank 999 - GND
+#Other net   PACKAGE_PIN AA8      - MGTAVCC                   Bank 999 - MGTAVCC_R
+#Other net   PACKAGE_PIN AB10     - MGTAVCC                   Bank 999 - MGTAVCC_R
+#Other net   PACKAGE_PIN AC8      - MGTAVCC                   Bank 999 - MGTAVCC_R
+#Other net   PACKAGE_PIN R8       - MGTAVCC                   Bank 999 - MGTAVCC_R
+#Other net   PACKAGE_PIN T10      - MGTAVCC                   Bank 999 - MGTAVCC_R
+#Other net   PACKAGE_PIN U8       - MGTAVCC                   Bank 999 - MGTAVCC_R
+#Other net   PACKAGE_PIN W8       - MGTAVCC                   Bank 999 - MGTAVCC_R
+#Other net   PACKAGE_PIN AB6      - MGT1V2                    Bank 999 - MGTAVTT_R
+#Other net   PACKAGE_PIN AD6      - MGT1V2                    Bank 999 - MGTAVTT_R
+#Other net   PACKAGE_PIN AF6      - MGT1V2                    Bank 999 - MGTAVTT_R
+#Other net   PACKAGE_PIN AH6      - MGT1V2                    Bank 999 - MGTAVTT_R
+#Other net   PACKAGE_PIN AK6      - MGT1V2                    Bank 999 - MGTAVTT_R
+#Other net   PACKAGE_PIN AM6      - MGT1V2                    Bank 999 - MGTAVTT_R
+#Other net   PACKAGE_PIN AP6      - MGT1V2                    Bank 999 - MGTAVTT_R
+#Other net   PACKAGE_PIN M6       - MGT1V2                    Bank 999 - MGTAVTT_R
+#Other net   PACKAGE_PIN P6       - MGT1V2                    Bank 999 - MGTAVTT_R
+#Other net   PACKAGE_PIN T6       - MGT1V2                    Bank 999 - MGTAVTT_R
+#Other net   PACKAGE_PIN V6       - MGT1V2                    Bank 999 - MGTAVTT_R
+#Other net   PACKAGE_PIN Y6       - MGT1V2                    Bank 999 - MGTAVTT_R
+#Other net   PACKAGE_PIN V10      - MGT1V8                    Bank 999 - MGTVCCAUX_R
+#Other net   PACKAGE_PIN Y10      - MGT1V8                    Bank 999 - MGTVCCAUX_R
+#Other net   PACKAGE_PIN N27      - MGTRAVCC                  Bank 999 - PS_MGTRAVCC
+#Other net   PACKAGE_PIN R27      - MGTRAVCC                  Bank 999 - PS_MGTRAVCC
+#Other net   PACKAGE_PIN N31      - MGT1V8                    Bank 999 - PS_MGTRAVTT
+#Other net   PACKAGE_PIN P29      - MGT1V8                    Bank 999 - PS_MGTRAVTT
+#Other net   PACKAGE_PIN T29      - MGT1V8                    Bank 999 - PS_MGTRAVTT
+#Other net   PACKAGE_PIN P23      - VCC1V8                    Bank 999 - VCCAUX
+#Other net   PACKAGE_PIN R23      - VCC1V8                    Bank 999 - VCCAUX
+#Other net   PACKAGE_PIN U23      - VCC1V8                    Bank 999 - VCCAUX
+#Other net   PACKAGE_PIN V23      - VCC1V8                    Bank 999 - VCCAUX
+#Other net   PACKAGE_PIN N22      - VCC1V8                    Bank 999 - VCCAUX_IO
+#Other net   PACKAGE_PIN R22      - VCC1V8                    Bank 999 - VCCAUX_IO
+#Other net   PACKAGE_PIN T22      - VCC1V8                    Bank 999 - VCCAUX_IO
+#Other net   PACKAGE_PIN U22      - VCC1V8                    Bank 999 - VCCAUX_IO
+#Other net   PACKAGE_PIN R12      - VCCINT                    Bank 999 - VCCBRAM
+#Other net   PACKAGE_PIN T12      - VCCINT                    Bank 999 - VCCBRAM
+#Other net   PACKAGE_PIN V12      - VCCINT                    Bank 999 - VCCBRAM
+#Other net   PACKAGE_PIN W12      - VCCINT                    Bank 999 - VCCBRAM
+#Other net   PACKAGE_PIN M15      - VCCINT                    Bank 999 - VCCINT
+#Other net   PACKAGE_PIN M17      - VCCINT                    Bank 999 - VCCINT
+#Other net   PACKAGE_PIN M19      - VCCINT                    Bank 999 - VCCINT
+#Other net   PACKAGE_PIN M21      - VCCINT                    Bank 999 - VCCINT
+#Other net   PACKAGE_PIN N14      - VCCINT                    Bank 999 - VCCINT
+#Other net   PACKAGE_PIN N16      - VCCINT                    Bank 999 - VCCINT
+#Other net   PACKAGE_PIN N18      - VCCINT                    Bank 999 - VCCINT
+#Other net   PACKAGE_PIN N20      - VCCINT                    Bank 999 - VCCINT
+#Other net   PACKAGE_PIN P15      - VCCINT                    Bank 999 - VCCINT
+#Other net   PACKAGE_PIN P17      - VCCINT                    Bank 999 - VCCINT
+#Other net   PACKAGE_PIN P19      - VCCINT                    Bank 999 - VCCINT
+#Other net   PACKAGE_PIN P21      - VCCINT                    Bank 999 - VCCINT
+#Other net   PACKAGE_PIN R14      - VCCINT                    Bank 999 - VCCINT
+#Other net   PACKAGE_PIN R16      - VCCINT                    Bank 999 - VCCINT
+#Other net   PACKAGE_PIN R20      - VCCINT                    Bank 999 - VCCINT
+#Other net   PACKAGE_PIN T15      - VCCINT                    Bank 999 - VCCINT
+#Other net   PACKAGE_PIN T19      - VCCINT                    Bank 999 - VCCINT
+#Other net   PACKAGE_PIN T21      - VCCINT                    Bank 999 - VCCINT
+#Other net   PACKAGE_PIN U14      - VCCINT                    Bank 999 - VCCINT
+#Other net   PACKAGE_PIN U16      - VCCINT                    Bank 999 - VCCINT
+#Other net   PACKAGE_PIN U20      - VCCINT                    Bank 999 - VCCINT
+#Other net   PACKAGE_PIN V15      - VCCINT                    Bank 999 - VCCINT
+#Other net   PACKAGE_PIN V19      - VCCINT                    Bank 999 - VCCINT
+#Other net   PACKAGE_PIN V21      - VCCINT                    Bank 999 - VCCINT
+#Other net   PACKAGE_PIN W14      - VCCINT                    Bank 999 - VCCINT
+#Other net   PACKAGE_PIN W16      - VCCINT                    Bank 999 - VCCINT
+#Other net   PACKAGE_PIN W18      - VCCINT                    Bank 999 - VCCINT
+#Other net   PACKAGE_PIN W20      - VCCINT                    Bank 999 - VCCINT
+#Other net   PACKAGE_PIN Y15      - VCCINT                    Bank 999 - VCCINT
+#Other net   PACKAGE_PIN Y17      - VCCINT                    Bank 999 - VCCINT
+#Other net   PACKAGE_PIN Y19      - VCCINT                    Bank 999 - VCCINT
+#Other net   PACKAGE_PIN P13      - VCCINT                    Bank 999 - VCCINT_IO
+#Other net   PACKAGE_PIN T13      - VCCINT                    Bank 999 - VCCINT_IO
+#Other net   PACKAGE_PIN U13      - VCCINT                    Bank 999 - VCCINT_IO
+#Other net   PACKAGE_PIN V13      - VCCINT                    Bank 999 - VCCINT_IO
+#Other net   PACKAGE_PIN Y13      - VCCINT                    Bank 999 - VCCINT_IO
+#Other net   PACKAGE_PIN V26      - VCC1V8                    Bank 999 - VCC_PSAUX
+#Other net   PACKAGE_PIN W25      - VCC1V8                    Bank 999 - VCC_PSAUX
+#Other net   PACKAGE_PIN W26      - VCC1V8                    Bank 999 - VCC_PSAUX
+#Other net   PACKAGE_PIN Y25      - VCC1V8                    Bank 999 - VCC_PSAUX
+#Other net   PACKAGE_PIN Y23      - VCC_PSBATT                Bank 999 - VCC_PSBATT
+#Other net   PACKAGE_PIN U25      - VCCPSDDRPLL               Bank 999 - VCC_PSDDR_PLL
+#Other net   PACKAGE_PIN V25      - VCCPSDDRPLL               Bank 999 - VCC_PSDDR_PLL
+#Other net   PACKAGE_PIN AA23     - VCCINT                    Bank 999 - VCC_PSINTFP
+#Other net   PACKAGE_PIN AB21     - VCCINT                    Bank 999 - VCC_PSINTFP
+#Other net   PACKAGE_PIN AB22     - VCCINT                    Bank 999 - VCC_PSINTFP
+#Other net   PACKAGE_PIN AB23     - VCCINT                    Bank 999 - VCC_PSINTFP
+#Other net   PACKAGE_PIN AB24     - VCCINT                    Bank 999 - VCC_PSINTFP
+#Other net   PACKAGE_PIN AC21     - VCCINT                    Bank 999 - VCC_PSINTFP
+#Other net   PACKAGE_PIN AC22     - VCCINT                    Bank 999 - VCC_PSINTFP
+#Other net   PACKAGE_PIN AB25     - VCCINT                    Bank 999 - VCC_PSINTFP_DDR
+#Other net   PACKAGE_PIN AC24     - VCCINT                    Bank 999 - VCC_PSINTFP_DDR
+#Other net   PACKAGE_PIN AC25     - VCCINT                    Bank 999 - VCC_PSINTFP_DDR
+#Other net   PACKAGE_PIN AA22     - VCCINT                    Bank 999 - VCC_PSINTLP
+#Other net   PACKAGE_PIN V22      - VCCINT                    Bank 999 - VCC_PSINTLP
+#Other net   PACKAGE_PIN W21      - VCCINT                    Bank 999 - VCC_PSINTLP
+#Other net   PACKAGE_PIN W22      - VCCINT                    Bank 999 - VCC_PSINTLP
+#Other net   PACKAGE_PIN Y21      - VCCINT                    Bank 999 - VCC_PSINTLP
+#Other net   PACKAGE_PIN Y22      - VCCINT                    Bank 999 - VCC_PSINTLP
+#Other net   PACKAGE_PIN V24      - MGT1V2                    Bank 999 - VCC_PSPLL
+#Other net   PACKAGE_PIN W24      - MGT1V2                    Bank 999 - VCC_PSPLL
+#Other net   PACKAGE_PIN Y24      - MGT1V2                    Bank 999 - VCC_PSPLL
+#Other net   PACKAGE_PIN AD21     - VCCINT_VCU                Bank 999 - VCCINT_VCU
+#Other net   PACKAGE_PIN AD22     - VCCINT_VCU                Bank 999 - VCCINT_VCU
+#Other net   PACKAGE_PIN AD23     - VCCINT_VCU                Bank 999 - VCCINT_VCU
+#Other net   PACKAGE_PIN AD24     - VCCINT_VCU                Bank 999 - VCCINT_VCU
+
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_0]
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_1]
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_2]
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_3]
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_4]
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_5]
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_6]
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_7]
+#set_property PACKAGE_PIN G8 [get_ports PMOD0_0]
+#set_property PACKAGE_PIN H8 [get_ports PMOD0_1]
+#set_property PACKAGE_PIN G7 [get_ports PMOD0_2]
+#set_property PACKAGE_PIN H7 [get_ports PMOD0_3]
+#set_property PACKAGE_PIN G6 [get_ports PMOD0_4]
+#set_property PACKAGE_PIN H6 [get_ports PMOD0_5]
+#set_property PACKAGE_PIN J6 [get_ports PMOD0_6]
+#set_property PACKAGE_PIN J7 [get_ports PMOD0_7]
+#set_property PULLUP true [get_ports PMOD0_2]
+#set_property PULLUP true [get_ports PMOD0_3]
+#set_property PULLUP true [get_ports PMOD0_4]
+#set_property PULLUP true [get_ports PMOD0_5]
+#set_property PULLUP true [get_ports PMOD0_6]
+#set_property PULLUP true [get_ports PMOD0_7]
+
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_0]
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_1]
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_2]
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_3]
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_4]
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_5]
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_6]
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_7]
+#set_property PACKAGE_PIN J9  [get_ports PMOD1_0]
+#set_property PACKAGE_PIN K9  [get_ports PMOD1_1]
+#set_property PACKAGE_PIN K8  [get_ports PMOD1_2]
+#set_property PACKAGE_PIN L8  [get_ports PMOD1_3]
+#set_property PACKAGE_PIN L10 [get_ports PMOD1_4]
+#set_property PACKAGE_PIN M10 [get_ports PMOD1_5]
+#set_property PACKAGE_PIN M8  [get_ports PMOD1_6]
+#set_property PACKAGE_PIN M9  [get_ports PMOD1_7]
+
+#set_property PULLUP true [get_ports PMOD1_7]
+#set_property PULLUP true [get_ports PMOD1_6]
+#set_property PULLUP true [get_ports PMOD1_5]
+#set_property PULLUP true [get_ports PMOD1_4]
+#set_property PULLUP true [get_ports PMOD1_3]
+#set_property PULLUP true [get_ports PMOD1_2]
+#set_property PULLUP true [get_ports PMOD1_1]
+#set_property PULLUP true [get_ports PMOD1_0]
+
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[0]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[1]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[2]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[3]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[4]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[5]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[6]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[7]} ]
+#set_property PACKAGE_PIN G8 [get_ports {P0[0]} ]
+#set_property PACKAGE_PIN H8 [get_ports {P0[1]} ]
+#set_property PACKAGE_PIN G7 [get_ports {P0[2]} ]
+#set_property PACKAGE_PIN H7 [get_ports {P0[3]} ]
+#set_property PACKAGE_PIN G6 [get_ports {P0[4]} ]
+#set_property PACKAGE_PIN H6 [get_ports {P0[5]} ]
+#set_property PACKAGE_PIN J6 [get_ports {P0[6]} ]
+#set_property PACKAGE_PIN J7 [get_ports {P0[7]} ]
+set_property PULLUP true [get_ports {P0[2]} ]
+set_property PULLUP true [get_ports {P0[3]} ]
+set_property PULLUP true [get_ports {P0[4]} ]
+set_property PULLUP true [get_ports {P0[5]} ]
+set_property PULLUP true [get_ports {P0[6]} ]
+set_property PULLUP true [get_ports {P0[7]} ]
+
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[0]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[1]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[2]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[3]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[4]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[5]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[6]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[7]} ]
+#set_property PACKAGE_PIN J9  [get_ports {P1[0]} ]
+#set_property PACKAGE_PIN K9  [get_ports {P1[1]} ]
+#set_property PACKAGE_PIN K8  [get_ports {P1[2]} ]
+#set_property PACKAGE_PIN L8  [get_ports {P1[3]} ]
+#set_property PACKAGE_PIN L10 [get_ports {P1[4]} ]
+#set_property PACKAGE_PIN M10 [get_ports {P1[5]} ]
+#set_property PACKAGE_PIN M8  [get_ports {P1[6]} ]
+#set_property PACKAGE_PIN M9  [get_ports {P1[7]} ]
+
+set_property PULLUP true [get_ports {P1[7]} ]
+set_property PULLUP true [get_ports {P1[6]} ]
+set_property PULLUP true [get_ports {P1[5]} ]
+set_property PULLUP true [get_ports {P1[4]} ]
+set_property PULLUP true [get_ports {P1[3]} ]
+set_property PULLUP true [get_ports {P1[2]} ]
+set_property PULLUP true [get_ports {P1[1]} ]
+set_property PULLUP true [get_ports {P1[0]} ]
+
+#PMODA pin0 to FTCLK
+set_property PACKAGE_PIN K9 [get_ports {P1[1]}]
+
+#PMODA pin1 to FTSSN
+set_property PACKAGE_PIN L8 [get_ports {P1[3]}]
+
+#PMODA pin2 to FTMISO
+set_property PACKAGE_PIN J9 [get_ports {P1[0]}]
+
+#PMODA pin3 to FTMIOSIO
+set_property PACKAGE_PIN K8 [get_ports {P1[2]}]
+
+#PMODB pin1 to SWDIOTMS
+set_property PACKAGE_PIN G8 [get_ports SWDIOTMS]
+
+#PMODB pin4 to SWCLKTCK
+set_property PACKAGE_PIN H7 [get_ports SWCLKTCK]
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets uPAD_SWDCLK_I/IOBUF3V3/O]
+
+#PMODA pin4 : UART2RXD
+#PMODA pin4 : UART2TXD
+
+
+# LED0 to P0[0]
+set_property PACKAGE_PIN D5 [get_ports {P0[0]}]
+# LED1 to P0[1]
+set_property PACKAGE_PIN D6 [get_ports {P0[1]}]
+# LED2 to P0[2]
+set_property PACKAGE_PIN A5 [get_ports {P0[2]}]
+# LED3 to P0[3]
+set_property PACKAGE_PIN B5 [get_ports {P0[3]}]
+
+# SW0 to NRST (Down for active low)
+set_property PACKAGE_PIN B4 [get_ports NRST]
+
+# CLK125MHz (need dvider)
+set_property IOSTANDARD LVCMOS18 [get_ports XTAL1 ]
+set_property PACKAGE_PIN F23 [get_ports XTAL1]
+
+
+## auto mapped - to remap
+set_property PACKAGE_PIN C4 [get_ports {P0[10]}]
+set_property PACKAGE_PIN C3 [get_ports {P0[11]}]
+set_property PACKAGE_PIN B3 [get_ports {P0[12]}]
+set_property PACKAGE_PIN D2 [get_ports {P0[13]}]
+set_property PACKAGE_PIN C2 [get_ports {P0[14]}]
+set_property PACKAGE_PIN E3 [get_ports {P0[15]}]
+set_property PACKAGE_PIN F6 [get_ports {P0[4]}]
+set_property PACKAGE_PIN E5 [get_ports {P0[5]}]
+set_property PACKAGE_PIN F5 [get_ports {P0[6]}]
+set_property PACKAGE_PIN F4 [get_ports {P0[7]}]
+set_property PACKAGE_PIN E4 [get_ports {P0[8]}]
+set_property PACKAGE_PIN D4 [get_ports {P0[9]}]
+set_property PACKAGE_PIN M10 [get_ports {P1[10]}]
+set_property PACKAGE_PIN L10 [get_ports {P1[11]}]
+set_property PACKAGE_PIN M9 [get_ports {P1[12]}]
+set_property PACKAGE_PIN M8 [get_ports {P1[13]}]
+set_property PACKAGE_PIN N11 [get_ports {P1[14]}]
+set_property PACKAGE_PIN M11 [get_ports {P1[15]}]
+set_property PACKAGE_PIN H8 [get_ports {P1[4]}]
+set_property PACKAGE_PIN G7 [get_ports {P1[5]}]
+set_property PACKAGE_PIN H6 [get_ports {P1[6]}]
+set_property PACKAGE_PIN G6 [get_ports {P1[7]}]
+set_property PACKAGE_PIN J7 [get_ports {P1[8]}]
+set_property PACKAGE_PIN J6 [get_ports {P1[9]}]
+set_property PACKAGE_PIN E2 [get_ports VDD]
+set_property PACKAGE_PIN A3 [get_ports VDDIO]
+set_property PACKAGE_PIN A2 [get_ports VSS]
+set_property PACKAGE_PIN C1 [get_ports VSSIO]
+set_property PACKAGE_PIN B1 [get_ports XTAL2]
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_zcu104/fpga_synth.tcl b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_zcu104/fpga_synth.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..3efad9bc098849601d9112461fb08f29f0d3a7dc
--- /dev/null
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_zcu104/fpga_synth.tcl
@@ -0,0 +1 @@
+synth_design -top cmsdk_mcu_chip -part xczu7ev-ffvc1156-2-e
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_zcu104/fpga_timing.xdc b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_zcu104/fpga_timing.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..b93d2f8531fa39a7c455d065bcbd564bfd606b1b
--- /dev/null
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/target_fpga_zcu104/fpga_timing.xdc
@@ -0,0 +1,95 @@
+##################################################################################
+##                                                                              ##
+## ZYNQ timing XDC                                                              ##
+##                                                                              ##
+##################################################################################
+
+create_clock -name CLK -period 30 [get_ports XTAL1]
+create_clock -name VCLK -period 30 -waveform {5 20}
+
+create_clock -name SWCLK -period 60 [get_ports SWCLKTCK]
+create_clock -name VSWCLK -period 60 -waveform {5 35}
+
+set_clock_groups -name async_clk_swclock -asynchronous \
+-group [get_clocks -include_generated_clocks CLK] \
+-group [get_clocks -include_generated_clocks VSWCLK]
+
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports {dip_switch_4bits_tri_i[*]}]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports {dip_switch_4bits_tri_i[*]}]
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_2]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports PMOD0_2]
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_3]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports PMOD0_3]
+#set_output_delay -clock [get_clocks clk_pl_0] -min -add_delay 5.000 [get_ports {led_4bits_tri_o[*]}]
+#set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {led_4bits_tri_o[*]}]
+
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P0[0]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[0]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P0[1]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[1]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P0[2]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[2]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P0[3]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[3]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P0[4]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[4]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P0[5]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[5]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P0[6]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[6]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P0[7]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[7]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P0[8]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[8]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P0[9]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[9]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P0[10]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[10]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P0[11]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[11]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P0[12]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[12]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P0[13]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[13]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P0[14]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[14]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P0[15]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[15]}]
+
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P1[0]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[0]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P1[1]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[1]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P1[2]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[2]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P1[3]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[3]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P1[4]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[4]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P1[5]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[5]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P1[6]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[6]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P1[7]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[7]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P1[8]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[8]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P1[9]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[9]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P1[10]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[10]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P1[11]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[11]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P1[12]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[12]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P1[13]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[13]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P1[14]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[14]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay  5.000 [get_ports {P1[15]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[15]}]
+
+#set_property C_CLK_INPUT_FREQ_HZ 5000000 [get_debug_cores dbg_hub]
+#set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+#set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+#connect_debug_port dbg_hub/clk [get_nets clk]
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/v2html_doc.tgz b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/v2html_doc.tgz
index 64a53d2a0ae16bb11179ff28ddd5ceadcec49747..aa9c831d92b81ab61e1db1a36126c6a0bea9afac 100644
Binary files a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/v2html_doc.tgz and b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/v2html_doc.tgz differ
diff --git a/FPGALIB/pads/verilog/PAD_INOUT8MA_NOE.v b/FPGALIB/pads/verilog/PAD_INOUT8MA_NOE.v
new file mode 100644
index 0000000000000000000000000000000000000000..fa92fec42cf177510654b4a581f9af3749d38eef
--- /dev/null
+++ b/FPGALIB/pads/verilog/PAD_INOUT8MA_NOE.v
@@ -0,0 +1,37 @@
+// from GLIB_PADLIB.v
+//-----------------------------------------------------------------------------
+// soclabs generic IO pad model
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright © 2022, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module PAD_INOUT8MA_NOE (
+   // Inouts
+   PAD, 
+   // Outputs
+   I, 
+   // Inputs
+   O,
+   NOE
+   );
+   inout PAD;
+   output I;
+   input O;
+   input NOE;
+
+  IOBUF #(
+    .IOSTANDARD ("LVCMOS33"),
+    .DRIVE(8)
+  ) IOBUF3V3 (
+    .O(I),
+    .IO(PAD),
+    .I(O),
+    .T(NOE)
+  );
+    
+endmodule // PAD_INOUT8MA_NOE
diff --git a/FPGALIB/pads/verilog/PAD_VDDIO.v b/FPGALIB/pads/verilog/PAD_VDDIO.v
new file mode 100644
index 0000000000000000000000000000000000000000..4fd7137e498cde9cef4ac9785cdef6d08349e69a
--- /dev/null
+++ b/FPGALIB/pads/verilog/PAD_VDDIO.v
@@ -0,0 +1,29 @@
+// from GLIB_PADLIB.v
+//-----------------------------------------------------------------------------
+// soclabs generic IO pad model
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright © 2022, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module PAD_VDDIO (
+   // Inouts
+   PAD
+   );
+   inout PAD;
+
+  IOBUF #(
+    .IOSTANDARD ("LVCMOS33"),
+    .DRIVE(8)
+  ) IOBUF3V3 (
+    .O( ),
+    .IO(PAD),
+    .I(1'b1),
+    .T(1'b1)
+  );
+   
+endmodule // PAD_VDDIO
diff --git a/FPGALIB/pads/verilog/PAD_VDDSOC.v b/FPGALIB/pads/verilog/PAD_VDDSOC.v
new file mode 100644
index 0000000000000000000000000000000000000000..80f6a7200ee52de65784474c930ba65f8a9059be
--- /dev/null
+++ b/FPGALIB/pads/verilog/PAD_VDDSOC.v
@@ -0,0 +1,29 @@
+// from GLIB_PADLIB.v
+//-----------------------------------------------------------------------------
+// soclabs generic IO pad model
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright © 2022, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module PAD_VDDSOC (
+   // Inouts
+   PAD
+   );
+   inout PAD;
+
+  IOBUF #(
+    .IOSTANDARD ("LVCMOS33"),
+    .DRIVE(8)
+  ) IOBUF3V3 (
+    .O( ),
+    .IO(PAD),
+    .I(1'b1),
+    .T(1'b1)
+  );
+    
+endmodule // PAD_VDDSOC
diff --git a/FPGALIB/pads/verilog/PAD_VSS.v b/FPGALIB/pads/verilog/PAD_VSS.v
new file mode 100644
index 0000000000000000000000000000000000000000..046a389e5e39745459318e03888398083d2da29e
--- /dev/null
+++ b/FPGALIB/pads/verilog/PAD_VSS.v
@@ -0,0 +1,29 @@
+// from GLIB_PADLIB.v
+//-----------------------------------------------------------------------------
+// soclabs generic IO pad model
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright © 2022, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module PAD_VSS (
+   // Inouts
+   PAD
+   );
+   inout PAD;
+
+  IOBUF #(
+    .IOSTANDARD ("LVCMOS33"),
+    .DRIVE(8)
+  ) IOBUF3V3 (
+    .O( ),
+    .IO(PAD),
+    .I(1'b1),
+    .T(1'b1)
+  );
+    
+endmodule // PAD_VSS
diff --git a/FPGALIB/pads/verilog/PAD_VSSIO.v b/FPGALIB/pads/verilog/PAD_VSSIO.v
new file mode 100644
index 0000000000000000000000000000000000000000..6bfb333db8746e7658ad4e719462e68538d60732
--- /dev/null
+++ b/FPGALIB/pads/verilog/PAD_VSSIO.v
@@ -0,0 +1,29 @@
+// from GLIB_PADLIB.v
+//-----------------------------------------------------------------------------
+// soclabs generic IO pad model
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright © 2022, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module PAD_VSSIO (
+   // Inouts
+   PAD
+   );
+   inout PAD;
+
+  IOBUF #(
+    .IOSTANDARD ("LVCMOS33"),
+    .DRIVE(8)
+  ) IOBUF3V3 (
+    .O( ),
+    .IO(PAD),
+    .I(1'b1),
+    .T(1'b1)
+  );
+    
+endmodule // PAD_VSSIO