From 0df464955141aba3190b08e5c5cb9a49fd40b7e6 Mon Sep 17 00:00:00 2001
From: dwf1m12 <d.w.flynn@soton.ac.uk>
Date: Fri, 21 Jan 2022 16:42:14 +0000
Subject: [PATCH] cut down Flash and SRAM sizes to still run larger testcode
images
---
.../systems/cortex_m0_mcu/verilog/cmsdk_mcu.v | 19 +++++++++++--------
.../cortex_m0_mcu/verilog/cmsdk_mcu_chip.v | 12 +++++++-----
2 files changed, 18 insertions(+), 13 deletions(-)
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu.v b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu.v
index 2f097e3..1aeb28f 100644
--- a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu.v
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu.v
@@ -745,9 +745,9 @@ module cmsdk_mcu #(
//----------------------------------------
cmsdk_ahb_rom
#(.MEM_TYPE(ROM_MEM_TYPE),
-/// .AW(16), // 64K bytes flash ROM
-// .AW(13), // 8K bytes flash ROM -Dhry
- .AW(10), // 1K bytes flash ROM - Hello
+// .AW(16), // 64K bytes flash ROM
+ .AW(13), // 8K bytes flash ROM -Dhry
+// .AW(10), // 1K bytes flash ROM - Hello
.filename("image.hex"),
.WS_N(`ARM_CMSDK_ROM_MEM_WS_N),
.WS_S(`ARM_CMSDK_ROM_MEM_WS_S),
@@ -756,9 +756,9 @@ cmsdk_ahb_rom
.HCLK (HCLKSYS),
.HRESETn (HRESETn),
.HSEL (flash_hsel), // AHB inputs
-/// .HADDR (HADDR[15:0]),
-// .HADDR (HADDR[12:0]),
- .HADDR (HADDR[ 9:0]),
+// .HADDR (HADDR[15:0]),
+ .HADDR (HADDR[12:0]),
+// .HADDR (HADDR[ 9:0]),
.HTRANS (HTRANS),
.HSIZE (HSIZE),
.HWRITE (HWRITE),
@@ -793,6 +793,7 @@ ahb_bootrom__mangled
.HRDATA (boot_hrdata),
.HRESP (boot_hresp)
);
+
`else
// Only use if BOOT_MEM_TYPE is not zero
cmsdk_ahb_rom
@@ -827,7 +828,8 @@ cmsdk_ahb_rom
cmsdk_ahb_ram
#(.MEM_TYPE(RAM_MEM_TYPE),
/// .AW(16), // 64K bytes SRAM
- .AW( 9), // 1K bytes SRAM
+ .AW(10), // 1K bytes SRAM
+// .AW( 9), // 512 bytes SRAM
.WS_N(`ARM_CMSDK_RAM_MEM_WS_N),
.WS_S(`ARM_CMSDK_RAM_MEM_WS_S))
u_ahb_ram (
@@ -835,7 +837,8 @@ cmsdk_ahb_ram
.HRESETn (HRESETn),
.HSEL (sram_hsel), // AHB inputs
/// .HADDR (HADDR[15:0]),
- .HADDR (HADDR[ 8:0]),
+ .HADDR (HADDR[ 9:0]),
+// .HADDR (HADDR[ 8:0]),
.HTRANS (HTRANS),
.HSIZE (HSIZE),
.HWRITE (HWRITE),
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_chip.v b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_chip.v
index c966601..7a840f7 100644
--- a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_chip.v
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_chip.v
@@ -1119,7 +1119,7 @@ PAD_INOUT8MA_NOE uPAD_P1_15 (
cmsdk_ahb_rom
#(.MEM_TYPE(ROM_MEM_TYPE),
.AW(16), // 64K bytes flash ROM
-// .AW(13), // 8K bytes flash ROM -Dhry
+// .AW(15), // 32K bytes flash ROM -Dhry
// .AW(10), // 1K bytes flash ROM - Hello
.filename("image.hex"),
.WS_N(`ARM_CMSDK_ROM_MEM_WS_N),
@@ -1130,7 +1130,7 @@ cmsdk_ahb_rom
.HRESETn (HRESETn),
.HSEL (flash_hsel), // AHB inputs
.HADDR (HADDR[15:0]),
-// .HADDR (HADDR[12:0]),
+// .HADDR (HADDR[14:0]),
// .HADDR (HADDR[ 9:0]),
.HTRANS (HTRANS),
.HSIZE (HSIZE),
@@ -1200,15 +1200,17 @@ cmsdk_ahb_rom
//----------------------------------------
cmsdk_ahb_ram
#(.MEM_TYPE(RAM_MEM_TYPE),
- .AW(16), // 64K bytes SRAM
-// .AW( 9), // 1K bytes SRAM
+/// .AW(16), // 64K bytes SRAM
+ .AW(10), // 1K bytes SRAM
+// .AW( 9), // 512 bytes SRAM
.WS_N(`ARM_CMSDK_RAM_MEM_WS_N),
.WS_S(`ARM_CMSDK_RAM_MEM_WS_S))
u_ahb_ram (
.HCLK (HCLKSYS),
.HRESETn (HRESETn),
.HSEL (sram_hsel), // AHB inputs
- .HADDR (HADDR[15:0]),
+/// .HADDR (HADDR[15:0]),
+ .HADDR (HADDR[ 9:0]),
// .HADDR (HADDR[ 8:0]),
.HTRANS (HTRANS),
.HSIZE (HSIZE),
--
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