diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0/component.xml b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0/component.xml
index 3f9304c2d3b245ff2b885a7ab9711d551884c394..c9d8d6e573fef4d3a7f1d643e634a02f82032d93 100644
--- a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0/component.xml
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0/component.xml
@@ -1,123 +1,9 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>soclabs.org</spirit:vendor>
- <spirit:library>user</spirit:library>
- <spirit:name>ft1248x1_to_stream8</spirit:name>
+ <spirit:library>ip</spirit:library>
+ <spirit:name>ft1248x1_to_stream8_1.0</spirit:name>
<spirit:version>1.0</spirit:version>
- <spirit:busInterfaces>
- <spirit:busInterface>
- <spirit:name>resetn</spirit:name>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
- <spirit:slave/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RST</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>resetn</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>POLARITY</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.RESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>clk</spirit:name>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
- <spirit:slave/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>CLK</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>clk</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_RESET</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET">resetn</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_BUSIF</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF">txd:rxd</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>txd</spirit:name>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
- <spirit:master/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TDATA</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>txd_tdata8_o</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TVALID</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>txd_tvalid_o</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TREADY</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>txd_tready_i</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>rxd</spirit:name>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
- <spirit:slave/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TDATA</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>rxd_tdata8_i</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TVALID</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>rxd_tvalid_i</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TREADY</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>rxd_tready_o</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- </spirit:busInterface>
- </spirit:busInterfaces>
<spirit:model>
<spirit:views>
<spirit:view>
@@ -125,7 +11,6 @@
<spirit:displayName>Synthesis</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
- <spirit:modelName>ft1248x1_to_stream8</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
</spirit:fileSetRef>
@@ -141,7 +26,6 @@
<spirit:displayName>Simulation</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
- <spirit:modelName>ft1248x1_to_stream8</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
</spirit:fileSetRef>
@@ -152,254 +36,21 @@
</spirit:parameter>
</spirit:parameters>
</spirit:view>
- <spirit:view>
- <spirit:name>xilinx_xpgui</spirit:name>
- <spirit:displayName>UI Layout</spirit:displayName>
- <spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
- <spirit:fileSetRef>
- <spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
- </spirit:fileSetRef>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>viewChecksum</spirit:name>
- <spirit:value>f92e9879</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:view>
- <spirit:view>
- <spirit:name>archive_project</spirit:name>
- <spirit:displayName>Miscellaneous</spirit:displayName>
- <spirit:envIdentifier>:vivado.xilinx.com:misc.files</spirit:envIdentifier>
- <spirit:fileSetRef>
- <spirit:localName>archive_project_view_fileset</spirit:localName>
- </spirit:fileSetRef>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>viewChecksum</spirit:name>
- <spirit:value>119b3fd8</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:view>
</spirit:views>
- <spirit:ports>
- <spirit:port>
- <spirit:name>ft_clk_i</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>ft_ssn_i</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>ft_miso_o</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>ft_miosio_i</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>ft_miosio_o</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>ft_miosio_z</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>clk</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>resetn</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>txd_tvalid_o</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>txd_tdata8_o</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left spirit:format="long">7</spirit:left>
- <spirit:right spirit:format="long">0</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>txd_tready_i</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- <spirit:driver>
- <spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
- </spirit:driver>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>rxd_tready_o</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>rxd_tdata8_i</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left spirit:format="long">7</spirit:left>
- <spirit:right spirit:format="long">0</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- <spirit:driver>
- <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
- </spirit:driver>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>rxd_tvalid_i</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- </spirit:ports>
</spirit:model>
- <spirit:choices>
- <spirit:choice>
- <spirit:name>choice_list_9d8b0d81</spirit:name>
- <spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
- <spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
- </spirit:choice>
- </spirit:choices>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
<spirit:file>
<spirit:name>src/synclib.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
- <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+ <spirit:logicalName>ft1248x1_to_stream8_1.0</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>src/ft1248x1_to_stream8.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_06e9a745</spirit:userFileType>
- <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+ <spirit:logicalName>ft1248x1_to_stream8_1.0</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
@@ -407,83 +58,70 @@
<spirit:file>
<spirit:name>src/synclib.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
- <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+ <spirit:logicalName>ft1248x1_to_stream8_1.0</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>src/ft1248x1_to_stream8.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
- <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
- </spirit:file>
- </spirit:fileSet>
- <spirit:fileSet>
- <spirit:name>xilinx_xpgui_view_fileset</spirit:name>
- <spirit:file>
- <spirit:name>xgui/ft1248x1_to_stream8_v1_0.tcl</spirit:name>
- <spirit:fileType>tclSource</spirit:fileType>
- <spirit:userFileType>CHECKSUM_f92e9879</spirit:userFileType>
- <spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
- </spirit:file>
- </spirit:fileSet>
- <spirit:fileSet>
- <spirit:name>archive_project_view_fileset</spirit:name>
- <spirit:file>
- <spirit:name>ip_project_archive.zip</spirit:name>
- <spirit:userFileType>zip</spirit:userFileType>
+ <spirit:logicalName>ft1248x1_to_stream8_1.0</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
- <spirit:description>ft1248x1_to_stream8_v1_0</spirit:description>
+ <spirit:description>ft1248x1_to_stream8_1.0:1.0</spirit:description>
<spirit:parameters>
<spirit:parameter>
<spirit:name>Component_Name</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">ft1248x1_to_stream8_v1_0</spirit:value>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">ft1248x1_to_stream8_1_0_v1_0</spirit:value>
</spirit:parameter>
</spirit:parameters>
<spirit:vendorExtensions>
<xilinx:coreExtensions>
- <xilinx:supportedFamilies>
- <xilinx:family xilinx:lifeCycle="Production">zynquplus</xilinx:family>
- </xilinx:supportedFamilies>
<xilinx:taxonomies>
- <xilinx:taxonomy>/UserIP</xilinx:taxonomy>
+ <xilinx:taxonomy>/AXI_Infrastructure</xilinx:taxonomy>
+ <xilinx:taxonomy>/Debug_&_Verification/Debug</xilinx:taxonomy>
+ <xilinx:taxonomy>/Embedded_Processing/Debug_&_Verification/Debug</xilinx:taxonomy>
</xilinx:taxonomies>
- <xilinx:displayName>ft1248x1_to_stream8_v1_0</xilinx:displayName>
+ <xilinx:displayName>ft1248x1_to_stream8_1.0_v1_0</xilinx:displayName>
+ <xilinx:hideInCatalogGUI>true</xilinx:hideInCatalogGUI>
<xilinx:definitionSource>package_project</xilinx:definitionSource>
- <xilinx:vendorDisplayName>soclabs</xilinx:vendorDisplayName>
+ <xilinx:vendorDisplayName>soclabs.org</xilinx:vendorDisplayName>
<xilinx:vendorURL>http://soclabs.org</xilinx:vendorURL>
- <xilinx:coreRevision>3</xilinx:coreRevision>
- <xilinx:coreCreationDateTime>2022-08-02T14:30:20Z</xilinx:coreCreationDateTime>
+ <xilinx:coreRevision>1</xilinx:coreRevision>
+ <xilinx:upgrades>
+ <xilinx:canUpgradeFrom>xilinx.com:ip:ft1248x1_to_stream8_1.0:1.0</xilinx:canUpgradeFrom>
+ </xilinx:upgrades>
+ <xilinx:coreCreationDateTime>2022-08-18T13:41:50Z</xilinx:coreCreationDateTime>
<xilinx:tags>
- <xilinx:tag xilinx:name="ui.data.coregen.df@5518b824_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
- <xilinx:tag xilinx:name="ui.data.coregen.df@dd6b747_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
- <xilinx:tag xilinx:name="ui.data.coregen.df@1dd36a4a_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
- <xilinx:tag xilinx:name="ui.data.coregen.df@382bd830_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
- <xilinx:tag xilinx:name="ui.data.coregen.df@6aeff378_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
- <xilinx:tag xilinx:name="ui.data.coregen.df@68b65f1b_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
- <xilinx:tag xilinx:name="ui.data.coregen.df@6385c4eb_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
- <xilinx:tag xilinx:name="ui.data.coregen.df@16b128f7_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
- <xilinx:tag xilinx:name="ui.data.coregen.df@744eb339_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
- <xilinx:tag xilinx:name="ui.data.coregen.df@341d42a_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
- <xilinx:tag xilinx:name="ui.data.coregen.df@119532b1_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
- <xilinx:tag xilinx:name="ui.data.coregen.df@6244a695_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
- <xilinx:tag xilinx:name="ui.data.coregen.df@5677e373_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
- <xilinx:tag xilinx:name="ui.data.coregen.df@42f085dd_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
- <xilinx:tag xilinx:name="ui.data.coregen.df@7de75687_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
- <xilinx:tag xilinx:name="ui.data.coregen.df@7e5d266a_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
- <xilinx:tag xilinx:name="ui.data.coregen.df@75402bf4_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
- <xilinx:tag xilinx:name="ui.data.coregen.df@71bb76b3_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
- <xilinx:tag xilinx:name="ui.data.coregen.df@23e5a153_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
- <xilinx:tag xilinx:name="ui.data.coregen.df@861dc68_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
- <xilinx:tag xilinx:name="ui.data.coregen.df@5d40693a_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
- <xilinx:tag xilinx:name="ui.data.coregen.df@7771d989_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@554a8be0_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@2c2e0f51_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@4bf8650c_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@50a2d20f_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@679c5188_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@61453e2b_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@20d8eb40_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@9d02819_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@1f726801_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@7d50b16d_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@558791b8_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@dade147_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@50c7becf_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@134862eb_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@4c308b0f_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@174caa76_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@33e02927_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@1bc1eca_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@247a24c1_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@7f189307_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@4fc3a402_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@62f43e05_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@7f223669_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@77281e8f_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
</xilinx:tags>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2021.1</xilinx:xilinxVersion>
- <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="ba903ffc"/>
- <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="198bf64b"/>
- <xilinx:checksum xilinx:scope="ports" xilinx:value="ad10c1dd"/>
- <xilinx:checksum xilinx:scope="parameters" xilinx:value="736a069e"/>
+ <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="8af10ea9"/>
+ <xilinx:checksum xilinx:scope="parameters" xilinx:value="f93808b1"/>
</xilinx:packagingInfo>
</spirit:vendorExtensions>
</spirit:component>