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//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited.
//
// (C) COPYRIGHT 2006-2007 ARM Limited.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited.
//
// File Name  : pl230_apb_regs.v
// Checked In : $Date: 2007-03-15 15:17:04 +0530 (Thu, 15 Mar 2007) $
// Revision   : $Revision: 10866 $
// State      : $state: PL230-DE-98007-r0p0-02rel0 $
//
//-----------------------------------------------------------------------------
// Purpose : APB slave interface memory mapped registers
//
//-----------------------------------------------------------------------------

`include "pl230_defs.v"

[Up: pl230_udma u_pl230_apb_regs]
module pl230_apb_regsIndex (
  // Clock and Reset
  hclk,
  hresetn,
  // APB Slave Interface
  pclken,
  psel,
  pen,
  pwrite,
  paddr,
  pwdata,
  prdata,
  // Memory Mapped Registers
  //  Controller Configuration Registers
  dma_waitonreq,
  dma_err,
  ctrl_base_ptr,
  chnl_sw_request,
  chnl_useburst_status,
  chnl_req_mask_status,
  chnl_enable_status,
  chnl_pri_alt_status,
  chnl_priority_status,
  //  Integration Registers
  dma_stall,
  dma_req,
  dma_sreq,
  dma_done_status,
  dma_active_status,
  int_test_en,
  // Register Control
  ctrl_state,
  clr_useburst,
  set_useburst,
  toggle_channel,
  disable_channel,
  data_current_chnl_onehot,
  slave_err,
  master_enable,
  chnl_ctrl_hprot3to1
  );

  //----------------------------------------------------------------------------
  // Port declarations
  //----------------------------------------------------------------------------
  // Clock and Reset
  input                     hclk;                 // AMBA bus clock
  input                     hresetn;              // AMBA bus reset
  // APB Slave Interface
  input                     pclken;               // APB clock enable
  input                     psel;                 // APB peripheral select
  input                     pen;                  // APB transfer enable
  input                     pwrite;               // APB transfer direction
  input  [11:0]             paddr;                // APB address
  input  [31:0]             pwdata;               // APB write data
  output [31:0]             prdata;               // APB read data

  // Memory Mapped Registers
  //  Controller Configuration Registers
  input  [`PL230_CHNLS-1:0] dma_waitonreq;        // dma_waitonreq input status
  output                    dma_err;              // interrupt status
  output [31-1-`PL230_CHNL_BITS-2-2:0]
                            ctrl_base_ptr;        // control data base pointer
  output [`PL230_CHNLS-1:0] chnl_sw_request;      // channel software request
  output [`PL230_CHNLS-1:0] chnl_useburst_status; // channel use bursts status
  output [`PL230_CHNLS-1:0] chnl_req_mask_status; // channel request mask status
  output [`PL230_CHNLS-1:0] chnl_enable_status;   // channel enable status
  output [`PL230_CHNLS-1:0] chnl_pri_alt_status;  // channel primary/alternate
  output [`PL230_CHNLS-1:0] chnl_priority_status; // channel priority status
  //  Integration Registers
  input                     dma_stall;            // dma_stall input status
  input  [`PL230_CHNLS-1:0] dma_req;              // dma_req input status
  input  [`PL230_CHNLS-1:0] dma_sreq;             // dma_sreq input status
  output [`PL230_CHNLS-1:0] dma_done_status;      // dma_done output status
  output [`PL230_CHNLS-1:0] dma_active_status;    // dma_active output status
  output                    int_test_en;          // integration test enable

  // Register Control
  input  [`PL230_STATE_BITS-1:0]
                            ctrl_state;           // AHB control state
  input                     clr_useburst;         // clear chnl_useburst_status
  input                     set_useburst;         // set chnl_useburst_status
  input                     toggle_channel;       // toggle current channel
  input                     disable_channel;      // disable current channel
  input  [`PL230_CHNLS-1:0] data_current_chnl_onehot;
                                                  // current channel (one hot)
  input                     slave_err;            // AHB slave response not OK
  output                    master_enable;        // master enable
  output [2:0]              chnl_ctrl_hprot3to1;  // hprot for chnl ctrl access

  //----------------------------------------------------------------------------
  // Port signal declarations
  //----------------------------------------------------------------------------
  // APB read data
  reg    [31:0]             prdata;

  // Memory Mapped Registers
  // Not all registers in the programmer's model are implemented as flip-flops
  // The '*_set' and '*_clr' registrers are virtual as they are write only and
  // modify the '*_status' registers.
  //  Controller Configuration Registers
  //   channel control data base pointer
  reg    [31-1-`PL230_CHNL_BITS-2-2:0]
                            ctrl_base_ptr;
  //   channel software request
  reg    [`PL230_CHNLS-1:0] chnl_sw_request;
  //   channel use bursts status
  reg    [`PL230_CHNLS-1:0] chnl_useburst_status;
  //   channel external request mask status
  reg    [`PL230_CHNLS-1:0] chnl_req_mask_status;
  //   channel enable status
  reg    [`PL230_CHNLS-1:0] chnl_enable_status;
  //   channel primary/alternate flag status
  reg    [`PL230_CHNLS-1:0] chnl_pri_alt_status;
  //   channel priority status
  reg    [`PL230_CHNLS-1:0] chnl_priority_status;
  //  Integration Registers
`ifdef PL230_INCLUDE_TEST
  //   integration test enable
  reg                       int_test_en;
  //   dma_done primary output status
  reg    [`PL230_CHNLS-1:0] dma_done_status;
  //   dma_active primary output status
  reg    [`PL230_CHNLS-1:0] dma_active_status;
`else
  //   integration test enable
  wire                      int_test_en;
  //   dma_done primary output status
  wire   [`PL230_CHNLS-1:0] dma_done_status;
  //   dma_active primary output status
  wire   [`PL230_CHNLS-1:0] dma_active_status;
`endif

  //----------------------------------------------------------------------------
  // Local signal declarations
  //----------------------------------------------------------------------------
  // Loop index for generating channel specific logic
  integer                   i;
  // Write register enable
  wire                      write_reg;
  // Set register decode
  wire                      set_reg;
  // Integration Test Logic Control
  wire                      include_test;

  // Memory mapped register addresses
  //  Controller Configuration Registers
  wire   [11:0]             addr_dma_status;
  wire   [11:0]             addr_dma_cfg;
  wire   [11:0]             addr_ctrl_base_ptr;
  wire   [11:0]             addr_alt_ctrl_base_ptr;
  wire   [11:0]             addr_dma_waitonreq_status;
  wire   [11:0]             addr_chnl_sw_request;
  wire   [11:0]             addr_chnl_useburst_set;
  wire   [11:0]             addr_chnl_useburst_clr;
  wire   [11:0]             addr_chnl_req_mask_set;
  wire   [11:0]             addr_chnl_req_mask_clr;
  wire   [11:0]             addr_chnl_enable_set;
  wire   [11:0]             addr_chnl_enable_clr;
  wire   [11:0]             addr_chnl_pri_alt_set;
  wire   [11:0]             addr_chnl_pri_alt_clr;
  wire   [11:0]             addr_chnl_priority_set;
  wire   [11:0]             addr_chnl_priority_clr;
  wire   [11:0]             addr_err_clr;
  //  Integration Test Registers
  wire   [11:0]             addr_integration_cfg;
  wire   [11:0]             addr_stall_status;
  wire   [11:0]             addr_dma_req_status;
  wire   [11:0]             addr_dma_sreq_status;
  wire   [11:0]             addr_dma_done_set;
  wire   [11:0]             addr_dma_done_clr;
  wire   [11:0]             addr_dma_active_set;
  wire   [11:0]             addr_dma_active_clr;
  wire   [11:0]             addr_err_set;
  //  PrimeCell Configuration Registers
  wire   [11:0]             addr_periph_id_4;
  wire   [11:0]             addr_periph_id_0;
  wire   [11:0]             addr_periph_id_1;
  wire   [11:0]             addr_periph_id_2;
  wire   [11:0]             addr_periph_id_3;
  wire   [11:0]             addr_pcell_id_0;
  wire   [11:0]             addr_pcell_id_1;
  wire   [11:0]             addr_pcell_id_2;
  wire   [11:0]             addr_pcell_id_3;

  // Register Write
  //  Register write enables
  //   dma controller configuration
  wire                      dma_cfg_wen;
  //   channel control data base pointer
  wire                      ctrl_base_ptr_wen;
  //   channel manual request
  wire                      chnl_sw_request_wen;
  //   channel use bursts status
  wire                      chnl_useburst_status_wen;
  //   channel external request mask status
  wire                      chnl_req_mask_status_wen;
  //   channel enable status
  wire                      chnl_enable_status_wen;
  //   channel primary/alternate flag status
  wire                      chnl_pri_alt_status_wen;
  //   channel priority status
  wire                      chnl_priority_status_wen;
  //   dma_err primary output status
  wire                      err_status_wen;
  //   integration test enable
  wire                      int_test_en_wen;
  //   dma_done primary output status
  wire                      dma_done_status_wen;
  //   dma_active primary output status
  wire                      dma_active_status_wen;
  //  Register write data
  //   dma controller configuration
  wire   [3:0]              dma_cfg_nxt;
  //   channel control data base pointer
  wire   [31-1-`PL230_CHNL_BITS-2-2:0]
                            ctrl_base_ptr_nxt;
  //   channel software request
  wire   [`PL230_CHNLS-1:0] chnl_sw_request_nxt;
  //   channel use bursts status
  reg    [`PL230_CHNLS-1:0] chnl_useburst_status_nxt;
  //   channel external request mask status
  wire   [`PL230_CHNLS-1:0] chnl_req_mask_status_nxt;
  //   channel enable status
  reg    [`PL230_CHNLS-1:0] chnl_enable_status_nxt;
  //   channel primary/alternate flag status
  reg    [`PL230_CHNLS-1:0] chnl_pri_alt_status_nxt;
  //   channel priority status
  wire   [`PL230_CHNLS-1:0] chnl_priority_status_nxt;
  //   dma_err primary output status
  wire                      err_status_nxt;
  //   integration test enable
  wire                      int_test_en_nxt;
  //   dma_done primary output status
  wire   [`PL230_CHNLS-1:0] dma_done_status_nxt;
  //   dma_active primary output status
  wire   [`PL230_CHNLS-1:0] dma_active_status_nxt;

  // Memory Mapped Register
  //   dma controller configuration
  reg    [3:0]              dma_cfg;
  //   dma_err primary output status
  reg                       err_status;

  // Register Read
  //  number of dma channels
  integer                   numberofchannels;
  //  dma controller status
  reg    [31:0]             dma_status;
  // Mask dma_stall when integration test logic not included
  wire                      test_dma_stall;
  // Mask dma_req when integration test logic not included
  wire  [`PL230_CHNLS-1:0]  test_dma_req;
  // Mask dma_sreq when integration test logic not included
  wire  [`PL230_CHNLS-1:0]  test_dma_sreq;


  //----------------------------------------------------------------------------
  //
  // Beginning of main code
  //
  //----------------------------------------------------------------------------

  // Control
  assign write_reg = (pclken && psel && pen && pwrite);

  // Address decode
  assign set_reg = (paddr[2] == 1'b0);

  // Integration Test Logic Control
`ifdef PL230_INCLUDE_TEST
  assign include_test = 1'b1;
`else
  assign include_test = 1'b0;
`endif

  // Memory mapped register addresses
  //  Controller Configuration Registers
  assign addr_dma_status           = `PL230_ADDR_DMA_STATUS;
  assign addr_dma_cfg              = `PL230_ADDR_DMA_CFG;
  assign addr_ctrl_base_ptr        = `PL230_ADDR_CTRL_BASE_PTR;
  assign addr_alt_ctrl_base_ptr    = `PL230_ADDR_ALT_CTRL_BASE_PTR;
  assign addr_dma_waitonreq_status = `PL230_ADDR_DMA_WAITONREQ_STATUS;
  assign addr_chnl_sw_request      = `PL230_ADDR_CHNL_SW_REQUEST;
  assign addr_chnl_useburst_set    = `PL230_ADDR_CHNL_USEBURST_SET;
  assign addr_chnl_useburst_clr    = `PL230_ADDR_CHNL_USEBURST_CLR;
  assign addr_chnl_req_mask_set    = `PL230_ADDR_CHNL_REQ_MASK_SET;
  assign addr_chnl_req_mask_clr    = `PL230_ADDR_CHNL_REQ_MASK_CLR;
  assign addr_chnl_enable_set      = `PL230_ADDR_CHNL_ENABLE_SET;
  assign addr_chnl_enable_clr      = `PL230_ADDR_CHNL_ENABLE_CLR;
  assign addr_chnl_pri_alt_set     = `PL230_ADDR_CHNL_PRI_ALT_SET;
  assign addr_chnl_pri_alt_clr     = `PL230_ADDR_CHNL_PRI_ALT_CLR;
  assign addr_chnl_priority_set    = `PL230_ADDR_CHNL_PRIORITY_SET;
  assign addr_chnl_priority_clr    = `PL230_ADDR_CHNL_PRIORITY_CLR;
  assign addr_err_clr              = `PL230_ADDR_ERR_CLR;
  //  Integration Test Registers
  assign addr_integration_cfg      = `PL230_ADDR_INTEGRATION_CFG;
  assign addr_stall_status         = `PL230_ADDR_STALL_STATUS;
  assign addr_dma_req_status       = `PL230_ADDR_DMA_REQ_STATUS;
  assign addr_dma_sreq_status      = `PL230_ADDR_DMA_SREQ_STATUS;
  assign addr_dma_done_set         = `PL230_ADDR_DMA_DONE_SET;
  assign addr_dma_done_clr         = `PL230_ADDR_DMA_DONE_CLR;
  assign addr_dma_active_set       = `PL230_ADDR_DMA_ACTIVE_SET;
  assign addr_dma_active_clr       = `PL230_ADDR_DMA_ACTIVE_CLR;
  assign addr_err_set              = `PL230_ADDR_ERR_SET;
  //  PrimeCell Configuration Registers
  assign addr_periph_id_4          = `PL230_ADDR_PERIPH_ID_4;
  assign addr_periph_id_0          = `PL230_ADDR_PERIPH_ID_0;
  assign addr_periph_id_1          = `PL230_ADDR_PERIPH_ID_1;
  assign addr_periph_id_2          = `PL230_ADDR_PERIPH_ID_2;
  assign addr_periph_id_3          = `PL230_ADDR_PERIPH_ID_3;
  assign addr_pcell_id_0           = `PL230_ADDR_PCELL_ID_0;
  assign addr_pcell_id_1           = `PL230_ADDR_PCELL_ID_1;
  assign addr_pcell_id_2           = `PL230_ADDR_PCELL_ID_2;
  assign addr_pcell_id_3           = `PL230_ADDR_PCELL_ID_3;

  //----------------------------------------------------------------------------
  // Register Write
  //----------------------------------------------------------------------------

  //----------------------------------------------------------------------------
  //  Register write enables
  //----------------------------------------------------------------------------
  assign dma_cfg_wen =
    (paddr[11:2] == addr_dma_cfg[11:2]) && write_reg;
  assign ctrl_base_ptr_wen =
    (paddr[11:2] == addr_ctrl_base_ptr[11:2]) && write_reg;
  assign chnl_sw_request_wen =
    ((paddr[11:2] == addr_chnl_sw_request[11:2]) && write_reg) ||
    |chnl_sw_request;
  assign chnl_useburst_status_wen =
    clr_useburst || set_useburst ||
    (write_reg && (paddr[11:3] == addr_chnl_useburst_set[11:3]));
  assign chnl_req_mask_status_wen =
    write_reg && (paddr[11:3] == addr_chnl_req_mask_set[11:3]);
  assign chnl_enable_status_wen =
    disable_channel ||
    (write_reg && (paddr[11:3] == addr_chnl_enable_set[11:3]));
  assign chnl_pri_alt_status_wen =
    toggle_channel ||
    (write_reg && (paddr[11:3] == addr_chnl_pri_alt_set[11:3]));
  assign chnl_priority_status_wen =
    write_reg && (paddr[11:3] == addr_chnl_priority_set[11:3]);
  assign err_status_wen =
    slave_err ||
    (write_reg &&
      ((int_test_en && (paddr[11:2] == addr_err_set[11:2])) ||
       (paddr[11:2] == addr_err_clr[11:2]))
    );
  assign int_test_en_wen =
    write_reg && (paddr[11:2] == addr_integration_cfg[11:2]);
  assign dma_done_status_wen =
    int_test_en && write_reg && (paddr[11:3] == addr_dma_done_set[11:3]);
  assign dma_active_status_wen =
    int_test_en && write_reg && (paddr[11:3] == addr_dma_active_set[11:3]);

  //----------------------------------------------------------------------------
  //  Register write data
  //----------------------------------------------------------------------------
  // dma controller configuration
  assign dma_cfg_nxt          = {pwdata[7:5],pwdata[0]};

  // channel control data base pointer
  assign ctrl_base_ptr_nxt    = pwdata[31:1+`PL230_CHNL_BITS+2+2];

  // channel software request
  assign chnl_sw_request_nxt  = ((paddr[11:2] == addr_chnl_sw_request[11:2])
                                 && write_reg)
                               ? pwdata[`PL230_CHNLS-1:0] // set
                               : {`PL230_CHNLS{1'b0}};    // clear immediately

  // channel use bursts status
  always @( set_useburst or clr_useburst or  data_current_chnl_onehot or
            write_reg or paddr or addr_chnl_useburst_set or set_reg or
            chnl_useburst_status or pwdata)
  begin : p_chnl_useburst_status_nxt
    for ( i = 0; i < `PL230_CHNLS; i=i+1 )
    begin
      chnl_useburst_status_nxt[i]  =
             (set_useburst & data_current_chnl_onehot[i])
             ? 1'b1                                                     // set
             : (clr_useburst & data_current_chnl_onehot[i])
             ? 1'b0                                                     // clr
             : (write_reg && (paddr[11:3] == addr_chnl_useburst_set[11:3]))
             ? (set_reg
                 ? (chnl_useburst_status[i] | pwdata[i])                // set
                 : (chnl_useburst_status[i] & ~pwdata[i]))              // clr
             : chnl_useburst_status[i];                                 // hold
    end
  end // p_chnl_useburst_status_nxt

  // channel external request mask status
  assign chnl_req_mask_status_nxt = set_reg
                   ? (chnl_req_mask_status | pwdata[`PL230_CHNLS-1:0])   // set
                   : (chnl_req_mask_status & ~pwdata[`PL230_CHNLS-1:0]); // clr

  // channel enable status
  always @( disable_channel or data_current_chnl_onehot or
            write_reg or paddr or addr_chnl_enable_set or set_reg or
            chnl_enable_status or pwdata)
  begin : p_chnl_enable_status_nxt
    for ( i = 0; i < `PL230_CHNLS; i=i+1 )
    begin
      chnl_enable_status_nxt[i] =
             (disable_channel & data_current_chnl_onehot[i])
             ? 1'b0                                                     // clr
             : (write_reg && (paddr[11:3] == addr_chnl_enable_set[11:3]))
             ? (set_reg
                 ? (chnl_enable_status[i] | pwdata[i])                  // set
                 : (chnl_enable_status[i] & ~pwdata[i]))                // clr
             : chnl_enable_status[i];                                   // hold
    end
  end // p_chnl_enable_status_nxt

  // channel primary/alternate flag status
  always @( toggle_channel or  data_current_chnl_onehot or
            write_reg or paddr or addr_chnl_pri_alt_set or set_reg or
            chnl_pri_alt_status or pwdata)
  begin : p_chnl_pri_alt_status_nxt
    for ( i = 0; i < `PL230_CHNLS; i=i+1 )
    begin
      chnl_pri_alt_status_nxt[i] =
             (toggle_channel & data_current_chnl_onehot[i])
             ? ~chnl_pri_alt_status[i]                                  // tgl
             : (write_reg && (paddr[11:3] == addr_chnl_pri_alt_set[11:3]))
             ? (set_reg
                 ? (chnl_pri_alt_status[i]  | pwdata[i])                // set
                 : (chnl_pri_alt_status[i]  & ~pwdata[i]))              // clr
             : chnl_pri_alt_status[i];
    end
  end // p_chnl_pri_alt_status_nxt

  // channel priority status
  assign chnl_priority_status_nxt = set_reg
                   ? (chnl_priority_status | pwdata[`PL230_CHNLS-1:0])   // set
                   : (chnl_priority_status & ~pwdata[`PL230_CHNLS-1:0]); // clr

  // dma_err primary output status
  assign err_status_nxt = slave_err ||
`ifdef PL230_INCLUDE_TEST
                   (set_reg
                    ? (err_status           | pwdata[0])                // set
                    : (err_status           & ~pwdata[0]));             // clr
`else
                     (err_status           & ~pwdata[0]);               // clr
`endif

  // integration test enable
  assign int_test_en_nxt = pwdata[0];

  // dma_done primary output status
  assign dma_done_status_nxt     = set_reg
                   ? (dma_done_status     | pwdata[`PL230_CHNLS-1:0])    // set
                   : (dma_done_status     & ~pwdata[`PL230_CHNLS-1:0]);  // clr

  // dma_active primary output status
  assign dma_active_status_nxt   = set_reg
                   ? (dma_active_status   | pwdata[`PL230_CHNLS-1:0])    // set
                   : (dma_active_status   & ~pwdata[`PL230_CHNLS-1:0]);  // clr

  //----------------------------------------------------------------------------
  //  Register write filp-flops
  //----------------------------------------------------------------------------

  // dma controller config
  always @( negedge hresetn or posedge hclk )
  begin : p_dma_cfg
    if ( hresetn == 1'b0 )
      dma_cfg <= 4'b0000;
    else
      if ( dma_cfg_wen )
        dma_cfg <= dma_cfg_nxt;
  end // p_dma_cfg

  // control data base pointer
  always @( negedge hresetn or posedge hclk )
  begin : p_ctrl_base_ptr
    if ( hresetn == 1'b0 )
      ctrl_base_ptr <= {32-1-`PL230_CHNL_BITS-2-2{1'b0}};
    else
      if ( ctrl_base_ptr_wen )
        ctrl_base_ptr <= ctrl_base_ptr_nxt;
  end // p_ctrl_base_ptr

  // channel software request
  always @( negedge hresetn or posedge hclk )
  begin : p_chnl_sw_request
    if ( hresetn == 1'b0 )
      chnl_sw_request <= {`PL230_CHNLS{1'b0}};
    else
      if ( chnl_sw_request_wen )
        chnl_sw_request <= chnl_sw_request_nxt;
  end // p_chnl_sw_request

  // channel use bursts status
  always @( negedge hresetn or posedge hclk )
  begin : p_chnl_useburst_status
    if ( hresetn == 1'b0 )
      chnl_useburst_status <= {`PL230_CHNLS{1'b0}};
    else
      if ( chnl_useburst_status_wen )
        chnl_useburst_status <= chnl_useburst_status_nxt;
  end // p_chnl_useburst_status

  // channel request mask status
  always @( negedge hresetn or posedge hclk )
  begin : p_chnl_req_mask_status
    if ( hresetn == 1'b0 )
      chnl_req_mask_status <= {`PL230_CHNLS{1'b0}};
    else
      if ( chnl_req_mask_status_wen )
        chnl_req_mask_status <= chnl_req_mask_status_nxt;
  end // p_chnl_req_mask_status

  // channel enable status
  always @( negedge hresetn or posedge hclk )
  begin : p_chnl_enable_status
    if ( hresetn == 1'b0 )
      chnl_enable_status <= {`PL230_CHNLS{1'b0}};
    else
      if ( chnl_enable_status_wen )
        chnl_enable_status <= chnl_enable_status_nxt;
  end // p_chnl_enable_status

  // channel primary/alternate status
  always @( negedge hresetn or posedge hclk )
  begin : p_chnl_pri_alt_status
    if ( hresetn == 1'b0 )
      chnl_pri_alt_status <= {`PL230_CHNLS{1'b0}};
    else
      if ( chnl_pri_alt_status_wen )
        chnl_pri_alt_status <= chnl_pri_alt_status_nxt;
  end // p_chnl_pri_alt_status

  // channel priority status
  always @( negedge hresetn or posedge hclk )
  begin : p_chnl_priority_status
    if ( hresetn == 1'b0 )
      chnl_priority_status <= {`PL230_CHNLS{1'b0}};
    else
      if ( chnl_priority_status_wen )
        chnl_priority_status <= chnl_priority_status_nxt;
  end // p_chnl_priority_status

  // interrupt status
  always @( negedge hresetn or posedge hclk )
  begin : p_err_status
    if ( hresetn == 1'b0 )
      err_status <= 1'b0;
    else
      if ( err_status_wen )
        err_status <= err_status_nxt;
  end // p_err_status

`ifdef PL230_INCLUDE_TEST
  // integration test enable
  always @( negedge hresetn or posedge hclk )
  begin : p_int_test_en
    if ( hresetn == 1'b0 )
      int_test_en <= 1'b0;
    else
      if ( int_test_en_wen )
        int_test_en <= int_test_en_nxt;
  end // p_int_test_en
`else
  assign int_test_en = 1'b0;
`endif

`ifdef PL230_INCLUDE_TEST
  // dma_done output status
  always @( negedge hresetn or posedge hclk )
  begin : p_dma_done_status
    if ( hresetn == 1'b0 )
      dma_done_status <= {`PL230_CHNLS{1'b0}};
    else
      if ( dma_done_status_wen )
        dma_done_status <= dma_done_status_nxt;
  end // p_dma_done_status
`else
  assign dma_done_status = {`PL230_CHNLS{1'b0}};
`endif

`ifdef PL230_INCLUDE_TEST
  // dma_active output status
  always @( negedge hresetn or posedge hclk )
  begin : p_dma_active_status
    if ( hresetn == 1'b0 )
      dma_active_status <= {`PL230_CHNLS{1'b0}};
    else
      if ( dma_active_status_wen )
        dma_active_status <= dma_active_status_nxt;
  end // p_dma_active_status
`else
  assign dma_active_status = {`PL230_CHNLS{1'b0}};
`endif

  //----------------------------------------------------------------------------
  // Register Read
  //----------------------------------------------------------------------------
  // Master enable
  assign master_enable = dma_cfg[0];
  // hprot value to be used when accessing channel control data
  assign chnl_ctrl_hprot3to1 = dma_cfg[3:1];

  //----------------------------------------------------------------------------
  // Register Read
  //----------------------------------------------------------------------------
  // DMA controller status
  always @( include_test or ctrl_state or master_enable )
  begin : p_dma_status
    numberofchannels = `PL230_CHNLS-1;
    dma_status = {{3{1'b0}},
                       include_test,
                       {7{1'b0}},
                       numberofchannels[4:0],
                       {(12 - `PL230_STATE_BITS){1'b0}},
                       ctrl_state,
                       {3{1'b0}},
                       master_enable
                      };
  end // p_dma_status

  // Define dma_err primary output status
  assign dma_err = err_status;

  // Mask dma_stall when integration test logic not included
  assign test_dma_stall = include_test & dma_stall;
  // Mask dma_req when integration test logic not included
  assign test_dma_req   = {`PL230_CHNLS{include_test}} & dma_req;
  // Mask dma_sreq when integration test logic not included
  assign test_dma_sreq  = {`PL230_CHNLS{include_test}} & dma_sreq;

  // APB read data multiplexor
  always @( paddr or
            addr_dma_status or addr_ctrl_base_ptr or addr_alt_ctrl_base_ptr or
            addr_dma_waitonreq_status or addr_chnl_useburst_set or
            addr_chnl_useburst_clr or addr_chnl_req_mask_set or
            addr_chnl_req_mask_clr or addr_chnl_enable_set or
            addr_chnl_enable_clr or addr_chnl_pri_alt_set or
            addr_chnl_pri_alt_clr or addr_chnl_priority_set or
            addr_chnl_priority_clr or addr_err_clr or
            addr_integration_cfg or addr_stall_status or
            addr_dma_req_status or addr_dma_sreq_status or
            addr_dma_done_set or addr_dma_done_clr or
            addr_dma_active_set or addr_dma_active_clr or
            addr_err_set or
            addr_periph_id_4 or addr_periph_id_0 or addr_periph_id_1 or
            addr_periph_id_2 or addr_periph_id_3 or addr_pcell_id_0 or
            addr_pcell_id_1 or addr_pcell_id_2 or addr_pcell_id_3 or
            dma_status or ctrl_base_ptr or dma_waitonreq or
            chnl_useburst_status or chnl_req_mask_status or
            chnl_enable_status or chnl_pri_alt_status or
            chnl_priority_status or err_status or
            int_test_en or test_dma_stall or test_dma_req or
            test_dma_sreq or dma_done_status or dma_active_status )
  begin : p_prdata
    prdata = {32{1'b0}};
    case (paddr[11:2])
      addr_dma_status[11:2]:
        prdata = dma_status;
      addr_ctrl_base_ptr[11:2]:
        prdata = {ctrl_base_ptr, {1+`PL230_CHNL_BITS+2+2{1'b0}}};
      addr_alt_ctrl_base_ptr[11:2]:
        prdata = {ctrl_base_ptr, 1'b1, {`PL230_CHNL_BITS+2+2{1'b0}}};
      addr_dma_waitonreq_status[11:2]:
        prdata[`PL230_CHNLS-1:0] = dma_waitonreq;
      addr_chnl_useburst_set[11:2],
      addr_chnl_useburst_clr[11:2]:
        prdata[`PL230_CHNLS-1:0] = chnl_useburst_status;
      addr_chnl_req_mask_set[11:2],
      addr_chnl_req_mask_clr[11:2]:
        prdata[`PL230_CHNLS-1:0] = chnl_req_mask_status;
      addr_chnl_enable_set[11:2],
      addr_chnl_enable_clr[11:2]:
        prdata[`PL230_CHNLS-1:0] = chnl_enable_status;
      addr_chnl_pri_alt_set[11:2],
      addr_chnl_pri_alt_clr[11:2]:
        prdata[`PL230_CHNLS-1:0] = chnl_pri_alt_status;
      addr_chnl_priority_set[11:2],
      addr_chnl_priority_clr[11:2]:
        prdata[`PL230_CHNLS-1:0] = chnl_priority_status;
      addr_err_clr[11:2]:
        prdata = {31'h0000_0000, err_status};
      addr_integration_cfg[11:2]:
        prdata = {31'h0000_0000, int_test_en};
      addr_stall_status[11:2]:
        prdata = {31'h0000_0000, test_dma_stall};
      addr_dma_req_status[11:2]:
        prdata[`PL230_CHNLS-1:0] = test_dma_req;
      addr_dma_sreq_status[11:2]:
        prdata[`PL230_CHNLS-1:0] = test_dma_sreq;
      addr_dma_done_set[11:2],
      addr_dma_done_clr[11:2]:
        prdata[`PL230_CHNLS-1:0] = dma_done_status;
      addr_dma_active_set[11:2],
      addr_dma_active_clr[11:2]:
        prdata[`PL230_CHNLS-1:0] = dma_active_status;
      addr_err_set[11:2]:
        prdata = {31'h0000_0000, err_status};
      addr_periph_id_4[11:2]:
        prdata = {24'h0000_00, `PL230_PERIPH_ID_4};
      addr_periph_id_0[11:2]:
        prdata = {24'h0000_00, `PL230_PERIPH_ID_0};
      addr_periph_id_1[11:2]:
        prdata = {24'h0000_00, `PL230_PERIPH_ID_1};
      addr_periph_id_2[11:2]:
        prdata = {24'h0000_00, `PL230_PERIPH_ID_2};
      addr_periph_id_3[11:2]:
        prdata = {24'h0000_00, `PL230_PERIPH_ID_3};
      addr_pcell_id_0[11:2]:
        prdata = {24'h0000_00, `PL230_PCELL_ID_0};
      addr_pcell_id_1[11:2]:
        prdata = {24'h0000_00, `PL230_PCELL_ID_1};
      addr_pcell_id_2[11:2]:
        prdata = {24'h0000_00, `PL230_PCELL_ID_2};
      addr_pcell_id_3[11:2]:
        prdata = {24'h0000_00, `PL230_PCELL_ID_3};
      default:
        prdata = 32'h0000_0000;
    endcase
  end // p_prdata


endmodule // pl230_apb_regs

`include "pl230_undefs.v"

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This page: Created:Wed Apr 6 17:30:52 2022
From: ../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel1/verilog/pl230_apb_regs.v

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