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//-----------------------------------------------------------------------------
// customised top-level example Cortex-M0 controller
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Flynn (d.w.flynn@soton.ac.uk)
//
// Copyright © 2021-2, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
//            (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
//                ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from Arm Limited or its affiliates.
//
//      SVN Information
//
//      Checked In          : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
//
//      Revision            : $Revision: 371321 $
//
//      Release Information : Cortex-M System Design Kit-r1p1-00rel0
//
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : Top level for example Cortex-M0/Cortex-M0+ microcontroller
//-----------------------------------------------------------------------------
//

`include "cmsdk_mcu_defs.v"

`define SYNTHBOOTROM 1

[Up: tb_cmsdk_mcu u_cmsdk_mcu]
module cmsdk_mcu_chipIndex #(
  //-----------------------------------------
  // CPU options

`ifdef ARM_CMSDK_INCLUDE_CLKGATE
  parameter CLKGATE_PRESENT = 1,
`else
  parameter CLKGATE_PRESENT = 0,
`endif
  parameter BE              = 0,   // Big or little endian
  parameter BKPT            = 4,   // Number of breakpoint comparators
  parameter DBG             = 1,   // Debug configuration
  parameter NUMIRQ          = 32,  // NUM of IRQ
  parameter SMUL            = 0,   // Multiplier configuration
  parameter SYST            = 1,   // SysTick
  parameter WIC             = 1,   // Wake-up interrupt controller support
  parameter WICLINES        = 34,  // Supported WIC lines
  parameter WPT             = 2,   // Number of DWT comparators
  parameter RESET_ALL_REGS  = 0,   // Do not reset all registers

  parameter BOOT_MEM_TYPE   = `ARM_CMSDK_BOOT_MEM_TYPE,   // Boot loader memory type

  parameter ROM_MEM_TYPE    = `ARM_CMSDK_ROM_MEM_TYPE,   // ROM memory type

  parameter RAM_MEM_TYPE    = `ARM_CMSDK_RAM_MEM_TYPE,   // RAM memory type

  //-----------------------------------------
  // System options

`ifdef ARM_CMSDK_INCLUDE_DMA
  parameter INCLUDE_DMA = 1, // Include instantiation of DMA-230
  // This option also add a number of bus components
  parameter DMA_CHANNEL_NUM = 1,
`else
  parameter INCLUDE_DMA = 0,
  parameter DMA_CHANNEL_NUM = 1,
`endif

`ifdef ARM_CMSDK_INCLUDE_BITBAND
  parameter INCLUDE_BITBAND = 1,
  // Include instantiation of Bit-band wrapper
  // This option add bit band wrapper to CPU interface
`else
  parameter INCLUDE_BITBAND = 0,
`endif

`ifdef ARM_CMSDK_INCLUDE_JTAG
  parameter INCLUDE_JTAG = 1  // Include JTAG feature
`else
  parameter INCLUDE_JTAG = 0  // Do not Include JTAG feature
`endif
 )
 (
`ifdef POWER_PINS
  inout  wire          VDDIO,
  inout  wire          VSSIO,
  inout  wire          VDD,
  inout  wire          VSS,
`endif
  input  wire          XTAL1, // input
  output wire          XTAL2, // output
  input  wire          NRST,  // active low reset
  inout  wire  [15:0]  P0,
  inout  wire  [15:0]  P1,

`ifdef ARM_CMSDK_INCLUDE_JTAG
  input  wire          nTRST,
  input  wire          TDI,
  output wire          TDO,
`endif
  inout  wire          SWDIOTMS,
  input  wire          SWCLKTCK);


//------------------------------------
// internal wires

  wire          xtal_clk_in;
  wire          xtal_clk_out;
  wire          nrst_in;
  wire  [15:0]  p0_in;      // level-shifted input from pad
  wire  [15:0]  p0_out;     // output port drive
  wire  [15:0]  p0_out_en;  // active high output drive enable (pad tech dependent)
  wire  [15:0]  p0_out_nen; // active low output drive enable (pad tech dependent)
  wire  [15:0]  p1_in;      // level-shifted input from pad
  wire  [15:0]  p1_out;     // output port drive
  wire  [15:0]  p1_out_en;  // active high output drive enable (pad tech dependent)
  wire  [15:0]  p1_out_nen; // active low output drive enable (pad tech dependent)
  wire  [15:0]  p1_out_mux;     // output port drive
  wire  [15:0]  p1_out_en_mux;  // active high output drive enable (pad tech dependent)
  wire  [15:0]  p1_out_nen_mux; // active low output drive enable (pad tech dependent)

`ifdef ARM_CMSDK_INCLUDE_JTAG
  wire          ntrst_in;
  wire          tdi_in;
  wire          tdo_out;
`endif
  wire          swdio_in;
  wire          swdio_out;
  wire          swdio_out_en;
  wire          swdio_out_nen;
  wire          swdclk_in;

  wire               ft_clk_o  ;
  wire               ft_ssn_o  ;
  wire               ft_miso_i;
  wire               ft_miosio_o;
  wire               ft_miosio_e;
  wire               ft_miosio_z;
  wire               ft_miosio_i;

  wire          ADPRESETREQ;
  
/*
  cmsdk_mcu_core
   #(.CLKGATE_PRESENT  (CLKGATE_PRESENT),
     .BE               (BE),
     .BKPT             (BKPT),          // Number of breakpoint comparators
     .DBG              (DBG),           // Debug configuration
     .NUMIRQ           (NUMIRQ),        // NUMIRQ
     .SMUL             (SMUL),          // Multiplier configuration
     .SYST             (SYST),          // SysTick
     .WIC              (WIC),           // Wake-up interrupt controller support
     .WICLINES         (WICLINES),      // Supported WIC lines
`ifdef CORTEX_M0PLUS
     .AWIDTH           (AWIDTH),        // Micro Trace Buffer SRAM address width
     .BASEADDR         (BASEADDR),      // ROM Table Base Address
     .HWF              (HWF),           // Half Word Fetching
     .IOP              (IOP),           // IO Port interface selected
     .IRQDIS           (IRQDIS),        // Interrupt Disable
     .MPU              (MPU),           // Memory Protection support
     .MTB              (MTB),           // MTB select
     .USER             (USER),          // User/Privilege
     .VTOR             (VTOR),          // Vector Table Offset support
`endif
     .WPT              (WPT),           // Number of DWT comparators
     .RESET_ALL_REGS   (RESET_ALL_REGS), // Do not reset all registers
     .BOOT_MEM_TYPE    (BOOT_MEM_TYPE), // Boot loader memory type
     .ROM_MEM_TYPE     (ROM_MEM_TYPE),  // ROM memory type
     .RAM_MEM_TYPE     (RAM_MEM_TYPE),  // RAM loader memory type
     .INCLUDE_BITBAND  (INCLUDE_BITBAND), // Include bit band wrapper
     .INCLUDE_DMA      (INCLUDE_DMA),   // Include DMA feature
     .INCLUDE_JTAG     (INCLUDE_JTAG)   // Include JTAG feature
   )
   u_cmsdk_mcu_core (
`ifdef POWER_PINS
  .VDDIO      (VDDIO),
  .VSSIO      (VSSIO),
  .VDD        (VDD),
  .VSS        (VSS),
`endif
  .clk        (xtal_clk_in), // primary clock
  .clk_out    (xtal_clk_out), // inverted clock out
  .nrst       (nrst_in)     // primary reset (active-low)

  .p0_in      (p0_in     ), // level-shifted input from pad
  .p0_out     (p0_out    ), // output port drive
  .p0_out_en  (p0_out_en ), // active high output drive enable (pad tech dependent)
  .p0_out_nen (p0_out_nen), // active low output drive enable (pad tech dependent)

  .p1_in          (p1_in     ), // level-shifted input from pad
  .p1_out_mux     (p1_out    ), // output port drive
  .p1_out_en_mux  (p1_out_en ), // active high output drive enable (pad tech dependent)
  .p1_out_nen_mux (p1_out_nen), // active low output drive enable (pad tech dependent)
  
`ifdef ARM_CMSDK_INCLUDE_JTAG
  .ntrst      (ntrst_in), // JTAG reset (active-low)
  .tdi        (tdi_in), // JTAG reset (active-low)
  .tdo        (tdo_out), // inverted clock out
`endif
  .swdio_in   (swdio_in), // Serial Wire Debug IO input
  .swdio_out  (swdio_out), // Serial Wire Debug IO output
  .swdio_out_en  (swdio_out_en), // Serial Wire Debug IO output drive enable (active high)
  .swdio_out_nen (swdio_out_nen), // Serial Wire Debug IO output drive enable (active low)
  .swdclk     (swdclk_in) // Serial Wire Debug clock input
  );
*/

//TIE_HI uTIEHI (.tiehi(tiehi));
 wire tiehi = 1'b1;
//TIE_LO uTIELO (.tielo(tielo));
 wire tielo = 1'b0;

 // --------------------------------------------------------------------------------
 // IO pad (GLIB Generic Library napping)
 // --------------------------------------------------------------------------------

`ifdef POWER_PINS
// Pad IO power supplies

PAD_VDDIO uPAD_VDDIO_1(
   .PAD(VDDIO)
   );

PAD_VDDIO uPAD_VSSIO_1(
   .PAD(VSSIO)
   );

// Core power supplies

PAD_VDDIO uPAD_VDD_1(
   .PAD(VDD)
   );

PAD_VDDIO uPAD_VSS_1(
   .PAD(VSS)
   );
`endif

// Clock, Reset and Serial Wire Debug ports

PAD_INOUT8MA_NOE uPAD_XTAL_I (
   .PAD (XTAL1), 
   .O   (tielo),
   .I   (xtal_clk_in), 
   .NOE (tiehi)
   );

PAD_INOUT8MA_NOE uPAD_XTAL_O (
   .PAD (XTAL2), 
   .O   (xtal_clk_out),
   .I   (tielo), 
   .NOE (tielo)
   );

PAD_INOUT8MA_NOE uPAD_NRST_I (
   .PAD (NRST), 
   .O   (tielo),
   .I   (nrst_in), 
   .NOE (tiehi)
   );

PAD_INOUT8MA_NOE uPAD_SWDIO_I (
   .PAD (SWDIOTMS), 
   .O   (swdio_out), 
   .I   (swdio_in),
   .NOE (swdio_out_nen)
   );

PAD_INOUT8MA_NOE uPAD_SWDCLK_I (
   .PAD (SWCLKTCK), 
   .O   (tielo), 
   .I   (swdclk_in),
   .NOE (tiehi)
   );

// GPI.I Port 0 x 16

PAD_INOUT8MA_NOE uPAD_P0_00 (
   .PAD (P0[00]), 
   .O   (p0_out[00]), 
   .I   (p0_in[00]),
   .NOE (p0_out_nen[00])
   );

PAD_INOUT8MA_NOE uPAD_P0_01 (
   .PAD (P0[01]), 
   .O   (p0_out[01]), 
   .I   (p0_in[01]),
   .NOE (p0_out_nen[01])
   );
  
PAD_INOUT8MA_NOE uPAD_P0_02 (
   .PAD (P0[02]), 
   .O   (p0_out[02]), 
   .I   (p0_in[02]),
   .NOE (p0_out_nen[02])
   );

PAD_INOUT8MA_NOE uPAD_P0_03 (
   .PAD (P0[03]), 
   .O   (p0_out[03]), 
   .I   (p0_in[03]),
   .NOE (p0_out_nen[03])
   );

PAD_INOUT8MA_NOE uPAD_P0_04 (
   .PAD (P0[04]), 
   .O   (p0_out[04]), 
   .I   (p0_in[04]),
   .NOE (p0_out_nen[04])
   );

PAD_INOUT8MA_NOE uPAD_P0_05 (
   .PAD (P0[05]), 
   .O   (p0_out[05]), 
   .I   (p0_in[05]),
   .NOE (p0_out_nen[05])
   );
  
PAD_INOUT8MA_NOE uPAD_P0_06 (
   .PAD (P0[06]), 
   .O   (p0_out[06]), 
   .I   (p0_in[06]),
   .NOE (p0_out_nen[06])
   );

PAD_INOUT8MA_NOE uPAD_P0_07 (
   .PAD (P0[07]), 
   .O   (p0_out[07]), 
   .I   (p0_in[07]),
   .NOE (p0_out_nen[07])
   );
  
PAD_INOUT8MA_NOE uPAD_P0_08 (
   .PAD (P0[08]), 
   .O   (p0_out[08]), 
   .I   (p0_in[08]),
   .NOE (p0_out_nen[08])
   );

PAD_INOUT8MA_NOE uPAD_P0_09 (
   .PAD (P0[09]), 
   .O   (p0_out[09]), 
   .I   (p0_in[09]),
   .NOE (p0_out_nen[09])
   );
  
PAD_INOUT8MA_NOE uPAD_P0_10 (
   .PAD (P0[10]), 
   .O   (p0_out[10]), 
   .I   (p0_in[10]),
   .NOE (p0_out_nen[10])
   );

PAD_INOUT8MA_NOE uPAD_P0_11 (
   .PAD (P0[11]), 
   .O   (p0_out[11]), 
   .I   (p0_in[11]),
   .NOE (p0_out_nen[11])
   );
  
PAD_INOUT8MA_NOE uPAD_P0_12 (
   .PAD (P0[12]), 
   .O   (p0_out[12]), 
   .I   (p0_in[12]),
   .NOE (p0_out_nen[12])
   );

PAD_INOUT8MA_NOE uPAD_P0_13 (
   .PAD (P0[13]), 
   .O   (p0_out[13]), 
   .I   (p0_in[13]),
   .NOE (p0_out_nen[13])
   );
  
PAD_INOUT8MA_NOE uPAD_P0_14 (
   .PAD (P0[14]), 
   .O   (p0_out[14]), 
   .I   (p0_in[14]),
   .NOE (p0_out_nen[14])
   );

PAD_INOUT8MA_NOE uPAD_P0_15 (
   .PAD (P0[15]), 
   .O   (p0_out[15]), 
   .I   (p0_in[15]),
   .NOE (p0_out_nen[15])
   );
  
// GPI.I Port 1 x 16
/*
PAD_INOUT8MA_NOE uPAD_P1_00 (
   .PAD (P1[00]), 
   .O   (p1_out_mux[00]), 
   .I   (p1_in[00]),
   .NOE (p1_out_nen_mux[00])
   );

PAD_INOUT8MA_NOE uPAD_P1_01 (
   .PAD (P1[01]), 
   .O   (p1_out_mux[01]), 
   .I   (p1_in[01]),
   .NOE (p1_out_nen_mux[01])
   );
  
PAD_INOUT8MA_NOE uPAD_P1_02 (
   .PAD (P1[02]), 
   .O   (p1_out_mux[02]), 
   .I   (p1_in[02]),
   .NOE (p1_out_nen_mux[02])
   );

PAD_INOUT8MA_NOE uPAD_P1_03 (
   .PAD (P1[03]), 
   .O   (p1_out_mux[03]), 
   .I   (p1_in[03]),
   .NOE (p1_out_nen_mux[03])
   );
*/

PAD_INOUT8MA_NOE uPAD_P1_00 (
   .PAD (P1[00]), 
   .O   (1'b0),       //p1_out[00]), 
   .I   (ft_miso_i), //p1_in[00]),
   .NOE (1'b1)        //p1_out_nen[00])
   );
assign p1_in[00] = ft_miso_i;

PAD_INOUT8MA_NOE uPAD_P1_01 (
   .PAD (P1[01]), 
   .O   (ft_clk_o  ), //p1_out[01]), 
   .I   (p1_in[01]),
   .NOE (1'b0)        //p1_out_nen[01])
   );
  
PAD_INOUT8MA_NOE uPAD_P1_02 (
   .PAD (P1[02]), 
   .O   (ft_miosio_o), //p1_out[02]), 
   .I   (ft_miosio_i),  //p1_in[02]),
   .NOE (ft_miosio_z)  //p1_out_nen[02])
   );
assign p1_in[02] = ft_miosio_i;

PAD_INOUT8MA_NOE uPAD_P1_03 (
   .PAD (P1[03]), 
   .O   (ft_ssn_o), 
   .I   (p1_in[03]),
   .NOE (1'b0)
   );

  
PAD_INOUT8MA_NOE uPAD_P1_04 (
   .PAD (P1[04]), 
   .O   (p1_out_mux[04]), 
   .I   (p1_in[04]),
   .NOE (p1_out_nen_mux[04])
   );

PAD_INOUT8MA_NOE uPAD_P1_05 (
   .PAD (P1[05]), 
   .O   (p1_out_mux[05]), 
   .I   (p1_in[05]),
   .NOE (p1_out_nen_mux[05])
   );
  
PAD_INOUT8MA_NOE uPAD_P1_06 (
   .PAD (P1[06]), 
   .O   (p1_out_mux[06]), 
   .I   (p1_in[06]),
   .NOE (p1_out_nen_mux[06])
   );

PAD_INOUT8MA_NOE uPAD_P1_07 (
   .PAD (P1[07]), 
   .O   (p1_out_mux[07]), 
   .I   (p1_in[07]),
   .NOE (p1_out_nen_mux[07])
   );
  
PAD_INOUT8MA_NOE uPAD_P1_08 (
   .PAD (P1[08]), 
   .O   (p1_out_mux[08]), 
   .I   (p1_in[08]),
   .NOE (p1_out_nen_mux[08])
   );

PAD_INOUT8MA_NOE uPAD_P1_09 (
   .PAD (P1[09]), 
   .O   (p1_out_mux[09]), 
   .I   (p1_in[09]),
   .NOE (p1_out_nen_mux[09])
   );
  
PAD_INOUT8MA_NOE uPAD_P1_10 (
   .PAD (P1[10]), 
   .O   (p1_out_mux[10]), 
   .I   (p1_in[10]),
   .NOE (p1_out_nen_mux[10])
   );

PAD_INOUT8MA_NOE uPAD_P1_11 (
   .PAD (P1[11]), 
   .O   (p1_out_mux[11]), 
   .I   (p1_in[11]),
   .NOE (p1_out_nen_mux[11])
   );
  
PAD_INOUT8MA_NOE uPAD_P1_12 (
   .PAD (P1[12]), 
   .O   (p1_out_mux[12]), 
   .I   (p1_in[12]),
   .NOE (p1_out_nen_mux[12])
   );

PAD_INOUT8MA_NOE uPAD_P1_13 (
   .PAD (P1[13]), 
   .O   (p1_out_mux[13]), 
   .I   (p1_in[13]),
   .NOE (p1_out_nen_mux[13])
   );
  
PAD_INOUT8MA_NOE uPAD_P1_14 (
   .PAD (P1[14]), 
   .O   (p1_out_mux[14]), 
   .I   (p1_in[14]),
   .NOE (p1_out_nen_mux[14])
   );

PAD_INOUT8MA_NOE uPAD_P1_15 (
   .PAD (P1[15]), 
   .O   (p1_out_mux[15]), 
   .I   (p1_in[15]),
   .NOE (p1_out_nen_mux[15])
   );
  
//------------------------------------
// internal wires

  assign p0_out_nen     = ~p0_out_en;     //active low pad drive option
  assign p1_out_nen_mux = ~p1_out_en_mux; //active low pad drive option
  
  wire               SLEEPING;
  wire               APBACTIVE;
  wire               SYSRESETREQ;    // processor system reset request
  wire               WDOGRESETREQ;   // watchdog system reset request
  wire               HRESETREQ;      // Combined system reset request
  wire               cmsdk_SYSRESETREQ; // Combined system reset request
  wire               clk_ctrl_sys_reset_req;
  wire               PMUHRESETREQ;
  wire               PMUDBGRESETREQ;
  wire               LOCKUP;
  wire               LOCKUPRESET;
  wire               PMUENABLE;
  wire               SLEEPDEEP;


`ifdef CORTEX_M0DESIGNSTART
  // if using DesignStart CortexM0, remove these signals
`else
  wire               WAKEUP;
  wire               GATEHCLK;
  wire               WICENREQ;
  wire               WICENACK;
  wire               CDBGPWRUPREQ;
  wire               CDBGPWRUPACK;
  wire               SLEEPHOLDREQn;
  wire               SLEEPHOLDACKn;

  wire               SYSPWRDOWNACK;
  wire               DBGPWRDOWNACK;
  wire               SYSPWRDOWN;
  wire               DBGPWRDOWN;
  wire               SYSISOLATEn;
  wire               SYSRETAINn;
  wire               DBGISOLATEn;
`endif

  wire               PORESETn;// Power on reset
  wire               HRESETn; // AHB reset
  wire               PRESETn; // APB and peripheral reset
`ifndef CORTEX_M0DESIGNSTART
  wire               DBGRESETn; // Debug system reset
`endif
  wire               FCLK;    // Free running system clock
  wire               HCLK;    // System clock from PMU
`ifndef CORTEX_M0DESIGNSTART
  wire               DCLK;
`endif
  wire               SCLK;
  wire               PCLK;    // Peripheral clock
  wire               PCLKG;   // Gated PCLK for APB
  wire               HCLKSYS; // System clock for memory
  wire               PCLKEN;  // Clock divider for AHB to APB bridge
  // Common AHB signals
  wire  [31:0]       HADDR;
  wire  [1:0]        HTRANS;
  wire  [2:0]        HSIZE;
  wire               HWRITE;
  wire  [31:0]       HWDATA;
  wire               HREADY;

// DMA controller master interface
  wire     [31:0]   dmac_haddr;
  wire     [1:0]    dmac_htrans;
  wire     [2:0]    dmac_hsize;
  wire     [2:0]    dmac_hburst;
  wire     [3:0]    dmac_hprot;
  wire              dmac_hmastlock;
  wire              dmac_hwrite;
  wire     [31:0]   dmac_hwdata;
  wire     [31:0]   dmac_hrdata;
  wire              dmac_hready;
  wire              dmac_hresp;

  wire              dmac_done;
  wire              dmac_err;
  wire              exp_penable;
  wire              exp_pwrite;
  wire  [11:0]      exp_paddr;
  wire  [31:0]      exp_pwdata;
  wire              exp15_psel;
  wire              exp15_pready;
  wire              exp15_pslverr;
  wire     [31:0]   exp15_prdata;
  wire              exp14_psel;
  wire              exp14_pready;
  wire              exp14_pslverr;
  wire     [31:0]   exp14_prdata;

  // Flash memory AHB signals
  wire               flash_hsel;
  wire               flash_hreadyout;
  wire  [31:0]       flash_hrdata;
  wire               flash_hresp;

  // SRAM AHB signals
  wire               sram_hsel;
  wire               sram_hreadyout;
  wire  [31:0]       sram_hrdata;
  wire               sram_hresp;

  // Boot loader/firmware AHB signals
  // Only use if BOOT_MEM_TYPE is not zero
  wire               boot_hsel;
  wire               boot_hreadyout;
  wire  [31:0]       boot_hrdata;
  wire               boot_hresp;

  // internal peripheral signals
  wire               uart0_rxd;
  wire               uart0_txd;
  wire               uart0_txen;
  wire               uart1_rxd;
  wire               uart1_txd;
  wire               uart1_txen;
  wire               uart2_rxd;
  wire               uart2_txd;
  wire               uart2_txen;

  wire               timer0_extin;
  wire               timer1_extin;

  wire  [15:0]       p0_altfunc;

  wire  [15:0]       p1_altfunc;

  localparam BASEADDR_GPIO0       = 32'h4001_0000;
  localparam BASEADDR_GPIO1       = 32'h4001_1000;
  localparam BASEADDR_SYSROMTABLE = 32'hF000_0000;

`ifdef CORTEX_M0PLUS
`ifdef ARM_CMSDK_INCLUDE_MTB
  // MTB Control
  wire               TSTART;
  wire               TSTOP;

  // EMBEDDED SRAM (MTB) INTERFACE
  wire               RAMHCLK;
  wire  [31:0]       RAMRD;
  wire  [AWIDTH-3:0] RAMAD;
  wire  [31:0]       RAMWD;
  wire               RAMCS;
  wire  [ 3:0]       RAMWE;

  localparam BASEADDR_MTBSRAM     = 32'hF021_0000;

  wire [31:0]        SRAMBASEADDR = BASEADDR_MTBSRAM;
`endif
`endif

  // Internal Debug signals
  wire               i_trst_n;
  wire               i_swditms;
  wire               i_swclktck;
  wire               i_tdi;
  wire               i_tdo;
  wire               i_tdoen_n;
  wire               i_swdo;
  wire               i_swdoen;

  wire               TESTMODE;

`ifdef ARM_CMSDK_INCLUDE_JTAG
`else
  // Serial wire debug is used.  nTRST, TDI and TDO are not needed
  wire               nTRST = 1'b0;
  wire               TDI   = 1'b1;
  wire               TDO;
`endif

  assign TESTMODE = 1'b0;

//----------------------------------------
// Clock and reset controller
//----------------------------------------
`ifdef CORTEX_M0DESIGNSTART
  // Clock controller generates reset if PMU request (PMUHRESETREQ),
  // CPU request or watchdog request (SYSRESETREQ)
  assign clk_ctrl_sys_reset_req = PMUHRESETREQ | cmsdk_SYSRESETREQ;
`else
  // Clock controller generates reset if PMU request (PMUHRESETREQ),
  // CPU request or watchdog request (HRESETREQ)
  assign clk_ctrl_sys_reset_req = PMUHRESETREQ | HRESETREQ;
`endif

  // Clock controller to generate reset and clock signals
  cmsdk_mcu_clkctrl
   #(.CLKGATE_PRESENT(CLKGATE_PRESENT))
   u_cmsdk_mcu_clkctrl(
     // inputs
    .XTAL1            (xtal_clk_in),
    .NRST             (nrst_in),

    .APBACTIVE        (APBACTIVE),
    .SLEEPING         (SLEEPING),
    .SLEEPDEEP        (SLEEPDEEP),
    .LOCKUP           (LOCKUP),
    .LOCKUPRESET      (LOCKUPRESET),
    .SYSRESETREQ      (clk_ctrl_sys_reset_req),
    .DBGRESETREQ      (PMUDBGRESETREQ),
    .CGBYPASS         (TESTMODE),
    .RSTBYPASS        (TESTMODE),

     // outputs
    .XTAL2            (xtal_clk_out),

    .FCLK             (FCLK),

    .PCLK             (PCLK),
    .PCLKG            (PCLKG),
    .PCLKEN           (PCLKEN),
`ifdef CORTEX_M0DESIGNSTART
    .PORESETn         (PORESETn),  // for cm0 designstart
    .HRESETn          (HRESETn),   // for cm0 designstart
`endif
    .PRESETn          (PRESETn)
    );

//----------------------------------------
//
   // System Reset request can be from processor or watchdog
   // or when lockup happens and the control flag is set.
   assign  cmsdk_SYSRESETREQ = SYSRESETREQ | WDOGRESETREQ |
                               ADPRESETREQ |
                               (LOCKUP & LOCKUPRESET);

`ifdef CORTEX_M0DESIGNSTART
   // Power Management Unit will not be available
   assign  HCLK = FCLK;        // connect HCLK to FCLK
   assign  SCLK = FCLK;        // connect SCLK to FCLK

   // Since there is no PMU, these signals are not used
   assign  PMUDBGRESETREQ = 1'b0;
   assign  PMUHRESETREQ   = 1'b0;

`else

  wire   gated_hclk;
  wire   gated_dclk;
  wire   gated_sclk;

`ifdef CORTEX_M0
  // Cortex-M0 Power management unit
  cortexm0_pmu u_cortexm0_pmu
  ( // Inputs
    .FCLK             (FCLK),
    .PORESETn         (PORESETn),
    .HRESETREQ        (cmsdk_SYSRESETREQ), // from processor / watchdog
    .PMUENABLE        (PMUENABLE),       // from System Controller
    .WICENACK         (WICENACK),        // from WIC in integration

    .WAKEUP           (WAKEUP),          // from WIC in integration
    .CDBGPWRUPREQ     (CDBGPWRUPREQ),

    .SLEEPDEEP        (SLEEPDEEP),
    .SLEEPHOLDACKn    (SLEEPHOLDACKn),
    .GATEHCLK         (GATEHCLK),
    .SYSPWRDOWNACK    (SYSPWRDOWNACK),
    .DBGPWRDOWNACK    (DBGPWRDOWNACK),
    .CGBYPASS         (TESTMODE),

   // Outputs
    .HCLK             (gated_hclk),
    .DCLK             (gated_dclk),
    .SCLK             (gated_sclk),
    .WICENREQ         (WICENREQ),
    .CDBGPWRUPACK     (CDBGPWRUPACK),
    .SYSISOLATEn      (SYSISOLATEn),
    .SYSRETAINn       (SYSRETAINn),
    .SYSPWRDOWN       (SYSPWRDOWN),
    .DBGISOLATEn      (DBGISOLATEn),
    .DBGPWRDOWN       (DBGPWRDOWN),
    .SLEEPHOLDREQn    (SLEEPHOLDREQn),
    .PMUDBGRESETREQ   (PMUDBGRESETREQ),
    .PMUHRESETREQ     (PMUHRESETREQ)
   );

  cortexm0_rst_ctl u_rst_ctl
  (// Inputs
   .GLOBALRESETn      (NRST),
   .FCLK              (FCLK),
   .HCLK              (gated_hclk),
   .DCLK              (gated_dclk),
   .SYSRESETREQ       (cmsdk_SYSRESETREQ),
   .PMUHRESETREQ      (PMUHRESETREQ),
   .PMUDBGRESETREQ    (PMUDBGRESETREQ),
   .RSTBYPASS         (1'b0),
   .SE                (1'b0),

   // Outputs
   .PORESETn          (PORESETn),
   .HRESETn           (HRESETn),
   .DBGRESETn         (DBGRESETn),
   .HRESETREQ         (HRESETREQ));

`else
  // Cortex-M0+ Power management unit
  cm0p_ik_pmu u_cortexm0plus_pmu
  ( // Inputs
    .FCLK             (FCLK),
    .PORESETn         (PORESETn),
    .HRESETREQ        (HRESETREQ),
    .PMUENABLE        (PMUENABLE),
    .WICENACK         (WICENACK),

    .WAKEUP           (WAKEUP),
    .CDBGPWRUPREQ     (CDBGPWRUPREQ),

    .SLEEPDEEP        (SLEEPDEEP),
    .SLEEPHOLDACKn    (SLEEPHOLDACKn),
    .GATEHCLK         (GATEHCLK),
    .SYSPWRDOWNACK    (SYSPWRDOWNACK),
    .DBGPWRDOWNACK    (DBGPWRDOWNACK),
    .DFTSE            (1'b0),

    // Outputs
    .HCLK             (gated_hclk),
    .DCLK             (gated_dclk),
    .SCLK             (gated_sclk),
    .WICENREQ         (WICENREQ),
    .CDBGPWRUPACK     (CDBGPWRUPACK),
    .SYSISOLATEn      (SYSISOLATEn),
    .SYSRETAINn       (SYSRETAINn),
    .SYSPWRDOWN       (SYSPWRDOWN),
    .DBGISOLATEn      (DBGISOLATEn),
    .DBGPWRDOWN       (DBGPWRDOWN),
    .SLEEPHOLDREQn    (SLEEPHOLDREQn),
    .PMUHRESETREQ     (PMUHRESETREQ),
    .PMUDBGRESETREQ   (PMUDBGRESETREQ)
   );

  cm0p_ik_rst_ctl u_rst_ctl
  (// Inputs
   .GLOBALRESETn      (NRST),
   .FCLK              (FCLK),
   .HCLK              (gated_hclk),
   .DCLK              (gated_dclk),
   .SYSRESETREQ       (cmsdk_SYSRESETREQ),
   .PMUHRESETREQ      (PMUHRESETREQ),
   .PMUDBGRESETREQ    (PMUDBGRESETREQ),
   .HREADY            (HREADY),
   .DFTRSTDISABLE     (1'b0),
   .DFTSE             (1'b0),

   // Outputs
   .PORESETn          (PORESETn),
   .HRESETn           (HRESETn),
   .DBGRESETn         (DBGRESETn),
   .HRESETREQ         (HRESETREQ));

`endif

  // Bypass clock gating cell in PMU if CLKGATE_PRESENT is 0
  assign  HCLK = (CLKGATE_PRESENT==0) ? FCLK : gated_hclk;
  assign  DCLK = (CLKGATE_PRESENT==0) ? FCLK : gated_dclk;
  assign  SCLK = (CLKGATE_PRESENT==0) ? FCLK : gated_sclk;

  // In this example system, power control takes place immediately.
  // In a real circuit you might need to add delays in the next two
  // signal assignments for correct operation.
  assign   SYSPWRDOWNACK = SYSPWRDOWN;
  assign   DBGPWRDOWNACK = DBGPWRDOWN;

`endif

  // -------------------------------
  // DMA Controller - ADP engine
  // -------------------------------

  wire        comio_tx_ready;
  wire [7:0]  comio_tx_data8;
  wire        comio_tx_valid;

  wire        comio_rx_ready;
  wire [7:0]  comio_rx_data8;
  wire        comio_rx_valid;
  
  wire        stdio_tx_ready;
  wire [7:0]  stdio_tx_data8;
  wire        stdio_tx_valid;

  wire        stdio_rx_ready;
  wire [7:0]  stdio_rx_data8;
  wire        stdio_rx_valid;

  wire [7:0]  adp_gpo8;
  wire [7:0]  adp_gpi8;

  assign adp_gpi8 = adp_gpo8;
assign ADPRESETREQ = adp_gpo8[0];

  // DMA controller present
  ADPcontrol_v1_0 u_ADP (
  // Clock and Reset
    .ahb_hclk          (HCLKSYS),
    .ahb_hresetn       (HRESETn),
  // DMA Control
    .com_rx_tready       (comio_rx_ready),
    .com_rx_tdata        (comio_rx_data8),
    .com_rx_tvalid       (comio_rx_valid),
    .com_tx_tready       (comio_tx_ready),
    .com_tx_tdata        (comio_tx_data8),
    .com_tx_tvalid       (comio_tx_valid),
    .stdio_rx_tready     (stdio_rx_ready),
    .stdio_rx_tdata      (stdio_rx_data8),
    .stdio_rx_tvalid     (stdio_rx_valid),
    .stdio_tx_tready     (stdio_tx_ready),
    .stdio_tx_tdata      (stdio_tx_data8),
    .stdio_tx_tvalid     (stdio_tx_valid),
    .gpo8                (adp_gpo8),
    .gpi8                (adp_gpi8),
  // AHB-Lite Master Interface
    .ahb_hready        (dmac_hready),
    .ahb_hresp         (dmac_hresp),
    .ahb_hrdata        (dmac_hrdata),
    .ahb_htrans        (dmac_htrans),
    .ahb_hwrite        (dmac_hwrite),
    .ahb_haddr         (dmac_haddr),
    .ahb_hsize         (dmac_hsize),
    .ahb_hburst        (dmac_hburst),
    .ahb_hmastlock     (dmac_hmastlock),
    .ahb_hprot         (dmac_hprot),
    .ahb_hwdata        (dmac_hwdata)
  );

   cmsdk_apb_uart_streamio u_apb_uart_com (
    .PCLK              (PCLK),     // Peripheral clock
    .PCLKG             (PCLKG),    // Gated PCLK for bus
    .PRESETn           (PRESETn),  // Reset

    .PSEL              (exp14_psel),     // APB interface inputs
    .PADDR             (exp_paddr[11:2]),
    .PENABLE           (exp_penable),
    .PWRITE            (exp_pwrite),
    .PWDATA            (exp_pwdata),

    .PRDATA            (exp14_prdata),   // APB interface outputs
    .PREADY            (exp14_pready),
    .PSLVERR           (exp14_pslverr),

    .ECOREVNUM         (4'h0),// Engineering-change-order revision bits

    .RXD               (1'b1),      // Receive data

    .TXD               ( ),      // Transmit data
    .TXEN              ( ),     // Transmit Enabled

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