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    .BAUDTICK          ( ),   // Baud rate x16 tick output (for testing)

    .TX_VALID_o        (stdio_rx_valid),
    .TX_DATA8_o        (stdio_rx_data8),
    .TX_READY_i        (stdio_rx_ready),

    .RX_VALID_i        (stdio_tx_valid),
    .RX_DATA8_i        (stdio_tx_data8),
    .RX_READY_o        (stdio_tx_ready),

    .TXINT             ( ),       // Transmit Interrupt
    .RXINT             ( ),       // Receive  Interrupt
    .TXOVRINT          ( ),    // Transmit Overrun Interrupt
    .RXOVRINT          ( ),    // Receive  Overrun Interrupt
    .UARTINT           ( ) // Combined Interrupt
  );

  wire        [7:0]  ft_clkdiv = 8'd03;

  ft1248_streamio_v1_0 #
   (.FT1248_WIDTH (1),
    .FT1248_CLKON(0) )
    u_ftdio_com    (
    .clk              (HCLKSYS),
    .resetn           (HRESETn),
    .ft_clkdiv        (ft_clkdiv    ),
    .ft_clk_o         (ft_clk_o     ),
    .ft_ssn_o         (ft_ssn_o     ),
    .ft_miso_i        (ft_miso_i    ),
    .ft_miosio_o      (ft_miosio_o  ),
    .ft_miosio_e      (ft_miosio_e  ),
    .ft_miosio_z      (ft_miosio_z  ),
    .ft_miosio_i      (ft_miosio_i  ),
    .rxd_tready       (comio_tx_ready),
    .rxd_tdata        (comio_tx_data8),
    .rxd_tvalid       (comio_tx_valid),
    .rxd_tlast        (1'b0),
    .txd_tready       (comio_rx_ready),
    .txd_tdata        (comio_rx_data8),
    .txd_tvalid       (comio_rx_valid),
    .txd_tlast        ( )
  );
 

//---------------------------------------------------
// System design for example Cortex-M0/Cortex-M0+ MCU
//---------------------------------------------------
  cmsdk_mcu_system
   #(.CLKGATE_PRESENT  (CLKGATE_PRESENT),
     .BE               (BE),
     .BASEADDR_GPIO0   (BASEADDR_GPIO0), // GPIO0 Base Address
     .BASEADDR_GPIO1   (BASEADDR_GPIO1), // GPIO1 Base Address
     .BKPT             (BKPT),       // Number of breakpoint comparators
     .DBG              (DBG),        // Debug configuration
     .NUMIRQ           (NUMIRQ),     // NUMIRQ
     .SMUL             (SMUL),       // Multiplier configuration
     .SYST             (SYST),       // SysTick
     .WIC              (WIC),        // Wake-up interrupt controller support
     .WICLINES         (WICLINES),   // Supported WIC lines
     .WPT              (WPT),        // Number of DWT comparators
     .RESET_ALL_REGS   (RESET_ALL_REGS), // Do not reset all registers
     .BOOT_MEM_TYPE    (BOOT_MEM_TYPE), // Boot loader memory type
     .INCLUDE_DMA      (INCLUDE_DMA), // Include DMA feature
     .INCLUDE_BITBAND  (INCLUDE_BITBAND), // Include bit band wrapper
     .INCLUDE_JTAG     (INCLUDE_JTAG), // Include JTAG feature
     .BASEADDR_SYSROMTABLE (BASEADDR_SYSROMTABLE) // System ROM Table base address
   )
    u_cmsdk_mcu_system (
    .FCLK             (FCLK),
    .HCLK             (HCLK),
`ifndef CORTEX_M0DESIGNSTART
    .DCLK             (DCLK),
`endif
    .SCLK             (SCLK),
    .HRESETn          (HRESETn),
    .PORESETn         (PORESETn),
`ifdef CORTEX_M0
    .DBGRESETn        (DBGRESETn),
    .RSTBYPASS        (TESTMODE),
`endif

    .PCLK             (PCLK),
    .PCLKG            (PCLKG),
    .PRESETn          (PRESETn),
    .PCLKEN           (PCLKEN),

    // Common AHB signals
    .HADDR            (HADDR),
    .HTRANS           (HTRANS),
    .HSIZE            (HSIZE),
    .HWRITE           (HWRITE),
    .HWDATA           (HWDATA),
    .HREADY           (HREADY),

    // Flash
    .flash_hsel       (flash_hsel),
    .flash_hreadyout  (flash_hreadyout),
    .flash_hrdata     (flash_hrdata),
    .flash_hresp      (flash_hresp),

    // SRAM
    .sram_hsel        (sram_hsel),
    .sram_hreadyout   (sram_hreadyout),
    .sram_hrdata      (sram_hrdata),
    .sram_hresp       (sram_hresp),

    // Optional boot loader
    // Only use if BOOT_MEM_TYPE is not zero
    .boot_hsel        (boot_hsel),
    .boot_hreadyout   (boot_hreadyout),
    .boot_hrdata      (boot_hrdata),
    .boot_hresp       (boot_hresp),

    // Status
    .APBACTIVE        (APBACTIVE),
    .SLEEPING         (SLEEPING),
    .SYSRESETREQ      (SYSRESETREQ),
    .WDOGRESETREQ     (WDOGRESETREQ),
    .LOCKUP           (LOCKUP),
    .LOCKUPRESET      (LOCKUPRESET),
    .PMUENABLE        (PMUENABLE),
    .SLEEPDEEP        (SLEEPDEEP),

`ifdef CORTEX_M0DESIGNSTART
`else  //if using DesignStart CortexM0, remove these signals

    .GATEHCLK         (GATEHCLK),
    .WAKEUP           (WAKEUP),
    .WICENREQ         (WICENREQ),
    .WICENACK         (WICENACK),
    .CDBGPWRUPREQ     (CDBGPWRUPREQ),
    .CDBGPWRUPACK     (CDBGPWRUPACK),
    .SLEEPHOLDREQn    (SLEEPHOLDREQn),
    .SLEEPHOLDACKn    (SLEEPHOLDACKn),

    // Debug
    .nTRST            (i_trst_n),
    .SWDITMS          (i_swditms),
    .SWCLKTCK         (i_swclktck),
    .TDI              (i_tdi),
    .TDO              (i_tdo),
    .nTDOEN           (i_tdoen_n),
    .SWDO             (i_swdo),
    .SWDOEN           (i_swdoen),
`endif

    // UART
    .uart0_rxd        (uart0_rxd),
    .uart0_txd        (uart0_txd),
    .uart0_txen       (uart0_txen),
    .uart1_rxd        (uart1_rxd),
    .uart1_txd        (uart1_txd),
    .uart1_txen       (uart1_txen),
    .uart2_rxd        (uart2_rxd),
    .uart2_txd        (uart2_txd),
    .uart2_txen       (uart2_txen),

    // Timer
    .timer0_extin     (timer0_extin),
    .timer1_extin     (timer1_extin),

    // IO Ports
    .p0_in            (p0_in),
    .p0_out           (p0_out),
    .p0_outen         (p0_out_en),
    .p0_altfunc       (p0_altfunc),

    .p1_in            (p1_in),
    .p1_out           (p1_out),
    .p1_outen         (p1_out_en),
    .p1_altfunc       (p1_altfunc),


  // DMA Control
 //   .dma_req       (dma230_tie0),
 //   .dma_sreq      (dma230_tie0),
 //   .dma_waitonreq (dma230_tie0),
 //   .dma_stall     (1'b0),
 //   .dma_active    (),
    .dma_done      (dmac_done),
    .dma_err       (dmac_err),
  // AHB-Lite Master Interface
    .dmac_hready        (dmac_hready),
    .dmac_hresp         (dmac_hresp),
    .dmac_hrdata        (dmac_hrdata),
    .dmac_htrans        (dmac_htrans),
    .dmac_hwrite        (dmac_hwrite),
    .dmac_haddr         (dmac_haddr),
    .dmac_hsize         (dmac_hsize),
    .dmac_hburst        (dmac_hburst),
    .dmac_hmastlock     (dmac_hmastlock),
    .dmac_hprot         (dmac_hprot),
    .dmac_hwdata        (dmac_hwdata),
  // APB Slave Interface
    .exp12_psel          ( ),
    .exp13_psel          ( ),
    .exp14_psel          (exp14_psel),
    .exp15_psel          ( ),
    .exp_penable         (exp_penable),
    .exp_pwrite          (exp_pwrite),
    .exp_paddr           (exp_paddr[11:0]),
    .exp_pwdata          (exp_pwdata[31:0]),
    .exp12_prdata        (32'h00000000),
    .exp12_pready        (1'b1),
    .exp12_pslverr       (1'b0),
    .exp13_prdata        (32'h00000000),
    .exp13_pready        (1'b1),
    .exp13_pslverr       (1'b0),
    .exp14_prdata        (exp14_prdata),
    .exp14_pready        (exp14_pready),
    .exp14_pslverr       (exp14_pslverr),
    .exp15_prdata        (32'h00000000),
    .exp15_pready        (1'b1),
    .exp15_pslverr       (1'b0),

    .DFTSE            (1'b0)
  );

//----------------------------------------
// If DMA is present, use SCLK for system HCLK so that
// DMA can run even if processor is in sleep mode.
// Otherwise there is only one master (cpu), so AHB system
// clock can be stopped when DMA take place.

//  assign   HCLKSYS  = (INCLUDE_DMA!=0) ? SCLK : HCLK;
  assign   HCLKSYS  = SCLK;

//----------------------------------------
// Flash memory
//----------------------------------------
cmsdk_ahb_rom
  #(.MEM_TYPE(ROM_MEM_TYPE),
//    .AW(16),  // 64K bytes flash ROM
    .AW(13),  // 8K bytes flash ROM -Dhry
//    .AW(10),  // 1K bytes flash ROM - Hello
    .filename("image.hex"),
    .WS_N(`ARM_CMSDK_ROM_MEM_WS_N),
    .WS_S(`ARM_CMSDK_ROM_MEM_WS_S),
    .BE  (BE))
   u_ahb_rom (
    .HCLK             (HCLKSYS),
    .HRESETn          (HRESETn),
    .HSEL             (flash_hsel),  // AHB inputs
//    .HADDR            (HADDR[15:0]),
    .HADDR            (HADDR[12:0]),
//    .HADDR            (HADDR[ 9:0]),
    .HTRANS           (HTRANS),
    .HSIZE            (HSIZE),
    .HWRITE           (HWRITE),
    .HWDATA           (HWDATA),
    .HREADY           (HREADY),

    .HREADYOUT        (flash_hreadyout), // Outputs
    .HRDATA           (flash_hrdata),
    .HRESP            (flash_hresp)
  );

//----------------------------------------
// Boot loader / Firmware
//----------------------------------------
// Only use if BOOT_MEM_TYPE is not zero
`ifdef SYNTHBOOTROM
ahb_bootrom
//ahb_bootrom__mangled
//  #(.AW(10)  ) // 1K bytes ROM
   u_ahb_bootloader (
    .HCLK             (HCLKSYS),
    .HRESETn          (HRESETn),
    .HSEL             (boot_hsel),  // AHB inputs
    .HADDR            (HADDR[ 9:0]),
    .HTRANS           (HTRANS),
    .HSIZE            (HSIZE),
    .HWRITE           (HWRITE),
    .HWDATA           (HWDATA),
    .HREADY           (HREADY),

    .HREADYOUT        (boot_hreadyout), // Outputs
    .HRDATA           (boot_hrdata),
    .HRESP            (boot_hresp)
  );
  
`else
// Only use if BOOT_MEM_TYPE is not zero
cmsdk_ahb_rom
  #(.MEM_TYPE(BOOT_MEM_TYPE),
//    .AW(12),  // 4K bytes ROM
    .AW(10),  // 1K bytes ROM
    .filename("bootloader.hex"),
    .WS_N(`ARM_CMSDK_BOOT_MEM_WS_N),
    .WS_S(`ARM_CMSDK_BOOT_MEM_WS_S),
    .BE  (BE))
   u_ahb_bootloader (
    .HCLK             (HCLKSYS),
    .HRESETn          (HRESETn),
    .HSEL             (boot_hsel),  // AHB inputs
//    .HADDR            (HADDR[11:0]),
    .HADDR            (HADDR[ 9:0]),
    .HTRANS           (HTRANS),
    .HSIZE            (HSIZE),
    .HWRITE           (HWRITE),
    .HWDATA           (HWDATA),
    .HREADY           (HREADY),

    .HREADYOUT        (boot_hreadyout), // Outputs
    .HRDATA           (boot_hrdata),
    .HRESP            (boot_hresp)
  );
`endif

//----------------------------------------
// SRAM
//----------------------------------------
cmsdk_ahb_ram
  #(.MEM_TYPE(RAM_MEM_TYPE),
///    .AW(16),  // 64K bytes SRAM
    .AW(10),  // 1K bytes SRAM
//    .AW( 9),  // 512 bytes SRAM
    .WS_N(`ARM_CMSDK_RAM_MEM_WS_N),
    .WS_S(`ARM_CMSDK_RAM_MEM_WS_S))
   u_ahb_ram (
    .HCLK             (HCLKSYS),
    .HRESETn          (HRESETn),
    .HSEL             (sram_hsel),  // AHB inputs
///    .HADDR            (HADDR[15:0]),
    .HADDR            (HADDR[ 9:0]),
//    .HADDR            (HADDR[ 8:0]),
    .HTRANS           (HTRANS),
    .HSIZE            (HSIZE),
    .HWRITE           (HWRITE),
    .HWDATA           (HWDATA),
    .HREADY           (HREADY),

    .HREADYOUT        (sram_hreadyout), // Outputs
    .HRDATA           (sram_hrdata),
    .HRESP            (sram_hresp)
  );

//----------------------------------------
// MTB SRAM Memory
//----------------------------------------
`ifdef CORTEX_M0PLUS
`ifdef ARM_CMSDK_INCLUDE_MTB

  cm0p_ik_sram
   #(.MEMNAME         ("MTB SRAM"),
     .DATAWIDTH       (32),
     .ADDRWIDTH       (AWIDTH-2),
     .MEMBASE         (BASEADDR_MTBSRAM))
    u_mtbram
    (//Output
     .RDATA           (RAMRD),
     //Inputs
     .CLK             (RAMHCLK),
     .ADDRESS         (RAMAD[AWIDTH-3:0]),
     .CS              (RAMCS),
     .WE              (RAMWE),
     .WDATA           (RAMWD));

`endif
`endif

//----------------------------------------
// I/O port pin muxing and tristate
//----------------------------------------

  assign        i_swclktck    =  swdclk_in;
  assign        i_swditms     =  swdio_in;
  assign        swdio_out     =  i_swdo;
  assign        swdio_out_en  =  i_swdoen;
  assign        swdio_out_nen = !i_swdoen;

  cmsdk_mcu_pin_mux
    u_pin_mux (
    // UART
    .uart0_rxd        (uart0_rxd),
    .uart0_txd        (uart0_txd),
    .uart0_txen       (uart0_txen),
    .uart1_rxd        (uart1_rxd),
    .uart1_txd        (uart1_txd),
    .uart1_txen       (uart1_txen),
    .uart2_rxd        (uart2_rxd),
    .uart2_txd        (uart2_txd),
    .uart2_txen       (uart2_txen),

    // Timer
    .timer0_extin     (timer0_extin),
    .timer1_extin     (timer1_extin),

`ifdef CORTEX_M0PLUS
`ifdef ARM_CMSDK_INCLUDE_MTB
    // MTB CONTROL
    .TSTART           (TSTART),
    .TSTOP            (TSTOP),
`endif
`endif

    // IO Ports
    .p0_in            ( ), // was (p0_in) now from pad inputs),
    .p0_out           (p0_out),
    .p0_outen         (p0_out_en),
    .p0_altfunc       (p0_altfunc),

    .p1_in            ( ), // was(p1_in) now from pad inputs),
    .p1_out           (p1_out),
    .p1_outen         (p1_out_en),
    .p1_altfunc       (p1_altfunc),

    // Debug
    .i_trst_n         (i_trst_n),
    .i_swditms        ( ), //i_swditms),
    .i_swclktck       ( ), //i_swclktck),
    .i_tdi            (i_tdi),
    .i_tdo            (i_tdo),
    .i_tdoen_n        (i_tdoen_n),
    .i_swdo           (i_swdo),
    .i_swdoen         (i_swdoen),

    // IO pads
    .p1_out_mux       (p1_out_mux),
    .p1_out_en_mux    (p1_out_en_mux),
    .P0               ( ), //P0),
    .P1               ( ), //P1),

    .nTRST            (nTRST),  // Not needed if serial-wire debug is used
    .TDI              (TDI),    // Not needed if serial-wire debug is used
    .SWDIOTMS         ( ), //SWDIOTMS),
    .SWCLKTCK         ( ), //SWCLKTCK),
    .TDO              (TDO)     // Not needed if serial-wire debug is used

  );

endmodule




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This page: Created:Wed Apr 6 17:30:52 2022
From: ../verilog/cmsdk_mcu_chip.v

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