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  // Check register clear command: ALTFUNCCLR register
  assert_next
  #(`OVL_ERROR, 1,1,0,
    `OVL_ASSERT,
    "write 1 to clear the register bit"
    )
  u_ovl_iop_gpio_clear_reg_altfunc
  (.clk         ( HCLK ),
   .reset_n     (HRESETn),
   .start_event ((ovl_gpio_wr) &
                 (IOADDR[11:0]==12'h01C)  // ALTFUNCCLR
                 ),
   .test_expr   (
                  reg_altfunc == (ovl_reg_altfunc_d &( ~(ovl_iowdata_d[15:0] & ovl_iop_byte_strobe_d_msk)) & ALTERNATE_FUNC_MASK)
                 )
   );

  // Check register clear command:  INTENCLR register
  assert_next
  #(`OVL_ERROR, 1,1,0,
    `OVL_ASSERT,
    "write 1 to clear the register bit"
    )
  u_ovl_iop_gpio_clear_reg_inten
  (.clk         ( HCLK ),
   .reset_n     (HRESETn),
   .start_event ((ovl_gpio_wr) &
                 (IOADDR[11:0]==12'h024)  // INTENCLR
                 ),
   .test_expr   (
                  reg_inten == (ovl_reg_inten_d & (~(ovl_iowdata_d[15:0]& ovl_iop_byte_strobe_d_msk)))
                 )
   );

  // Check register clear command:  INTTYPECLR register
  assert_next
  #(`OVL_ERROR, 1,1,0,
    `OVL_ASSERT,
    "write 1 to clear the register bit"
    )
  u_ovl_iop_gpio_clear_reg_inttype
  (.clk         ( HCLK ),
   .reset_n     (HRESETn),
   .start_event ((ovl_gpio_wr) &
                 (IOADDR[11:0]==12'h02C)  // INTTYPECLR
                 ),
   .test_expr   (
                  reg_inttype == (ovl_reg_inttype_d & (~(ovl_iowdata_d[15:0]& ovl_iop_byte_strobe_d_msk)))
                 )
   );

  // Check register clear command:  INTPOLCLR register
  assert_next
  #(`OVL_ERROR, 1,1,0,
    `OVL_ASSERT,
    "write 1 to clear the register bit"
    )
  u_ovl_iop_gpio_clear_reg_intpol
  (.clk         ( HCLK ),
   .reset_n     (HRESETn),
   .start_event ((ovl_gpio_wr) &
                 (IOADDR[11:0]==12'h034)  // INTPOLCLR
                 ),
   .test_expr   (
                  reg_intpol == (ovl_reg_intpol_d & (~(ovl_iowdata_d[15:0]& ovl_iop_byte_strobe_d_msk)))
                 )
   );

  // Check register clear command:  INTCLR register
  assert_next
  #(`OVL_ERROR, 1,1,0,
    `OVL_ASSERT,
    "write 1 to clear the register bit"
    )
  u_ovl_iop_gpio_clear_reg_intclr
  (.clk         ( FCLK ),
   .reset_n     (HRESETn),
   .start_event ((ovl_gpio_wr) &
                 (IOADDR[11:0]==12'h038)  // INTCLR
                 ),
   .test_expr   (
                  reg_intstat == ((ovl_reg_intstat_d & (~(ovl_iowdata_fclk_d[15:0]& ovl_reg_intclr_wr_d_msk))) |
                                  ( ovl_new_masked_int_d) )
                 )
   );


//****************************************
// X check
//****************************************

  // Port out should not go to X
  assert_never_unknown
  #(`OVL_ERROR, PortWidth, `OVL_ASSERT,
    "GPIO PORTOUT went X")
   u_ovl_iop_gpio_portout_x (
   .clk(HCLK),
   .reset_n(HRESETn),
   .qualifier(1'b1),
   .test_expr(PORTOUT)
   );

  // Port enable should not go to X
  assert_never_unknown
  #(`OVL_ERROR, PortWidth, `OVL_ASSERT,
    "GPIO port enable went X")
   u_ovl_iop_gpio_porten_x (
   .clk(HCLK),
   .reset_n(HRESETn),
   .qualifier(1'b1),
   .test_expr(PORTEN)
   );

  // Port alt function should not go to X
  assert_never_unknown
  #(`OVL_ERROR, PortWidth, `OVL_ASSERT,
    "GPIO alt function went X")
   u_ovl_iop_gpio_altfunc_x (
   .clk(HCLK),
   .reset_n(HRESETn),
   .qualifier(1'b1),
   .test_expr(PORTFUNC)
   );

  // Interrupt should not go to X
  assert_never_unknown
  #(`OVL_ERROR, PortWidth, `OVL_ASSERT,
    "GPIO INT went X")
   u_ovl_iop_gpio_gpioint_x (
   .clk(HCLK),
   .reset_n(HRESETn),
   .qualifier(1'b1),
   .test_expr(GPIOINT)
   );

  // Interrupt should not go to X
  assert_never_unknown
  #(`OVL_ERROR, 1, `OVL_ASSERT,
    "GPIO COMB INT went X")
   u_ovl_iop_gpio_combint_x (
   .clk(HCLK),
   .reset_n(HRESETn),
   .qualifier(1'b1),
   .test_expr(COMBINT)
   );


`endif

endmodule

12
HierarchyFilesModulesSignalsTasksFunctionsHelp

This page: Created:Mon Apr 25 12:30:36 2022
From: ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_iop_gpio/verilog/cmsdk_iop_gpio.v

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