// --------------------------------------------------------------------------------
// TARMAC for the Cortex-M0 or Cortex-M0+
// --------------------------------------------------------------------------------
`ifdef CORTEX_M0PLUS
`ifdef USE_TARMAC
`define ARM_CM0PIK_DBG_PATH u_cm0pmtb_int.u_cm0pintegration.u_imp.u_cortexm0plus
cm0p_tarmac
u_tarmac
(.en_i (1'b1),
.echo_i (1'b0),
.id_i (32'h1),
.use_time_i (1'b1),
.tube_i (32'h40400000),
.halted_i (`ARM_CM0PIK_DBG_PATH.HALTED),
.lockup_i (`ARM_CM0PIK_DBG_PATH.LOCKUP),
.hclk (`ARM_CM0PIK_DBG_PATH.HCLK),
.hready_i (`ARM_CM0PIK_DBG_PATH.HREADY),
.haddr_i (`ARM_CM0PIK_DBG_PATH.HADDR[31:0]),
.hprot_i (`ARM_CM0PIK_DBG_PATH.HPROT[3:0]),
.hsize_i (`ARM_CM0PIK_DBG_PATH.HSIZE[2:0]),
.hwrite_i (`ARM_CM0PIK_DBG_PATH.HWRITE),
.htrans_i (`ARM_CM0PIK_DBG_PATH.HTRANS[1:0]),
.hresetn_i (`ARM_CM0PIK_DBG_PATH.HRESETn),
.hresp_i (`ARM_CM0PIK_DBG_PATH.HRESP),
.hrdata_i (`ARM_CM0PIK_DBG_PATH.HRDATA[31:0]),
.hwdata_i (`ARM_CM0PIK_DBG_PATH.HWDATA[31:0]),
.ppb_trans_i (`ARM_CM0PIK_DBG_PATH.u_top.u_sys.u_matrix.ppb_trans),
.scs_rdata_i (`ARM_CM0PIK_DBG_PATH.u_top.u_sys.u_matrix.scs_rdata),
.ahb_trans_i (`ARM_CM0PIK_DBG_PATH.u_top.u_sys.u_core.ahb_trans),
.ipsr_i (`ARM_CM0PIK_DBG_PATH.u_top.u_sys.u_core.ipsr_q[5:0]),
.tbit_i (`ARM_CM0PIK_DBG_PATH.u_top.u_sys.u_core.tbit_q),
.fault_i (`ARM_CM0PIK_DBG_PATH.u_top.u_sys.u_core.fault_q),
.cc_pass_i (`ARM_CM0PIK_DBG_PATH.u_top.u_sys.u_core.cc_pass),
.spsel_i (`ARM_CM0PIK_DBG_PATH.u_top.u_sys.u_core.spsel_q),
.npriv_i (`ARM_CM0PIK_DBG_PATH.u_top.u_sys.u_core.npriv_q),
.primask_i (`ARM_CM0PIK_DBG_PATH.u_top.u_sys.u_core.primask_q),
.apsr_i (`ARM_CM0PIK_DBG_PATH.u_top.u_sys.u_core.apsr_q[3:0]),
.state_i (`ARM_CM0PIK_DBG_PATH.u_top.u_sys.u_core.state_q[3:0]),
.op_i (`ARM_CM0PIK_DBG_PATH.u_top.u_sys.u_core.op_q[15:0]),
.op_s_i (`ARM_CM0PIK_DBG_PATH.u_top.u_sys.u_core.op_s_q),
.iq_i (`ARM_CM0PIK_DBG_PATH.u_top.u_sys.u_core.iq_q[15:0]),
.iq_s_i (`ARM_CM0PIK_DBG_PATH.u_top.u_sys.u_core.iq_s_q),
.psp_en_i (`ARM_CM0PIK_DBG_PATH.u_top.u_sys.u_core.psp_en),
.msp_en_i (`ARM_CM0PIK_DBG_PATH.u_top.u_sys.u_core.msp_en),
.wr_data_i (`ARM_CM0PIK_DBG_PATH.u_top.u_sys.u_core.wr_data[31:0]),
.wr_data_sp_i (`ARM_CM0PIK_DBG_PATH.u_top.u_sys.u_core.wr_data_sp[29:0]),
.wr_addr_en_i (`ARM_CM0PIK_DBG_PATH.u_top.u_sys.u_core.wr_addr_en[3:0]),
.iaex_i (`ARM_CM0PIK_DBG_PATH.u_top.u_sys.u_core.iaex_q[30:0]),
.preempt_i (`ARM_CM0PIK_DBG_PATH.u_top.u_sys.u_core.preempt),
.int_ready_i (`ARM_CM0PIK_DBG_PATH.u_top.u_sys.u_core.int_ready_q),
.irq_ack_i (`ARM_CM0PIK_DBG_PATH.u_top.u_sys.u_core.irq_ack),
.rfe_ack_i (`ARM_CM0PIK_DBG_PATH.u_top.u_sys.u_core.rfe_ack),
.int_pend_num_i (`ARM_CM0PIK_DBG_PATH.u_top.u_sys.u_core.nvm_int_pend_num_i[5:0]),
.atomic_i (`ARM_CM0PIK_DBG_PATH.u_top.u_sys.u_core.atomic_q),
.hardfault_i (`ARM_CM0PIK_DBG_PATH.u_top.u_sys.u_core.hdf_req),
.iotrans_i (`ARM_CM0PIK_DBG_PATH.IOTRANS),
.iowrite_i (`ARM_CM0PIK_DBG_PATH.IOWRITE),
.iosize_i (`ARM_CM0PIK_DBG_PATH.IOSIZE[1:0]),
.ioaddr_i (`ARM_CM0PIK_DBG_PATH.IOADDR[31:0]),
.iordata_i (`ARM_CM0PIK_DBG_PATH.IORDATA[31:0]),
.iowdata_i (`ARM_CM0PIK_DBG_PATH.IOWDATA[31:0]),
.slvtrans_i (`ARM_CM0PIK_DBG_PATH.SLVTRANS[1:0]),
.slvwrite_i (`ARM_CM0PIK_DBG_PATH.SLVWRITE),
.slvsize_i (`ARM_CM0PIK_DBG_PATH.SLVSIZE[1:0]),
.slvaddr_i (`ARM_CM0PIK_DBG_PATH.SLVADDR[31:0]),
.slvrdata_i (`ARM_CM0PIK_DBG_PATH.SLVRDATA[31:0]),
.slvwdata_i (`ARM_CM0PIK_DBG_PATH.SLVWDATA[31:0]),
.slvready_i (`ARM_CM0PIK_DBG_PATH.SLVREADY),
.slvresp_i (`ARM_CM0PIK_DBG_PATH.SLVRESP)
);
`endif // USE_TARMAC
`else
`ifdef CORTEX_M0
`ifdef USE_TARMAC
`define ARM_CM0IK_DBG_PATH u_cortex_m0_int.u_cortexm0
cm0_tarmac #(.LOGFILENAME("tarmac1.log"))
u_tarmac
(.enable_i (1'b1),
.hclk_i (`ARM_CM0IK_DBG_PATH.HCLK),
.hready_i (`ARM_CM0IK_DBG_PATH.HREADY),
.haddr_i (`ARM_CM0IK_DBG_PATH.HADDR[31:0]),
.hprot_i (`ARM_CM0IK_DBG_PATH.HPROT[3:0]),
.hsize_i (`ARM_CM0IK_DBG_PATH.HSIZE[2:0]),
.hwrite_i (`ARM_CM0IK_DBG_PATH.HWRITE),
.htrans_i (`ARM_CM0IK_DBG_PATH.HTRANS[1:0]),
.hresetn_i (`ARM_CM0IK_DBG_PATH.HRESETn),
.hresp_i (`ARM_CM0IK_DBG_PATH.HRESP),
.hrdata_i (`ARM_CM0IK_DBG_PATH.HRDATA[31:0]),
.hwdata_i (`ARM_CM0IK_DBG_PATH.HWDATA[31:0]),
.lockup_i (`ARM_CM0IK_DBG_PATH.LOCKUP),
.halted_i (`ARM_CM0IK_DBG_PATH.HALTED),
.codehintde_i (`ARM_CM0IK_DBG_PATH.CODEHINTDE[2:0]),
.codenseq_i (`ARM_CM0IK_DBG_PATH.CODENSEQ),
.hdf_req_i (`ARM_CM0IK_DBG_PATH.u_top.u_sys.ctl_hdf_request),
.int_taken_i (`ARM_CM0IK_DBG_PATH.u_top.u_sys.dec_int_taken_o),
.int_return_i (`ARM_CM0IK_DBG_PATH.u_top.u_sys.dec_int_return_o),
.int_pend_i (`ARM_CM0IK_DBG_PATH.u_top.u_sys.nvm_int_pend),
.pend_num_i (`ARM_CM0IK_DBG_PATH.u_top.u_sys.nvm_int_pend_num[5:0]),
.ipsr_i (`ARM_CM0IK_DBG_PATH.u_top.u_sys.psr_ipsr[5:0]),
.ex_last_i (`ARM_CM0IK_DBG_PATH.u_top.u_sys.u_core.ctl_ex_last),
.iaex_en_i (`ARM_CM0IK_DBG_PATH.u_top.u_sys.u_core.ctl_iaex_en),
.reg_waddr_i (`ARM_CM0IK_DBG_PATH.u_top.u_sys.u_core.ctl_wr_addr[3:0]),
.reg_write_i (`ARM_CM0IK_DBG_PATH.u_top.u_sys.u_core.ctl_wr_en),
.xpsr_en_i (`ARM_CM0IK_DBG_PATH.u_top.u_sys.u_core.ctl_xpsr_en),
.fe_addr_i (`ARM_CM0IK_DBG_PATH.u_top.u_sys.u_core.pfu_fe_addr[30:0]),
.int_delay_i (`ARM_CM0IK_DBG_PATH.u_top.u_sys.u_core.pfu_int_delay),
.special_i (`ARM_CM0IK_DBG_PATH.u_top.u_sys.u_core.pfu_op_special),
.opcode_i (`ARM_CM0IK_DBG_PATH.u_top.u_sys.u_core.pfu_opcode[15:0]),
.reg_wdata_i (`ARM_CM0IK_DBG_PATH.u_top.u_sys.u_core.psr_gpr_wdata[31:0]),
.atomic_i (`ARM_CM0IK_DBG_PATH.u_top.u_sys.u_core.u_ctl.atomic),
.atomic_nxt_i (`ARM_CM0IK_DBG_PATH.u_top.u_sys.u_core.u_ctl.atomic_nxt),
.dabort_i (`ARM_CM0IK_DBG_PATH.u_top.u_sys.u_core.u_ctl.data_abort),
.ex_last_nxt_i (`ARM_CM0IK_DBG_PATH.u_top.u_sys.u_core.u_ctl.ex_last_nxt),
.int_preempt_i (`ARM_CM0IK_DBG_PATH.u_top.u_sys.u_core.u_ctl.int_preempt),
.psp_sel_i (`ARM_CM0IK_DBG_PATH.u_top.u_sys.u_core.u_gpr.psp_sel),
.xpsr_i (`ARM_CM0IK_DBG_PATH.u_top.u_sys.u_core.u_gpr.xpsr[31:0]),
.iaex_i (`ARM_CM0IK_DBG_PATH.u_top.u_sys.u_core.u_pfu.iaex[30:0]),
.iaex_nxt_i (`ARM_CM0IK_DBG_PATH.u_top.u_sys.u_core.u_pfu.iaex_nxt[30:0]),
.opcode_nxt_i (`ARM_CM0IK_DBG_PATH.u_top.u_sys.u_core.u_pfu.ibuf_de_nxt[15:0]),
.delay_count_i (`ARM_CM0IK_DBG_PATH.u_top.u_sys.u_core.u_pfu.ibuf_lo[13:6]),
.tbit_en_i (`ARM_CM0IK_DBG_PATH.u_top.u_sys.u_core.u_pfu.tbit_en),
.cflag_en_i (`ARM_CM0IK_DBG_PATH.u_top.u_sys.u_core.u_psr.cflag_ena),
.ipsr_en_i (`ARM_CM0IK_DBG_PATH.u_top.u_sys.u_core.u_psr.ipsr_ena),
.nzflag_en_i (`ARM_CM0IK_DBG_PATH.u_top.u_sys.u_core.u_psr.nzflag_ena),
.vflag_en_i (`ARM_CM0IK_DBG_PATH.u_top.u_sys.u_core.u_psr.vflag_ena)
);
`endif // USE_TARMAC
`endif // CORTEX_M0
`endif // CORTEX_M0PLUS
`ifdef USE_TARMAC
`ifdef CORTEX_M3
//synthesis translate_off
tarmac #("tarmac1.log")
utarmac ();
//synthesis translate_on
`endif
`endif
//---------------------------------------------------------------------------
// TracePort capturing buffer
//---------------------------------------------------------------------------
`ifdef ARM_CMSDK_DEBUG_TESTER_TRACE
cmsdk_debug_tester_trace_capture
u_trace_capture
(
// Outputs
.HREADYOUT (hready_out_tcb),
.HRESP (hresp_tcb),
.HRDATA (hrdata_tcb),
// Inputs
.HCLK (CLK),
.HRESETn (PORESETn),
.HSEL (hsel_tcb),
.HADDR (haddr[10:0]),
.HWRITE (hwrite),
.HTRANS (htrans[1:0]),
.HSIZE (hsize[2:0]),
.HWDATA (hwdata[31:0]),
.HREADY (hready_mux),
.TRACECLK (TRACECLK),
.TRACEDATA (TRACEDATA),
.SWV (SWV)
);
`else
assign hready_out_tcb = hready_out_def_slv;
assign hresp_tcb = hresp_def_slv;
assign hrdata_tcb = 32'h00000000;
`endif
//-----------------------------------------------------------------------------
// Character Output - debug_tester block, for debug purpose
//-----------------------------------------------------------------------------
reg [7:0] tube_string [127:0]; // buffer to hold printed message
reg [6:0] string_length; // Number of character in buffer
reg nxt_end_simulation; // end simulation signal (0x4 detected)
reg reg_end_simulation; // Delayed end simulation signal
integer i; // loop counter
reg [7:0] text_char; // temp variable for display
wire [7:0] d_chardata = {1'b0, (gpio_1_out[6:0] & gpio_1_en[6:0])}; // Data from GPIO
wire d_charstrobe = (gpio_1_out[7] & gpio_1_en[7]); // Strobe from GPIO
reg last_d_charstrobe; // last d_charstrobe for edge detection
// Registering d_charstrobe for edge detection
always @ (posedge CLK or negedge PORESETn)
begin
if (~PORESETn)
last_d_charstrobe <= 1'b0;
else
last_d_charstrobe <= d_charstrobe;
end
// Message display
always @ (posedge CLK or negedge PORESETn)
begin: p_tube
if (~PORESETn)
begin
string_length = {7{1'b0}};
nxt_end_simulation <= 1'b0;
for (i=0; i<= 127; i=i+1)
begin
tube_string[i] = 8'h00;
end
end
else
if (d_charstrobe & (~last_d_charstrobe))
begin
if (d_chardata==8'h04) // Stop simulation if 0x04 is received
nxt_end_simulation <= 1'b1;
else if ((d_chardata==13)|(d_chardata==10))
// New line
begin
tube_string[string_length] = 8'h00;
$write("%t DEBUG TESTER: ",$time);
for (i=0; i<= string_length; i=i+1)
begin
text_char = tube_string[i];
$write("%s",text_char);
end
$write("\n");
string_length <= {7{1'b0}};
end
else
begin
tube_string[string_length] = d_chardata;
string_length = string_length + 1;
if (string_length >79) // line too long, display and clear buffer
begin
tube_string[string_length] = 8'h00;
$write("%t DEBUG TESTER: ",$time);
for (i=0; i<= string_length; i=i+1)
begin
text_char = tube_string[i];
$write("%s",text_char);
end
$write("\n");
string_length <= {7{1'b0}};
end
end
end
end // p_TUBE
// Delay for simulation end
always @ (posedge CLK or negedge PORESETn)
begin: p_sim_end
if (~PORESETn)
begin
reg_end_simulation <= 1'b0;
end
else
begin
reg_end_simulation <= nxt_end_simulation;
if (reg_end_simulation==1'b1)
begin
$write("%t DEBUG TESTER: Test Ended\n",$time);
$stop;
end
end
end
endmodule
This page: |
Created: | Wed Nov 24 14:08:44 2021 |
|
From: |
../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_debug_tester/verilog/cmsdk_debug_tester.v |