//-----------------------------------------------------------------------------
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// only be used by a person authorised under and to the extent permitted
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//
// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
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// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from Arm Limited or its affiliates.
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// SVN Information
//
// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
//
// Revision : $Revision: 371321 $
//
// Release Information : Cortex-M System Design Kit-r1p1-00rel0
//
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : Simple clock and power on reset generator
//-----------------------------------------------------------------------------
`timescale 1ns/1ps
module cmsdk_clkreset
(
output wire CLK,
output wire NRST);
reg clock_q = 1'b0;
reg reset_n_q = 1'b0;
initial
begin
#10 clock_q <= 1'b1;
#100 reset_n_q <= 1'b1;
end
always @(clock_q)
#10 clock_q <= ~clock_q;
assign CLK = clock_q;
assign NRST = reset_n_q;
endmodule
This page: |
Created: | Wed Nov 24 14:08:44 2021 |
|
From: |
../verilog/cmsdk_clkreset.v |