//-----------------------------------------------------------------------------
// customised top-level example Cortex-M0 controller
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Flynn (d.w.flynn@soton.ac.uk)
//
// Copyright © 2021, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from Arm Limited or its affiliates.
//
// SVN Information
//
// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
//
// Revision : $Revision: 371321 $
//
// Release Information : Cortex-M System Design Kit-r1p1-00rel0
//
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : Top level for example Cortex-M0/Cortex-M0+ microcontroller
//-----------------------------------------------------------------------------
//
`include "cmsdk_mcu_defs.v"
module cmsdk_mcu
#(
//-----------------------------------------
// CPU options
`ifdef ARM_CMSDK_INCLUDE_CLKGATE
parameter CLKGATE_PRESENT = 1,
`else
parameter CLKGATE_PRESENT = 0,
`endif
parameter BE = 0, // Big or little endian
parameter BKPT = 4, // Number of breakpoint comparators
parameter DBG = 1, // Debug configuration
parameter NUMIRQ = 32, // NUM of IRQ
parameter SMUL = 0, // Multiplier configuration
parameter SYST = 1, // SysTick
parameter WIC = 1, // Wake-up interrupt controller support
parameter WICLINES = 34, // Supported WIC lines
parameter WPT = 2, // Number of DWT comparators
parameter RESET_ALL_REGS = 0, // Do not reset all registers
//-----------------------------------------
// Memory options - see cmsdk_mcu_defs.v
// This is defined in systems/cortex_m0_mcu/cmsdk_mcu_defs.v
// Based on the definition constants in logical/models/memories/cmsdk_ahb_memory_model_defs.v
// 0) AHB_ROM_NONE - memory not present
// 1) AHB_ROM_BEH_MODEL - behavioral ROM memory
// 2) AHB_ROM_FPGA_SRAM_MODEL - behavioral FPGA SRAM model with SRAM wrapper
// 3) AHB_ROM_FLASH32_MODEL - behavioral 32-bit flash memory
parameter BOOT_MEM_TYPE = `ARM_CMSDK_BOOT_MEM_TYPE, // Boot loader memory type
// This is defined in systems/cortex_m0_mcu/cmsdk_mcu_defs.v
// Based on the definition constants in logical/models/memories/cmsdk_ahb_memory_model_defs.v
// 0) AHB_ROM_NONE - memory not present (Not valid for a Cortex-M0 system)
// 1) AHB_ROM_BEH_MODEL - behavioral ROM memory
// 2) AHB_ROM_FPGA_SRAM_MODEL - behavioral FPGA SRAM model with SRAM wrapper
// 3) AHB_ROM_FLASH32_MODEL - behavioral 32-bit flash memory
parameter ROM_MEM_TYPE = `ARM_CMSDK_ROM_MEM_TYPE, // ROM memory type
// This is defined in systems/cortex_m0_mcu/cmsdk_mcu_defs.v
// Based on the definition constants in logical/models/memories/cmsdk_ahb_memory_model_defs.v
// 0) AHB_RAM_NONE - memory not present (Not valid for a Cortex-M0 system
// 1) AHB_RAM_BEH_MODEL - behavioral RAM memory
// 2) AHB_RAM_FPGA_SRAM_MODEL - behavioral SRAM model with SRAM wrapper
// 3) AHB_RAM_EXT_SRAM16_MODEL - for benchmarking using 16-bit external asynchronous SRAM
// 4) AHB_RAM_EXT_SRAM8_MODEL - for benchmarking using 8-bit external asynchronous SRAM
parameter RAM_MEM_TYPE = `ARM_CMSDK_RAM_MEM_TYPE, // RAM memory type
//-----------------------------------------
// System options
`ifdef ARM_CMSDK_INCLUDE_DMA
parameter INCLUDE_DMA = 1, // Include instantiation of DMA-230
// This option also add a number of bus components
parameter DMA_CHANNEL_NUM = 4,
`else
parameter INCLUDE_DMA = 0,
parameter DMA_CHANNEL_NUM = 4,
`endif
`ifdef ARM_CMSDK_INCLUDE_BITBAND
parameter INCLUDE_BITBAND = 1,
// Include instantiation of Bit-band wrapper
// This option add bit band wrapper to CPU interface
`else
parameter INCLUDE_BITBAND = 0,
`endif
`ifdef ARM_CMSDK_INCLUDE_JTAG
parameter INCLUDE_JTAG = 1 // Include JTAG feature
`else
parameter INCLUDE_JTAG = 0 // Do not Include JTAG feature
`endif
)
(
input wire XTAL1, // input
output wire XTAL2, // output
input wire NRST, // active low reset
inout wire [15:0] P0,
inout wire [15:0] P1,
`ifdef ARM_CMSDK_INCLUDE_JTAG
input wire nTRST,
input wire TDI,
output wire TDO,
`endif
inout wire SWDIOTMS,
input wire SWCLKTCK);
//------------------------------------
// internal wires
wire SLEEPING;
wire APBACTIVE;
wire SYSRESETREQ; // processor system reset request
wire WDOGRESETREQ; // watchdog system reset request
wire HRESETREQ; // Combined system reset request
wire cmsdk_SYSRESETREQ; // Combined system reset request
wire clk_ctrl_sys_reset_req;
wire PMUHRESETREQ;
wire PMUDBGRESETREQ;
wire LOCKUP;
wire LOCKUPRESET;
wire PMUENABLE;
wire SLEEPDEEP;
`ifdef CORTEX_M0DESIGNSTART
// if using DesignStart CortexM0, remove these signals
`else
wire WAKEUP;
wire GATEHCLK;
wire WICENREQ;
wire WICENACK;
wire CDBGPWRUPREQ;
wire CDBGPWRUPACK;
wire SLEEPHOLDREQn;
wire SLEEPHOLDACKn;
wire SYSPWRDOWNACK;
wire DBGPWRDOWNACK;
wire SYSPWRDOWN;
wire DBGPWRDOWN;
wire SYSISOLATEn;
wire SYSRETAINn;
wire DBGISOLATEn;
`endif
wire PORESETn;// Power on reset
wire HRESETn; // AHB reset
wire PRESETn; // APB and peripheral reset
`ifndef CORTEX_M0DESIGNSTART
wire DBGRESETn; // Debug system reset
`endif
wire FCLK; // Free running system clock
wire HCLK; // System clock from PMU
`ifndef CORTEX_M0DESIGNSTART
wire DCLK;
`endif
wire SCLK;
wire PCLK; // Peripheral clock
wire PCLKG; // Gated PCLK for APB
wire HCLKSYS; // System clock for memory
wire PCLKEN; // Clock divider for AHB to APB bridge
// Common AHB signals
wire [31:0] HADDR;
wire [1:0] HTRANS;
wire [2:0] HSIZE;
wire HWRITE;
wire [31:0] HWDATA;
wire HREADY;
// DMA controller master interface
wire [31:0] dmac_haddr;
wire [1:0] dmac_htrans;
wire [2:0] dmac_hsize;
wire [2:0] dmac_hburst;
wire [3:0] dmac_hprot;
wire dmac_hmastlock;
wire dmac_hwrite;
wire [31:0] dmac_hwdata;
wire [31:0] dmac_hrdata;
wire dmac_hready;
wire dmac_hresp;
wire dmac_done;
wire dmac_err;
wire dmac_psel;
wire dmac_pready;
wire exp_penable;
wire exp_pwrite;
wire [11:0] exp_paddr;
wire [31:0] exp_pwdata;
wire dmac_pslverr;
wire [31:0] dmac_prdata;
// Flash memory AHB signals
wire flash_hsel;
wire flash_hreadyout;
wire [31:0] flash_hrdata;
wire flash_hresp;
// SRAM AHB signals
wire sram_hsel;
wire sram_hreadyout;
wire [31:0] sram_hrdata;
wire sram_hresp;
// Boot loader/firmware AHB signals
// Only use if BOOT_MEM_TYPE is not zero
wire boot_hsel;
wire boot_hreadyout;
wire [31:0] boot_hrdata;
wire boot_hresp;
// internal peripheral signals
wire uart0_rxd;
wire uart0_txd;
wire uart0_txen;
wire uart1_rxd;
wire uart1_txd;
wire uart1_txen;
wire uart2_rxd;
wire uart2_txd;
wire uart2_txen;
wire timer0_extin;
wire timer1_extin;
wire [15:0] p0_in;
wire [15:0] p0_out;
wire [15:0] p0_outen;
wire [15:0] p0_altfunc;
wire [15:0] p1_in;
wire [15:0] p1_out;
wire [15:0] p1_outen;
wire [15:0] p1_altfunc;
localparam BASEADDR_GPIO0 = 32'h4001_0000;
localparam BASEADDR_GPIO1 = 32'h4001_1000;
localparam BASEADDR_SYSROMTABLE = 32'hF000_0000;
`ifdef CORTEX_M0PLUS
`ifdef ARM_CMSDK_INCLUDE_MTB
// MTB Control
wire TSTART;
wire TSTOP;
// EMBEDDED SRAM (MTB) INTERFACE
wire RAMHCLK;
wire [31:0] RAMRD;
wire [AWIDTH-3:0] RAMAD;
wire [31:0] RAMWD;
wire RAMCS;
wire [ 3:0] RAMWE;
localparam BASEADDR_MTBSRAM = 32'hF021_0000;
wire [31:0] SRAMBASEADDR = BASEADDR_MTBSRAM;
`endif
`endif
// Internal Debug signals
wire i_trst_n;
wire i_swditms;
wire i_swclktck;
wire i_tdi;
wire i_tdo;
wire i_tdoen_n;
wire i_swdo;
wire i_swdoen;
wire TESTMODE;
`ifdef ARM_CMSDK_INCLUDE_JTAG
`else
// Serial wire debug is used. nTRST, TDI and TDO are not needed
wire nTRST = 1'b0;
wire TDI = 1'b1;
wire TDO;
`endif
assign TESTMODE = 1'b0;
//----------------------------------------
// Clock and reset controller
//----------------------------------------
`ifdef CORTEX_M0DESIGNSTART
// Clock controller generates reset if PMU request (PMUHRESETREQ),
// CPU request or watchdog request (SYSRESETREQ)
assign clk_ctrl_sys_reset_req = PMUHRESETREQ | cmsdk_SYSRESETREQ;
`else
// Clock controller generates reset if PMU request (PMUHRESETREQ),
// CPU request or watchdog request (HRESETREQ)
assign clk_ctrl_sys_reset_req = PMUHRESETREQ | HRESETREQ;
`endif
// Clock controller to generate reset and clock signals
cmsdk_mcu_clkctrl
#(.CLKGATE_PRESENT(CLKGATE_PRESENT))
u_cmsdk_mcu_clkctrl(
// inputs
.XTAL1 (XTAL1),
.NRST (NRST),
.APBACTIVE (APBACTIVE),
.SLEEPING (SLEEPING),
.SLEEPDEEP (SLEEPDEEP),
.LOCKUP (LOCKUP),
.LOCKUPRESET (LOCKUPRESET),
.SYSRESETREQ (clk_ctrl_sys_reset_req),
.DBGRESETREQ (PMUDBGRESETREQ),
.CGBYPASS (TESTMODE),
.RSTBYPASS (TESTMODE),
// outputs
.XTAL2 (XTAL2),
.FCLK (FCLK),
.PCLK (PCLK),
.PCLKG (PCLKG),
.PCLKEN (PCLKEN),
`ifdef CORTEX_M0DESIGNSTART
.PORESETn (PORESETn), // for cm0 designstart
.HRESETn (HRESETn), // for cm0 designstart
`endif
.PRESETn (PRESETn)
);
//----------------------------------------
//
// System Reset request can be from processor or watchdog
// or when lockup happens and the control flag is set.
assign cmsdk_SYSRESETREQ = SYSRESETREQ | WDOGRESETREQ |
(LOCKUP & LOCKUPRESET);
`ifdef CORTEX_M0DESIGNSTART
// Power Management Unit will not be available
assign HCLK = FCLK; // connect HCLK to FCLK
assign SCLK = FCLK; // connect SCLK to FCLK
// Since there is no PMU, these signals are not used
assign PMUDBGRESETREQ = 1'b0;
assign PMUHRESETREQ = 1'b0;
`else
wire gated_hclk;
wire gated_dclk;
wire gated_sclk;
`ifdef CORTEX_M0
// Cortex-M0 Power management unit
cortexm0_pmu u_cortexm0_pmu
( // Inputs
.FCLK (FCLK),
.PORESETn (PORESETn),
.HRESETREQ (cmsdk_SYSRESETREQ), // from processor / watchdog
.PMUENABLE (PMUENABLE), // from System Controller
.WICENACK (WICENACK), // from WIC in integration
.WAKEUP (WAKEUP), // from WIC in integration
.CDBGPWRUPREQ (CDBGPWRUPREQ),
.SLEEPDEEP (SLEEPDEEP),
.SLEEPHOLDACKn (SLEEPHOLDACKn),
.GATEHCLK (GATEHCLK),
.SYSPWRDOWNACK (SYSPWRDOWNACK),
.DBGPWRDOWNACK (DBGPWRDOWNACK),
.CGBYPASS (TESTMODE),
// Outputs
.HCLK (gated_hclk),
.DCLK (gated_dclk),
.SCLK (gated_sclk),
.WICENREQ (WICENREQ),
.CDBGPWRUPACK (CDBGPWRUPACK),
.SYSISOLATEn (SYSISOLATEn),
.SYSRETAINn (SYSRETAINn),
.SYSPWRDOWN (SYSPWRDOWN),
.DBGISOLATEn (DBGISOLATEn),
.DBGPWRDOWN (DBGPWRDOWN),
.SLEEPHOLDREQn (SLEEPHOLDREQn),
.PMUDBGRESETREQ (PMUDBGRESETREQ),
.PMUHRESETREQ (PMUHRESETREQ)
);
cortexm0_rst_ctl u_rst_ctl
(// Inputs
.GLOBALRESETn (NRST),
.FCLK (FCLK),
.HCLK (gated_hclk),
.DCLK (gated_dclk),
.SYSRESETREQ (cmsdk_SYSRESETREQ),
.PMUHRESETREQ (PMUHRESETREQ),
.PMUDBGRESETREQ (PMUDBGRESETREQ),
.RSTBYPASS (1'b0),
.SE (1'b0),
// Outputs
.PORESETn (PORESETn),
.HRESETn (HRESETn),
.DBGRESETn (DBGRESETn),
.HRESETREQ (HRESETREQ));
`else
// Cortex-M0+ Power management unit
cm0p_ik_pmu u_cortexm0plus_pmu
( // Inputs
.FCLK (FCLK),
.PORESETn (PORESETn),
.HRESETREQ (HRESETREQ),
.PMUENABLE (PMUENABLE),
.WICENACK (WICENACK),
.WAKEUP (WAKEUP),
.CDBGPWRUPREQ (CDBGPWRUPREQ),
.SLEEPDEEP (SLEEPDEEP),
.SLEEPHOLDACKn (SLEEPHOLDACKn),
.GATEHCLK (GATEHCLK),
.SYSPWRDOWNACK (SYSPWRDOWNACK),
.DBGPWRDOWNACK (DBGPWRDOWNACK),
.DFTSE (1'b0),
// Outputs
.HCLK (gated_hclk),
.DCLK (gated_dclk),
.SCLK (gated_sclk),
.WICENREQ (WICENREQ),
.CDBGPWRUPACK (CDBGPWRUPACK),
.SYSISOLATEn (SYSISOLATEn),
.SYSRETAINn (SYSRETAINn),
.SYSPWRDOWN (SYSPWRDOWN),
.DBGISOLATEn (DBGISOLATEn),
.DBGPWRDOWN (DBGPWRDOWN),
.SLEEPHOLDREQn (SLEEPHOLDREQn),
.PMUHRESETREQ (PMUHRESETREQ),
.PMUDBGRESETREQ (PMUDBGRESETREQ)
);
cm0p_ik_rst_ctl u_rst_ctl
(// Inputs
.GLOBALRESETn (NRST),
.FCLK (FCLK),
.HCLK (gated_hclk),
.DCLK (gated_dclk),
.SYSRESETREQ (cmsdk_SYSRESETREQ),
.PMUHRESETREQ (PMUHRESETREQ),
.PMUDBGRESETREQ (PMUDBGRESETREQ),
.HREADY (HREADY),
.DFTRSTDISABLE (1'b0),
.DFTSE (1'b0),
// Outputs
.PORESETn (PORESETn),
.HRESETn (HRESETn),
.DBGRESETn (DBGRESETn),
.HRESETREQ (HRESETREQ));
`endif
// Bypass clock gating cell in PMU if CLKGATE_PRESENT is 0
assign HCLK = (CLKGATE_PRESENT==0) ? FCLK : gated_hclk;
assign DCLK = (CLKGATE_PRESENT==0) ? FCLK : gated_dclk;
assign SCLK = (CLKGATE_PRESENT==0) ? FCLK : gated_sclk;
// In this example system, power control takes place immediately.
// In a real circuit you might need to add delays in the next two
// signal assignments for correct operation.
assign SYSPWRDOWNACK = SYSPWRDOWN;
assign DBGPWRDOWNACK = DBGPWRDOWN;
`endif
// -------------------------------
// DMA Controller
// -------------------------------
// DMA interface not used in this example system
wire [DMA_CHANNEL_NUM-1:0] dma230_tie0; // tie off signal.
assign dma230_tie0 = {DMA_CHANNEL_NUM{1'b0}};
// DMA done per channel
wire [DMA_CHANNEL_NUM-1:0] dma230_done_ch;
generate if (INCLUDE_DMA != 0) begin : gen_pl230_udma
// DMA controller present
pl230_udma u_pl230_udma (
// Clock and Reset
.hclk (HCLKSYS),
.hresetn (HRESETn),
// DMA Control
.dma_req (dma230_tie0),
.dma_sreq (dma230_tie0),
.dma_waitonreq (dma230_tie0),
.dma_stall (1'b0),
.dma_active (),
.dma_done (dma230_done_ch),
.dma_err (dmac_err),
// AHB-Lite Master Interface
.hready (dmac_hready),
.hresp (dmac_hresp),
.hrdata (dmac_hrdata),
.htrans (dmac_htrans),
.hwrite (dmac_hwrite),
.haddr (dmac_haddr),
.hsize (dmac_hsize),
.hburst (dmac_hburst),
.hmastlock (dmac_hmastlock),
.hprot (dmac_hprot),
.hwdata (dmac_hwdata),
// APB Slave Interface
.pclken (PCLKEN),
.psel (dmac_psel),
.pen (exp_penable),
.pwrite (exp_pwrite),
.paddr (exp_paddr[11:0]),
.pwdata (exp_pwdata[31:0]),
.prdata (dmac_prdata)
);
assign dmac_pready = 1'b1;
assign dmac_pslverr = 1'b0;
assign dmac_done = |dma230_done_ch; // OR all the DMA done together
end else begin : gen_no_pl230_udma
// DMA controller not present
assign dmac_htrans = 2'b00;
assign dmac_hwrite = 1'b0;
assign dmac_haddr = 32'h00000000;
assign dmac_hsize = 3'b000;
assign dmac_hburst = 3'b000;
assign dmac_hmastlock = 1'b0;
assign dmac_hprot = 4'b0000;
assign dmac_hwdata = 32'h00000000;
assign dmac_done = 1'b0;
assign dmac_err = 1'b0;
assign dmac_pready = 1'b1;
assign dmac_pslverr = 1'b0;
assign dmac_prdata = 32'h00000000;
assign dma230_done_ch = {DMA_CHANNEL_NUM{1'b0}};
end endgenerate
//---------------------------------------------------
// System design for example Cortex-M0/Cortex-M0+ MCU
//---------------------------------------------------
cmsdk_mcu_system
#(.CLKGATE_PRESENT (CLKGATE_PRESENT),
.BE (BE),
.BASEADDR_GPIO0 (BASEADDR_GPIO0), // GPIO0 Base Address
.BASEADDR_GPIO1 (BASEADDR_GPIO1), // GPIO1 Base Address
.BKPT (BKPT), // Number of breakpoint comparators
.DBG (DBG), // Debug configuration
.NUMIRQ (NUMIRQ), // NUMIRQ
.SMUL (SMUL), // Multiplier configuration
.SYST (SYST), // SysTick
.WIC (WIC), // Wake-up interrupt controller support
.WICLINES (WICLINES), // Supported WIC lines
.WPT (WPT), // Number of DWT comparators
.RESET_ALL_REGS (RESET_ALL_REGS), // Do not reset all registers
.BOOT_MEM_TYPE (BOOT_MEM_TYPE), // Boot loader memory type
.INCLUDE_DMA (INCLUDE_DMA), // Include DMA feature
.INCLUDE_BITBAND (INCLUDE_BITBAND), // Include bit band wrapper
.INCLUDE_JTAG (INCLUDE_JTAG), // Include JTAG feature
.BASEADDR_SYSROMTABLE (BASEADDR_SYSROMTABLE) // System ROM Table base address
)
u_cmsdk_mcu_system (
.FCLK (FCLK),
.HCLK (HCLK),
`ifndef CORTEX_M0DESIGNSTART
.DCLK (DCLK),
`endif
.SCLK (SCLK),
.HRESETn (HRESETn),
.PORESETn (PORESETn),
`ifdef CORTEX_M0
.DBGRESETn (DBGRESETn),
.RSTBYPASS (TESTMODE),
`endif
.PCLK (PCLK),
.PCLKG (PCLKG),
.PRESETn (PRESETn),
.PCLKEN (PCLKEN),
// Common AHB signals
.HADDR (HADDR),
.HTRANS (HTRANS),
.HSIZE (HSIZE),
.HWRITE (HWRITE),
.HWDATA (HWDATA),
.HREADY (HREADY),
// Flash
.flash_hsel (flash_hsel),
.flash_hreadyout (flash_hreadyout),
.flash_hrdata (flash_hrdata),
.flash_hresp (flash_hresp),
// SRAM
.sram_hsel (sram_hsel),
.sram_hreadyout (sram_hreadyout),
.sram_hrdata (sram_hrdata),
.sram_hresp (sram_hresp),
// Optional boot loader
// Only use if BOOT_MEM_TYPE is not zero
.boot_hsel (boot_hsel),
.boot_hreadyout (boot_hreadyout),
.boot_hrdata (boot_hrdata),
.boot_hresp (boot_hresp),
// Status
.APBACTIVE (APBACTIVE),
.SLEEPING (SLEEPING),
.SYSRESETREQ (SYSRESETREQ),
.WDOGRESETREQ (WDOGRESETREQ),
.LOCKUP (LOCKUP),
.LOCKUPRESET (LOCKUPRESET),
.PMUENABLE (PMUENABLE),
.SLEEPDEEP (SLEEPDEEP),
`ifdef CORTEX_M0DESIGNSTART
`else //if using DesignStart CortexM0, remove these signals
.GATEHCLK (GATEHCLK),
.WAKEUP (WAKEUP),
.WICENREQ (WICENREQ),
.WICENACK (WICENACK),
.CDBGPWRUPREQ (CDBGPWRUPREQ),
.CDBGPWRUPACK (CDBGPWRUPACK),
.SLEEPHOLDREQn (SLEEPHOLDREQn),
.SLEEPHOLDACKn (SLEEPHOLDACKn),
// Debug
.nTRST (i_trst_n),
.SWDITMS (i_swditms),
.SWCLKTCK (i_swclktck),
.TDI (i_tdi),
.TDO (i_tdo),
.nTDOEN (i_tdoen_n),
.SWDO (i_swdo),
.SWDOEN (i_swdoen),
`endif
// UART
.uart0_rxd (uart0_rxd),
.uart0_txd (uart0_txd),
.uart0_txen (uart0_txen),
.uart1_rxd (uart1_rxd),
.uart1_txd (uart1_txd),
.uart1_txen (uart1_txen),
.uart2_rxd (uart2_rxd),
.uart2_txd (uart2_txd),
.uart2_txen (uart2_txen),
// Timer
.timer0_extin (timer0_extin),
.timer1_extin (timer1_extin),
// IO Ports
.p0_in (p0_in),
.p0_out (p0_out),
.p0_outen (p0_outen),
.p0_altfunc (p0_altfunc),
.p1_in (p1_in),
.p1_out (p1_out),
.p1_outen (p1_outen),
.p1_altfunc (p1_altfunc),
// DMA Control
// .dma_req (dma230_tie0),
// .dma_sreq (dma230_tie0),
// .dma_waitonreq (dma230_tie0),
// .dma_stall (1'b0),
// .dma_active (),
.dma_done (dmac_done),
.dma_err (dmac_err),
// AHB-Lite Master Interface
.dmac_hready (dmac_hready),
.dmac_hresp (dmac_hresp),
.dmac_hrdata (dmac_hrdata),
.dmac_htrans (dmac_htrans),
.dmac_hwrite (dmac_hwrite),
.dmac_haddr (dmac_haddr),
.dmac_hsize (dmac_hsize),
.dmac_hburst (dmac_hburst),
.dmac_hmastlock (dmac_hmastlock),
.dmac_hprot (dmac_hprot),
.dmac_hwdata (dmac_hwdata),
// APB Slave Interface
.dmac_psel (dmac_psel),
.exp_penable (exp_penable),
.exp_pwrite (exp_pwrite),
.exp_paddr (exp_paddr[11:0]),
.exp_pwdata (exp_pwdata[31:0]),
.dmac_prdata (dmac_prdata),
.dmac_pready (1'b1),
.dmac_pslverr (1'b0),
.DFTSE (1'b0)
);
//----------------------------------------
// If DMA is present, use SCLK for system HCLK so that
// DMA can run even if processor is in sleep mode.
// Otherwise there is only one master (cpu), so AHB system
// clock can be stopped when DMA take place.
// assign HCLKSYS = (INCLUDE_DMA!=0) ? SCLK : HCLK;
assign HCLKSYS = SCLK;
//----------------------------------------
// Flash memory
//----------------------------------------
cmsdk_ahb_rom
#(.MEM_TYPE(ROM_MEM_TYPE),
.AW(16), // 64K bytes flash ROM
.filename("image.hex"),
.WS_N(`ARM_CMSDK_ROM_MEM_WS_N),
.WS_S(`ARM_CMSDK_ROM_MEM_WS_S),
.BE (BE))
u_ahb_rom (
.HCLK (HCLKSYS),
.HRESETn (HRESETn),
.HSEL (flash_hsel), // AHB inputs
.HADDR (HADDR[15:0]),
.HTRANS (HTRANS),
.HSIZE (HSIZE),
.HWRITE (HWRITE),
.HWDATA (HWDATA),
.HREADY (HREADY),
.HREADYOUT (flash_hreadyout), // Outputs
.HRDATA (flash_hrdata),
.HRESP (flash_hresp)
);
//----------------------------------------
// Boot loader / Firmware
//----------------------------------------
// Only use if BOOT_MEM_TYPE is not zero
cmsdk_ahb_rom
#(.MEM_TYPE(BOOT_MEM_TYPE),
.AW(12), // 4K bytes ROM
.filename("bootloader.hex"),
.WS_N(`ARM_CMSDK_BOOT_MEM_WS_N),
.WS_S(`ARM_CMSDK_BOOT_MEM_WS_S),
.BE (BE))
u_ahb_bootloader (
.HCLK (HCLKSYS),
.HRESETn (HRESETn),
.HSEL (boot_hsel), // AHB inputs
.HADDR (HADDR[11:0]),
.HTRANS (HTRANS),
.HSIZE (HSIZE),
.HWRITE (HWRITE),
.HWDATA (HWDATA),
.HREADY (HREADY),
.HREADYOUT (boot_hreadyout), // Outputs
.HRDATA (boot_hrdata),
.HRESP (boot_hresp)
);
//----------------------------------------
// SRAM
//----------------------------------------
cmsdk_ahb_ram
#(.MEM_TYPE(RAM_MEM_TYPE),
.AW(16), // 64K bytes SRAM
.WS_N(`ARM_CMSDK_RAM_MEM_WS_N),
.WS_S(`ARM_CMSDK_RAM_MEM_WS_S))
u_ahb_ram (
.HCLK (HCLKSYS),
.HRESETn (HRESETn),
.HSEL (sram_hsel), // AHB inputs
.HADDR (HADDR[15:0]),
.HTRANS (HTRANS),
.HSIZE (HSIZE),
.HWRITE (HWRITE),
.HWDATA (HWDATA),
.HREADY (HREADY),
.HREADYOUT (sram_hreadyout), // Outputs
.HRDATA (sram_hrdata),
.HRESP (sram_hresp)
);
//----------------------------------------
// MTB SRAM Memory
//----------------------------------------
`ifdef CORTEX_M0PLUS
`ifdef ARM_CMSDK_INCLUDE_MTB
cm0p_ik_sram
#(.MEMNAME ("MTB SRAM"),
.DATAWIDTH (32),
.ADDRWIDTH (AWIDTH-2),
.MEMBASE (BASEADDR_MTBSRAM))
u_mtbram
(//Output
.RDATA (RAMRD),
//Inputs
.CLK (RAMHCLK),
.ADDRESS (RAMAD[AWIDTH-3:0]),
.CS (RAMCS),
.WE (RAMWE),
.WDATA (RAMWD));
`endif
`endif
//----------------------------------------
// I/O port pin muxing and tristate
//----------------------------------------
cmsdk_mcu_pin_mux
u_pin_mux (
// UART
.uart0_rxd (uart0_rxd),
.uart0_txd (uart0_txd),
.uart0_txen (uart0_txen),
.uart1_rxd (uart1_rxd),
.uart1_txd (uart1_txd),
.uart1_txen (uart1_txen),
.uart2_rxd (uart2_rxd),
.uart2_txd (uart2_txd),
.uart2_txen (uart2_txen),
// Timer
.timer0_extin (timer0_extin),
.timer1_extin (timer1_extin),
`ifdef CORTEX_M0PLUS
`ifdef ARM_CMSDK_INCLUDE_MTB
// MTB CONTROL
.TSTART (TSTART),
.TSTOP (TSTOP),
`endif
`endif
// IO Ports
.p0_in (p0_in),
.p0_out (p0_out),
.p0_outen (p0_outen),
.p0_altfunc (p0_altfunc),
.p1_in (p1_in),
.p1_out (p1_out),
.p1_outen (p1_outen),
.p1_altfunc (p1_altfunc),
// Debug
.i_trst_n (i_trst_n),
.i_swditms (i_swditms),
.i_swclktck (i_swclktck),
.i_tdi (i_tdi),
.i_tdo (i_tdo),
.i_tdoen_n (i_tdoen_n),
.i_swdo (i_swdo),
.i_swdoen (i_swdoen),
// IO pads
.P0 (P0),
.P1 (P1),
.nTRST (nTRST), // Not needed if serial-wire debug is used
.TDI (TDI), // Not needed if serial-wire debug is used
.SWDIOTMS (SWDIOTMS),
.SWCLKTCK (SWCLKTCK),
.TDO (TDO) // Not needed if serial-wire debug is used
);
// --------------------------------------------------------------------------------
// Assertion properties for configuration check
// --------------------------------------------------------------------------------
`ifdef ARM_AHB_ASSERT_ON
`include "std_ovl_defines.h"
assert_never
#(`OVL_FATAL,`OVL_ASSERT,
"No program ROM. Verilog parameter ROM_MEM_TYPE is set to AHB_ROM_NONE, which is not valid for a CMSDK system.")
u_ovl_rom_config_check
(.clk(HCLK), .reset_n(HRESETn), .test_expr (ROM_MEM_TYPE==`AHB_ROM_NONE));
assert_never
#(`OVL_FATAL,`OVL_ASSERT,
"No SRAM. Verilog parameter RAM_MEM_TYPE is set to AHB_RAM_NONE, which is not valid for a CMSDK system.")
u_ovl_ram_config_check
(.clk(HCLK), .reset_n(HRESETn), .test_expr (RAM_MEM_TYPE==`AHB_RAM_NONE));
`endif
endmodule
This page: |
Created: | Wed Nov 24 14:08:44 2021 |
|
From: |
../verilog/cmsdk_mcu.v |