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// from GLIB_PADLIB.v
//-----------------------------------------------------------------------------
// soclabs generic IO pad model
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Flynn (d.w.flynn@soton.ac.uk)
//
// Copyright © 2022, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------

// core logic supply rails (1V0, 0V)
[Up: cmsdk_mcu_chip_pads uPAD_VDD_1]
module PAD_VDDSOCIndex (
   PAD
   );
   inout PAD;
   assign PAD = 1'b1;
endmodule // PAD_VDDSOC

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This page: Created:Wed Nov 16 11:46:42 2022
From: ../../../../../GLIB/pads/verilog/PAD_VDDSOC.v

Verilog converted to html by v2html 7.30.1.3 (written by Costas Calamvokis).Help