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[Up: cmsdk_mcu_chip u_ahb_bootloader]
module ahb_bootromIndex #(
  // Parameters
  parameter AW       = 10 // Address width
 )
 (
 input  wire          HCLK,    // Clock
 input  wire          HRESETn, // Reset
 input  wire          HSEL,    // Device select
 input  wire [AW-1:0] HADDR,   // Address
 input  wire    [1:0] HTRANS,  // Transfer control
 input  wire    [2:0] HSIZE,   // Transfer size
 input  wire          HWRITE,  // Write control
 input  wire   [31:0] HWDATA,  // Write data - not used
 input  wire          HREADY,  // Transfer phase done
 output wire          HREADYOUT, // Device ready
 output wire   [31:0] HRDATA,  // Read data output
 output wire          HRESP   // Device response (always OKAY)
);

 bootrom u_bootrom (
 .CLK   (HCLK),
 .EN    (HSEL & HTRANS[1] & HREADY & !HWRITE),
 .ADDR  (HADDR[AW-1:2]),
 .RDATA (HRDATA)
 );
 assign HREADYOUT = 1'b1;
 assign HRESP = 1'b0;

endmodule

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This page: Created:Wed Nov 16 11:46:42 2022
From: ../verilog/ahb_bootrom.v

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