//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited.
//
// (C) COPYRIGHT 2006-2007 ARM Limited.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited.
//
// File Name : pl230_dma_data.v
// Checked In : $Date: 2007-03-15 15:17:04 +0530 (Thu, 15 Mar 2007) $
// Revision : $Revision: 10866 $
// State : $state: PL230-DE-98007-r0p0-02rel0 $
//
//-----------------------------------------------------------------------------
// Purpose : Multiplex DMA data byte lanes
//
//-----------------------------------------------------------------------------
`include "pl230_defs.v"
module pl230_dma_data
(
// DMA Data Control
src_size,
src_addr,
// DMA Source Data
hrdata,
// DMA Destination Data
dma_data_nxt
);
//----------------------------------------------------------------------------
// Block Parameters
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// Port declarations
//----------------------------------------------------------------------------
// DMA Data Control
input [1:0] src_size; // Source transfer size
input [1:0] src_addr; // Source four byte address
// DMA Source Data
input [31:0] hrdata; // AHB read data
// DMA Destination Data
output [31:0] dma_data_nxt; // DMA data next value
//----------------------------------------------------------------------------
// Port signal declarations
//----------------------------------------------------------------------------
// DMA data next value
reg [31:0] dma_data_nxt;
//----------------------------------------------------------------------------
// Local signal declarations
//----------------------------------------------------------------------------
// Byte select control conditions concatenation
wire [3:0] byte_control;
// Byte select 0 for destination data
wire [1:0] byte_sel0;
// Byte select 1 for destination data
wire [1:0] byte_sel1;
// Byte select 2 for destination data
wire [1:0] byte_sel2;
// Byte select 3 for destination data
wire [1:0] byte_sel3;
//----------------------------------------------------------------------------
//
// Beginning of main code
//
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// AHB data interface
//----------------------------------------------------------------------------
// Byte control variables
assign byte_control = {src_size, src_addr};
// Byte select 0
assign byte_sel0[0] =
// Byte
(byte_control[3:0] == {2'b00, 2'b01}) ||
(byte_control[3:0] == {2'b00, 2'b11})
// Half-word
// Word
// Reserved
;
assign byte_sel0[1] =
// Byte
(byte_control[3:0] == {2'b00, 2'b10}) ||
(byte_control[3:0] == {2'b00, 2'b11}) ||
// Half-word
(byte_control[3:1] == {2'b01, 1'b1 })
// Word
// Reserved
;
// Byte select 1
assign byte_sel1[0] =
// Byte
(byte_control[3:0] == {2'b00, 2'b01}) ||
(byte_control[3:0] == {2'b00, 2'b11}) ||
// Half-word
(byte_control[3:1] == {2'b01, 1'b0 }) ||
(byte_control[3:1] == {2'b01, 1'b1 }) ||
// Word
(byte_control[3:2] == {2'b10 }) ||
// Reserved
(byte_control[3:2] == {2'b11 })
;
assign byte_sel1[1] =
// Byte
(byte_control[3:0] == {2'b00, 2'b10}) ||
(byte_control[3:0] == {2'b00, 2'b11}) ||
// Half-word
(byte_control[3:1] == {2'b01, 1'b1 })
// Word
// Reserved
;
// Byte select 2
assign byte_sel2[0] =
// Byte
(byte_control[3:0] == {2'b00, 2'b01}) ||
(byte_control[3:0] == {2'b00, 2'b11})
// Half-word
// Word
// Reserved
;
assign byte_sel2[1] =
// Byte
(byte_control[3:0] == {2'b00, 2'b10}) ||
(byte_control[3:0] == {2'b00, 2'b11}) ||
// Half-word
(byte_control[3:1] == {2'b01, 1'b1 }) ||
// Word
(byte_control[3:2] == {2'b10 }) ||
// Reserved
(byte_control[3:2] == {2'b11 })
;
// Byte select 3
assign byte_sel3[0] =
// Byte
(byte_control[3:0] == {2'b00, 2'b01}) ||
(byte_control[3:0] == {2'b00, 2'b11}) ||
// Half-word
(byte_control[3:1] == {2'b01, 1'b0 }) ||
(byte_control[3:1] == {2'b01, 1'b1 }) ||
// Word
(byte_control[3:2] == {2'b10 }) ||
// Reserved
(byte_control[3:2] == {2'b11 })
;
assign byte_sel3[1] =
// Byte
(byte_control[3:0] == {2'b00, 2'b10}) ||
(byte_control[3:0] == {2'b00, 2'b11}) ||
// Half-word
(byte_control[3:1] == {2'b01, 1'b1 }) ||
// Word
(byte_control[3:2] == {2'b10 }) ||
// Reserved
(byte_control[3:2] == {2'b11 })
;
// Destination Byte 0 Multiplexor
always @( byte_sel0 or hrdata )
begin : p_dma_data_nxt_7_0
case ( byte_sel0 )
2'b00:
dma_data_nxt[7:0] = hrdata[7:0];
2'b01:
dma_data_nxt[7:0] = hrdata[15:8];
2'b10:
dma_data_nxt[7:0] = hrdata[23:16];
2'b11:
dma_data_nxt[7:0] = hrdata[31:24];
default:
dma_data_nxt[7:0] = 8'hxx;
endcase
end // p_dma_data_nxt_7_0
// Destination Byte 1 Multiplexor
always @( byte_sel1 or hrdata )
begin : p_dma_data_nxt_15_8
case ( byte_sel1 )
2'b00:
dma_data_nxt[15:8] = hrdata[7:0];
2'b01:
dma_data_nxt[15:8] = hrdata[15:8];
2'b10:
dma_data_nxt[15:8] = hrdata[23:16];
2'b11:
dma_data_nxt[15:8] = hrdata[31:24];
default:
dma_data_nxt[15:8] = 8'hxx;
endcase
end // p_dma_data_nxt_15_8
// Destination Byte 2 Multiplexor
always @( byte_sel2 or hrdata )
begin : p_dma_data_nxt_23_16
case ( byte_sel2 )
2'b00:
dma_data_nxt[23:16] = hrdata[7:0];
2'b01:
dma_data_nxt[23:16] = hrdata[15:8];
2'b10:
dma_data_nxt[23:16] = hrdata[23:16];
2'b11:
dma_data_nxt[23:16] = hrdata[31:24];
default:
dma_data_nxt[23:16] = 8'hxx;
endcase
end // p_dma_data_nxt_23_16
// Destination Byte 3 Multiplexor
always @( byte_sel3 or hrdata )
begin : p_dma_data_nxt_31_24
case ( byte_sel3 )
2'b00:
dma_data_nxt[31:24] = hrdata[7:0];
2'b01:
dma_data_nxt[31:24] = hrdata[15:8];
2'b10:
dma_data_nxt[31:24] = hrdata[23:16];
2'b11:
dma_data_nxt[31:24] = hrdata[31:24];
default:
dma_data_nxt[31:24] = 8'hxx;
endcase
end // p_dma_data_nxt_31_24
endmodule // pl230_dma_data
`include "pl230_undefs.v"
This page: |
Created: | Wed Nov 16 11:46:43 2022 |
|
From: |
../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_dma_data.v |