.HWRITE (sys_hwrite),
.HADDR (sys_haddr[11:0]),
.HWDATA (sys_hwdata),
// AHB Outputs
.HREADYOUT (gpio1_hreadyout),
.HRESP (gpio1_hresp),
.HRDATA (gpio1_hrdata),
.ECOREVNUM (4'h0),// Engineering-change-order revision bits
.PORTIN (p1_in), // GPIO Interface inputs
.PORTOUT (p1_out), // GPIO Interface outputs
.PORTEN (p1_outen),
.PORTFUNC (p1_altfunc), // Alternate function control
.GPIOINT (), // Interrupt outputs
.COMBINT (gpio1_combintr)
);
assign IOMATCH = 1'b0;
assign IORDATA = {32{(1'b0)}};
// APB subsystem for timers, UARTs
cmsdk_apb_subsystem #(
.APB_EXT_PORT12_ENABLE (0),
.APB_EXT_PORT13_ENABLE (0),
.APB_EXT_PORT14_ENABLE (1),
.APB_EXT_PORT15_ENABLE (INCLUDE_DMA),
.INCLUDE_IRQ_SYNCHRONIZER(0),
.INCLUDE_APB_TEST_SLAVE (1),
.INCLUDE_APB_TIMER0 (1), // Include simple timer #0
.INCLUDE_APB_TIMER1 (1), // Include simple timer #1
.INCLUDE_APB_DUALTIMER0 (1), // Include dual timer module
.INCLUDE_APB_UART0 (1), // Include simple UART #0
.INCLUDE_APB_UART1 (1), // Include simple UART #1
.INCLUDE_APB_UART2 (1), // Include simple UART #2.
.INCLUDE_APB_WATCHDOG (1), // Include APB watchdog module
.BE (BE)
)
u_apb_subsystem(
// AHB interface for AHB to APB bridge
.HCLK (HCLKSYS),
.HRESETn (HRESETn),
.HSEL (apbsys_hsel),
.HADDR (sys_haddr[15:0]),
.HTRANS (sys_htrans[1:0]),
.HWRITE (sys_hwrite),
.HSIZE (sys_hsize),
.HPROT (sys_hprot),
.HREADY (sys_hready),
.HWDATA (sys_hwdata[31:0]),
.HREADYOUT (apbsys_hreadyout),
.HRDATA (apbsys_hrdata),
.HRESP (apbsys_hresp),
// APB clock and reset
.PCLK (PCLK),
.PCLKG (PCLKG),
.PCLKEN (PCLKEN),
.PRESETn (PRESETn),
// APB extension ports
.PADDR (exp_paddr[11:0]),
.PWRITE (exp_pwrite),
.PWDATA (exp_pwdata[31:0]),
.PENABLE (exp_penable),
.ext12_psel (exp12_psel),
.ext13_psel (exp13_psel),
.ext14_psel (exp14_psel),
.ext15_psel (dmac_psel),
// Input from APB devices on APB expansion ports
.ext12_prdata (exp12_prdata),
.ext12_pready (exp12_pready),
.ext12_pslverr (exp12_pslverr),
.ext13_prdata (exp13_prdata),
.ext13_pready (exp13_pready),
.ext13_pslverr (exp13_pslverr),
.ext14_prdata (exp14_prdata),
.ext14_pready (exp14_pready),
.ext14_pslverr (exp14_pslverr),
.ext15_prdata (dmac_prdata),
.ext15_pready (dmac_pready),
.ext15_pslverr (dmac_pslverr),
.APBACTIVE (APBACTIVE), // Status Output for clock gating
// Peripherals
// UART
.uart0_rxd (uart0_rxd),
.uart0_txd (uart0_txd),
.uart0_txen (uart0_txen),
.uart1_rxd (uart1_rxd),
.uart1_txd (uart1_txd),
.uart1_txen (uart1_txen),
.uart2_rxd (uart2_rxd),
.uart2_txd (uart2_txd),
.uart2_txen (uart2_txen),
// Timer
.timer0_extin (timer0_extin),
.timer1_extin (timer1_extin),
// Interrupt outputs
.apbsubsys_interrupt (apbsubsys_interrupt),
.watchdog_interrupt (watchdog_interrupt),
// reset output
.watchdog_reset (WDOGRESETREQ)
);
// Connect system bus to external
assign HADDR = sys_haddr;
assign HTRANS = sys_htrans;
assign HSIZE = sys_hsize;
assign HWRITE = sys_hwrite;
assign HWDATA = sys_hwdata;
assign HREADY = sys_hready;
// -------------------------------
// DMA Controller
// -------------------------------
// DMA interface external in this example system
// -------------------------------
// Interrupt assignment
// -------------------------------
assign intnmi_cm0 = watchdog_interrupt;
assign intisr_cm0[ 5: 0] = apbsubsys_interrupt[ 5: 0];
assign intisr_cm0[ 6] = apbsubsys_interrupt[ 6] | gpio0_combintr;
assign intisr_cm0[ 7] = apbsubsys_interrupt[ 7] | gpio1_combintr;
assign intisr_cm0[14: 8] = apbsubsys_interrupt[14: 8];
assign intisr_cm0[15] = apbsubsys_interrupt[15] | dmac_done | dmac_err;
assign intisr_cm0[31:16] = apbsubsys_interrupt[31:16]| gpio0_intr;
// -------------------------------
// SysTick signals
// -------------------------------
cmsdk_mcu_stclkctrl
#(.DIV_RATIO (18'd01000))
u_cmsdk_mcu_stclkctrl (
.FCLK (FCLK),
.SYSRESETn (HRESETn),
.STCLKEN (STCLKEN),
.STCALIB (STCALIB)
);
// --------------------------------------------------------------------------------
// Verification components
// --------------------------------------------------------------------------------
`ifdef ARM_AHB_ASSERT_ON
// AHB protocol checker for process bus
AhbLitePC #(
.ADDR_WIDTH (32),
.DATA_WIDTH (32),
.BIG_ENDIAN (BE),
.MASTER_TO_INTERCONNECT ( 1),
.EARLY_BURST_TERMINATION ( 0),
// Property type (0=prove, 1=assume, 2=ignore)
.MASTER_REQUIREMENT_PROPTYPE ( 0),
.MASTER_RECOMMENDATION_PROPTYPE ( 0),
.MASTER_XCHECK_PROPTYPE ( 0),
.SLAVE_REQUIREMENT_PROPTYPE ( 0),
.SLAVE_RECOMMENDATION_PROPTYPE ( 0),
.SLAVE_XCHECK_PROPTYPE ( 0),
.INTERCONNECT_REQUIREMENT_PROPTYPE ( 0),
.INTERCONNECT_RECOMMENDATION_PROPTYPE ( 0),
.INTERCONNECT_XCHECK_PROPTYPE ( 0)
) u_AhbLitePC_processor
(
// clock
.HCLK (HCLKSYS),
// active low reset
.HRESETn (HRESETn),
// Main Master signals
.HADDR (cm0_haddr),
.HTRANS (cm0_htrans),
.HWRITE (cm0_hwrite),
.HSIZE (cm0_hsize),
.HBURST (cm0_hburst),
.HPROT (cm0_hprot),
.HWDATA (cm0_hwdata),
// Main Decoder signals
.HSELx (1'bx), // Ignored for this instance
// Main Slave signals
.HRDATA (cm0_hrdata),
.HREADY (cm0_hready),
.HREADYOUT (1'bx), // Ignored for this instance
.HRESP (cm0_hresp),
// HMASTER, // NOTE: not used
.HMASTLOCK (cm0_hmastlock)
);
generate if (INCLUDE_DMA != 0) begin : gen_ahblite_with_dma
// AHB protocol checker for DMA bus
AhbLitePC #(
.ADDR_WIDTH (32),
.DATA_WIDTH (32),
.BIG_ENDIAN (BE),
.MASTER_TO_INTERCONNECT ( 1),
.EARLY_BURST_TERMINATION ( 0),
// Property type (0=prove, 1=assume, 2=ignore)
.MASTER_REQUIREMENT_PROPTYPE ( 0),
.MASTER_RECOMMENDATION_PROPTYPE ( 0),
.MASTER_XCHECK_PROPTYPE ( 0),
.SLAVE_REQUIREMENT_PROPTYPE ( 0),
.SLAVE_RECOMMENDATION_PROPTYPE ( 0),
.SLAVE_XCHECK_PROPTYPE ( 0),
.INTERCONNECT_REQUIREMENT_PROPTYPE ( 0),
.INTERCONNECT_RECOMMENDATION_PROPTYPE ( 0),
.INTERCONNECT_XCHECK_PROPTYPE ( 0)
) u_AhbLitePC_dma
(
// clock
.HCLK (HCLKSYS),
// active low reset
.HRESETn (HRESETn),
// Main Master signals
.HADDR (ahbx_haddr),
.HTRANS (ahbx_htrans),
.HWRITE (ahbx_hwrite),
.HSIZE (ahbx_hsize),
.HBURST (ahbx_hburst),
.HPROT (ahbx_hprot),
.HWDATA (ahbx_hwdata),
// Main Decoder signals
.HSELx (1'bx), // Ignored for this instance
// Main Slave signals
.HRDATA (ahbx_hrdata),
.HREADY (ahbx_hready),
.HREADYOUT (1'bx), // Ignored for this instance
.HRESP (ahbx_hresp),
.HMASTLOCK (ahbx_hmastlock)
);
// AHB protocol checker for the out bus from bus multiplexer
// AHB-Lite slave interface
AhbLitePC #(
.ADDR_WIDTH (32),
.DATA_WIDTH (32),
.BIG_ENDIAN (BE),
.MASTER_TO_INTERCONNECT ( 1),
.EARLY_BURST_TERMINATION ( 0),
// Property type (0=prove, 1=assume, 2=ignore)
.MASTER_REQUIREMENT_PROPTYPE ( 0),
.MASTER_RECOMMENDATION_PROPTYPE ( 0),
.MASTER_XCHECK_PROPTYPE ( 0),
.SLAVE_REQUIREMENT_PROPTYPE ( 0),
.SLAVE_RECOMMENDATION_PROPTYPE ( 0),
.SLAVE_XCHECK_PROPTYPE ( 0),
.INTERCONNECT_REQUIREMENT_PROPTYPE ( 0),
.INTERCONNECT_RECOMMENDATION_PROPTYPE ( 0),
.INTERCONNECT_XCHECK_PROPTYPE ( 0)
) u_AhbLitePC_sys
(
// clock
.HCLK (HCLKSYS),
// active low reset
.HRESETn (HRESETn),
// Main Master signals
.HADDR (sys_haddr),
.HTRANS (sys_htrans),
.HWRITE (sys_hwrite),
.HSIZE (sys_hsize),
.HBURST (sys_hburst),
.HPROT (sys_hprot),
.HWDATA (sys_hwdata),
// Main Decoder signals
.HSELx (1'bx), // Ignored for this instance
// Main Slave signals
.HRDATA (sys_hrdata),
.HREADY (sys_hready),
.HREADYOUT (1'bx), // Ignored for this instance
.HRESP (sys_hresp),
.HMASTLOCK (ahbx_hmastlock)
);
end endgenerate
`endif
endmodule
This page: |
Created: | Wed Nov 16 11:46:43 2022 |
|
From: |
../verilog/cmsdk_mcu_system.v |