//-----------------------------------------------------------------------------
// customised example Cortex-M0 controller
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Flynn (d.w.flynn@soton.ac.uk)
//
// Copyright © 2021, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from Arm Limited or its affiliates.
//
// SVN Information
//
// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
//
// Revision : $Revision: 371321 $
//
// Release Information : Cortex-M System Design Kit-r1p1-00rel0
//
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : System level design for the example Cortex-M0 system
//-----------------------------------------------------------------------------
`include "cmsdk_mcu_defs.v"
module cmsdk_mcu_system
#(
`ifdef ARM_CMSDK_INCLUDE_CLKGATE
parameter CLKGATE_PRESENT = 1,
`else
parameter CLKGATE_PRESENT = 0,
`endif
parameter BASEADDR_GPIO0 = 32'h4001_0000, // GPIO0 peripheral base address
parameter BASEADDR_GPIO1 = 32'h4001_1000, // GPIO1 peripheral base address
parameter BE = 0, // 1: Big endian 0: little endian
parameter BKPT = 4, // Number of breakpoint comparators
parameter DBG = 1, // Debug configuration
parameter NUMIRQ = 32, // NUM of IRQ
parameter SMUL = 0, // Multiplier configuration
parameter SYST = 1, // SysTick
parameter WIC = 1, // Wake-up interrupt controller support
parameter WICLINES = 34, // Supported WIC lines
parameter WPT = 2, // Number of DWT comparators
parameter RESET_ALL_REGS = 0, // Do not reset all registers
parameter BOOT_MEM_TYPE = `ARM_CMSDK_BOOT_MEM_TYPE, // Boot loader memory type
`ifdef ARM_CMSDK_INCLUDE_DMA
parameter INCLUDE_DMA = 1, // Include instantiation of DMA-230
// This option also add a number of bus components
parameter DMA_CHANNEL_NUM = 1,
`else
parameter INCLUDE_DMA = 0, // Do not instantiation DMA-230
parameter DMA_CHANNEL_NUM = 1,
`endif
parameter INCLUDE_BITBAND = 0,
`ifdef ARM_CMSDK_INCLUDE_JTAG
parameter INCLUDE_JTAG = 1, // Include JTAG feature
`else
parameter INCLUDE_JTAG = 0, // Do not Include JTAG feature
`endif
// Generate BOOT_LOADER_PRESENT based on BOOT_MEM_TYPE
// This is a derived parameter - do not override using instiantiation
parameter BOOT_LOADER_PRESENT = (BOOT_MEM_TYPE==0) ? 0 : 1,
// Location of the System ROM Table.
parameter BASEADDR_SYSROMTABLE = 32'hF000_0000
)
(
input wire FCLK, // Free running clock
input wire HCLK, // AHB clock(from PMU)
input wire SCLK, // System clock
input wire HRESETn, // AHB and System reset
input wire PORESETn, // Power on reset
`ifdef CORTEX_M0
input wire DCLK, // Debug clock
input wire DBGRESETn, // Debug reset
input wire RSTBYPASS, // Reset by pass (for testing)
`endif
input wire PCLK, // Peripheral clock
input wire PCLKG, // Gated Peripheral bus clock
input wire PRESETn, // Peripheral system and APB reset
input wire PCLKEN, // Clock divide control for AHB to APB bridge
output wire [31:0] HADDR, // AHB to memory blocks - address
output wire [1:0] HTRANS, // AHB to memory blocks - transfer ctrl
output wire [2:0] HSIZE, // AHB to memory blocks - transfer size
output wire HWRITE, // AHB to memory blocks - write ctrl
output wire [31:0] HWDATA, // AHB to memory blocks - write data
output wire HREADY, // AHB to memory blocks - AHB ready
output wire flash_hsel, // AHB to flash memory - select
input wire flash_hreadyout, // AHB from flash blocks - ready
input wire [31:0] flash_hrdata, // AHB from flash blocks - read data
input wire flash_hresp, // AHB from flash blocks - response
output wire sram_hsel, // AHB to SRAM - select
input wire sram_hreadyout, // AHB from SRAM - ready
input wire [31:0] sram_hrdata, // AHB from SRAM - read data
input wire sram_hresp, // AHB from SRAM - response
// Optional : only if BOOT_MEM_TYPE!=0
output wire boot_hsel, // AHB to boot loader - select
input wire boot_hreadyout, // AHB from boot loader - ready
input wire [31:0] boot_hrdata, // AHB from boot loader - read data
input wire boot_hresp, // AHB from boot loader - response
output wire APBACTIVE, // APB bus active (for clock gating of PCLKG)
output wire SLEEPING, // Processor status - sleeping
output wire SLEEPDEEP, // Processor status - deep sleep
output wire SYSRESETREQ, // Processor control - system reset request
output wire WDOGRESETREQ, // Watchdog reset request
output wire LOCKUP, // Processor status - Locked up
output wire LOCKUPRESET, // System Controller cfg - reset if lockup
output wire PMUENABLE, // System Controller cfg - Enable PMU
`ifdef CORTEX_M0DESIGNSTART
`else //if using DesignStart Cortex-M0, remove these signals
output wire GATEHCLK, // Processor status - safe to gate HCLK
output wire WAKEUP, // Wake up request from WIC
input wire WICENREQ, // WIC enable request from PMU
output wire WICENACK, // WIC enable ack to PMU
output wire CDBGPWRUPREQ, // Debug Power Up request to PMU
input wire CDBGPWRUPACK, // Debug Power Up ACK from PMU
input wire SLEEPHOLDREQn, // Sleep extension request from PMU
output wire SLEEPHOLDACKn, // Sleep extension request to PMU
input wire nTRST, // JTAG - Test reset (active low)
input wire SWDITMS, // JTAG/SWD - TMS / SWD data input
input wire SWCLKTCK, // JTAG/SWD - TCK / SWCLK
input wire TDI, // JTAG - Test data in
output wire TDO, // JTAG - Test data out
output wire nTDOEN, // JTAG - Test data out enable (active low)
output wire SWDO, // SWD - SWD data output
output wire SWDOEN, // SWD - SWD data output enable
`endif
input wire uart0_rxd, // Uart 0 receive data
output wire uart0_txd, // Uart 0 transmit data
output wire uart0_txen, // Uart 0 transmit data enable
input wire uart1_rxd, // Uart 1 receive data
output wire uart1_txd, // Uart 1 transmit data
output wire uart1_txen, // Uart 1 transmit data enable
input wire uart2_rxd, // Uart 2 receive data
output wire uart2_txd, // Uart 2 transmit data
output wire uart2_txen, // Uart 2 transmit data enable
input wire timer0_extin, // Timer 0 external input
input wire timer1_extin, // Timer 1 external input
input wire [15:0] p0_in, // GPIO 0 inputs
output wire [15:0] p0_out, // GPIO 0 outputs
output wire [15:0] p0_outen, // GPIO 0 output enables
output wire [15:0] p0_altfunc, // GPIO 0 alternate function (pin mux)
input wire [15:0] p1_in, // GPIO 1 inputs
output wire [15:0] p1_out, // GPIO 1 outputs
output wire [15:0] p1_outen, // GPIO 1 output enables
output wire [15:0] p1_altfunc, // GPIO 1 alternate function (pin mux)
// AHB-Lite Master Interface
output wire ahbx_hready,
output wire ahbx_hresp,
output wire [31:0] ahbx_hrdata,
input wire [ 1:0] ahbx_htrans,
output wire ahbx_hwrite,
input wire [31:0] ahbx_haddr,
input wire [2 :0] ahbx_hsize,
input wire [2 :0] ahbx_hburst,
input wire ahbx_hmastlock,
input wire [3 :0] ahbx_hprot,
input wire [31:0] ahbx_hwdata,
// APB Slave Interface
output wire exp12_psel,
output wire exp13_psel,
output wire exp14_psel,
output wire exp_penable,
output wire exp_pwrite,
output wire [11:0] exp_paddr,
output wire [31:0] exp_pwdata,
input wire [31:0] exp12_prdata,
input wire exp12_pready,
input wire exp12_pslverr,
input wire [31:0] exp13_prdata,
input wire exp13_pready,
input wire exp13_pslverr,
input wire [31:0] exp14_prdata,
input wire exp14_pready,
input wire exp14_pslverr,
input wire DFTSE); // dummy scan enable port for synthesis
// -------------------------------
// Internal signals
// -------------------------------
wire HCLKSYS; // System AHB clock
// System bus from processor
wire [31:0] cm0_haddr;
wire [1:0] cm0_htrans;
wire [2:0] cm0_hsize;
wire [2:0] cm0_hburst;
wire [3:0] cm0_hprot;
wire cm0_hmaster;
wire cm0_hmastlock;
wire cm0_hwrite;
wire [31:0] cm0_hwdata;
wire [31:0] cm0_hrdata;
wire cm0_hready;
wire cm0_hresp;
// Bit band wrapper bus between CPU and the reset of the system
wire [31:0] cm_haddr;
wire [1:0] cm_htrans;
wire [2:0] cm_hsize;
wire [2:0] cm_hburst;
wire [3:0] cm_hprot;
wire cm_hmastlock;
wire cm_hmaster;
wire cm_hwrite;
wire [31:0] cm_hwdata;
wire [31:0] cm_hrdata;
wire cm_hready;
wire cm_hreadyout;
wire cm_hresp;
// DMA controller master interface
wire [31:0] dmac_haddr;
wire [1:0] dmac_htrans;
wire [2:0] dmac_hsize;
wire [2:0] dmac_hburst;
wire [3:0] dmac_hprot;
wire dmac_hmastlock;
wire dmac_hwrite;
wire [31:0] dmac_hwdata;
wire [31:0] dmac_hrdata;
wire dmac_hready;
wire dmac_hreadyout;
wire dmac_hresp;
wire dmac_done;
wire dmac_err;
wire dmac_psel;
wire dmac_pready;
wire dmac_pslverr;
wire [31:0] dmac_prdata;
// System bus
wire sys_hselm; // Note: the sys_hselm signal is for protocol checking only.
wire [31:0] sys_haddr;
wire [1:0] sys_htrans;
wire [2:0] sys_hsize;
wire [2:0] sys_hburst;
wire [3:0] sys_hprot;
wire sys_hmaster;
wire sys_hmastlock;
wire sys_hwrite;
wire [31:0] sys_hwdata;
wire [31:0] sys_hrdata;
wire sys_hready;
wire sys_hreadyout;
wire sys_hresp;
wire defslv_hsel; // AHB default slave signals
wire defslv_hreadyout;
wire [31:0] defslv_hrdata;
wire defslv_hresp;
wire apbsys_hsel; // APB subsystem AHB interface signals
wire apbsys_hreadyout;
wire [31:0] apbsys_hrdata;
wire apbsys_hresp;
wire gpio0_hsel; // AHB GPIO bus interface signals
wire gpio0_hreadyout;
wire [31:0] gpio0_hrdata;
wire gpio0_hresp;
wire gpio1_hsel; // AHB GPIO bus interface signals
wire gpio1_hreadyout;
wire [31:0] gpio1_hrdata;
wire gpio1_hresp;
wire sysctrl_hsel; // System control bus interface signals
wire sysctrl_hreadyout;
wire [31:0] sysctrl_hrdata;
wire sysctrl_hresp;
// MTB (Only available to the Cortex-M0+)
wire HSELMTB;
wire HREADYOUTMTB;
wire [31:0] HRDATAMTB;
wire HRESPMTB;
wire HSELSFR;
wire HSELRAM;
// System ROM Table
wire sysrom_hsel; // AHB to System ROM Table - select
wire sysrom_hreadyout; // AHB from System ROM Table - ready
wire [31:0] sysrom_hrdata; // AHB from System ROM Table - read data
wire sysrom_hresp; // AHB from System ROM Table - response
`ifdef CORTEX_M0PLUS
// Debug
wire DBGEN;
wire NIDEN;
wire SLVSTALL;
wire CPUWAIT;
// Processor status
wire [3:0] CODEHINT;
`endif
wire [1:0] sys_hmaster_i;
// APB expansion port signals
/// wire [11:0] exp_paddr;
/// wire [31:0] exp_pwdata;
/// wire exp_pwrite;
/// wire exp_penable;
wire [33:0] WICSENSE;
wire remap_ctrl;
// Interrupt request
wire [31:0] intisr_cm0;
wire intnmi_cm0;
wire [15:0] gpio0_intr;
wire gpio0_combintr;
wire gpio1_combintr;
wire [31:0] apbsubsys_interrupt;
wire watchdog_interrupt;
// I/O Port
wire IOMATCH;
wire [31:0] IORDATA;
wire IOTRANS;
wire IOWRITE;
wire [31:0] IOCHECK;
wire [31:0] IOADDR;
wire [ 1:0] IOSIZE;
wire IOMASTER;
wire IOPRIV;
wire [31:0] IOWDATA;
// event signals
wire TXEV;
wire RXEV;
// SysTick timer signals
wire STCLKEN;
wire [25:0] STCALIB;
// Processor debug signals
wire DBGRESTART;
wire DBGRESTARTED;
wire EDBGRQ;
// Processor status
wire HALTED;
`ifdef CORTEX_M0
wire [2:0] CODEHINTDE;
`endif
wire SPECHTRANS;
wire CODENSEQ;
wire SHAREABLE;
// -------------------------------
// Processor and power management
// -------------------------------
// If DMA is presented, use SCLK for system HCLK so that
// DMA can run even if processor is in sleep mode.
// Otherwise there is only one master (cpu), so AHB system
// clock can be stopped when DMA take place.
assign HCLKSYS = (INCLUDE_DMA!=0) ? SCLK : HCLK;
// assign HCLKSYS = SCLK;
`ifdef CORTEX_M0DESIGNSTART
// DESIGN START version, without PMU support
//instantiate the DesignStart Cortex M0
CORTEXM0DS
u_cortexm0_ds
(
// CLOCK AND RESETS ------------------
.HCLK (HCLK), // Clock
.HRESETn (HRESETn), // Asynchronous reset
// AHB-LITE MASTER PORT --------------
.HADDR (cm0_haddr),
.HTRANS (cm0_htrans),
.HSIZE (cm0_hsize),
.HBURST (cm0_hburst),
.HPROT (cm0_hprot),
.HMASTLOCK (cm0_hmastlock),
.HWRITE (cm0_hwrite),
.HWDATA (cm0_hwdata),
.HRDATA (cm0_hrdata),
.HREADY (cm0_hready),
.HRESP (cm0_hresp),
// MISCELLANEOUS ---------------------
.NMI (intnmi_cm0), // Non-maskable interrupt input
.IRQ (intisr_cm0[15:0]), // Interrupt request inputs
.TXEV (TXEV), // Event output (SEV executed)
.RXEV (RXEV), // Event input
.LOCKUP (LOCKUP), // Core is locked-up
.SYSRESETREQ (SYSRESETREQ), // System reset request
// POWER MANAGEMENT ------------------
.SLEEPING (SLEEPING) // Core and NVIC sleeping
);
// Force connect some signals to 0 or 1
assign SLEEPDEEP = 1'b0;
assign cm0_hmaster = 1'b0;
// Unused debug feature
assign DBGRESTART = 1'b0; // multi-core synchronous restart from halt
assign EDBGRQ = 1'b0; // multi-core synchronous halt request
assign RXEV = dmac_done; // Generate event when a DMA operation completed.
// No MTB in Cortex-M0
assign HRDATAMTB = {32{1'b0}};
assign HREADYOUTMTB = 1'b0;
assign HRESPMTB = 1'b0;
`else
`ifdef CORTEX_M0 // Cortex-M0 full version
// Cortex-M0 integration level
CORTEXM0INTEGRATION
#(.ACG (CLKGATE_PRESENT), // Architectural clock gating
.BE (BE), // Big-endian
.BKPT (BKPT), // Number of breakpoint comparators
.DBG (DBG), // Debug configuration
.JTAGnSW (INCLUDE_JTAG), // Debug port interface: JTAGnSW
.NUMIRQ (NUMIRQ), // Number of Interrupts
.RAR (RESET_ALL_REGS), // Reset All Registers
.SMUL (SMUL), // Multiplier configuration
.SYST (SYST), // SysTick
.WIC (WIC), // Wake-up interrupt controller support
.WICLINES (WICLINES), // Supported WIC lines
.WPT (WPT)) // Number of DWT comparators
u_cortex_m0_integration (
// System inputs
.FCLK (FCLK), // FCLK
.SCLK (SCLK), // SCLK generated from PMU
.HCLK (HCLK), // HCLK generated from PMU
.DCLK (DCLK), // DCLK generated from PMU
.PORESETn (PORESETn),
.HRESETn (HRESETn),
.DBGRESETn (DBGRESETn),
.RSTBYPASS (RSTBYPASS),
.SE (DFTSE),
// Power management inputs
.SLEEPHOLDREQn (SLEEPHOLDREQn),
.WICENREQ (WICENREQ),
.CDBGPWRUPACK (CDBGPWRUPACK),
// Power management outputs
.SLEEPHOLDACKn (SLEEPHOLDACKn),
.WICENACK (WICENACK),
.CDBGPWRUPREQ (CDBGPWRUPREQ),
.WAKEUP (WAKEUP),
.WICSENSE (WICSENSE),
.GATEHCLK (GATEHCLK),
.SYSRESETREQ (SYSRESETREQ),
// System bus
.HADDR (cm0_haddr),
.HTRANS (cm0_htrans),
.HSIZE (cm0_hsize),
.HBURST (cm0_hburst),
.HPROT (cm0_hprot),
.HMASTER (cm0_hmaster),
.HMASTLOCK (cm0_hmastlock),
.HWRITE (cm0_hwrite),
.HWDATA (cm0_hwdata),
.HRDATA (cm0_hrdata),
.HREADY (cm0_hready),
.HRESP (cm0_hresp),
.CODEHINTDE (CODEHINTDE),
.SPECHTRANS (SPECHTRANS),
.CODENSEQ (CODENSEQ),
// Interrupts
.IRQ (intisr_cm0[31:0]),
.NMI (intnmi_cm0),
.IRQLATENCY (8'h00),
.ECOREVNUM (28'h0),
// Systick
.STCLKEN (STCLKEN),
.STCALIB (STCALIB),
// Debug - JTAG or Serial wire
// inputs
.nTRST (nTRST),
.SWDITMS (SWDITMS),
.SWCLKTCK (SWCLKTCK),
.TDI (TDI),
// outputs
.TDO (TDO),
.nTDOEN (nTDOEN),
.SWDO (SWDO),
.SWDOEN (SWDOEN),
.DBGRESTART (DBGRESTART),
.DBGRESTARTED (DBGRESTARTED),
// Event communication
.TXEV (TXEV),
.RXEV (RXEV),
.EDBGRQ (EDBGRQ),
// Status output
.HALTED (HALTED),
.LOCKUP (LOCKUP),
.SLEEPING (SLEEPING),
.SLEEPDEEP (SLEEPDEEP)
);
// Unused debug feature
assign DBGRESTART = 1'b0; // multi-core synchronous restart from halt
assign EDBGRQ = 1'b0; // multi-core synchronous halt request
assign RXEV = dmac_done; // Generate event when a DMA operation completed.
// No MTB in Cortex-M0
assign HRDATAMTB = {32{1'b0}};
assign HREADYOUTMTB = 1'b0;
assign HRESPMTB = 1'b0;
`endif
`endif
// -------------------------------
// AHB system
// -------------------------------
generate if (INCLUDE_BITBAND != 0) begin : gen_ahb_bitband
cmsdk_ahb_bitband #(.MW(1), .BE(BE)) u_ahb_bitband (
// System
.HCLK (HCLKSYS),
.HRESETn (HRESETn),
.HSELS (1'b1),
.HADDRS (cm0_haddr),
.HTRANSS (cm0_htrans),
.HPROTS (cm0_hprot),
.HBURSTS (cm0_hburst),
.HMASTERS (cm0_hmaster),
.HMASTLOCKS (cm0_hmastlock),
.HSIZES (cm0_hsize),
.HWRITES (cm0_hwrite),
.HREADYS (cm0_hready),
.HWDATAS (cm0_hwdata),
.HREADYOUTS (cm0_hready),
.HRDATAS (cm0_hrdata),
.HRESPS (cm0_hresp),
.HSELM (),
.HADDRM (cm_haddr),
.HTRANSM (cm_htrans),
.HPROTM (cm_hprot),
.HBURSTM (cm_hburst),
.HMASTERM (cm_hmaster),
.HMASTLOCKM (cm_hmastlock),
.HSIZEM (cm_hsize),
.HWRITEM (cm_hwrite),
.HREADYM (cm_hready),
.HWDATAM (cm_hwdata),
.HREADYOUTM (cm_hreadyout),
.HRDATAM (cm_hrdata),
.HRESPM (cm_hresp)
);
end else begin : gen_no_ahb_bitband
// No bitband wrapper, direct signal connections
assign cm_haddr[31:0] = cm0_haddr[31:0];
assign cm_htrans[1:0] = cm0_htrans[1:0];
assign cm_hsize[2:0] = cm0_hsize[2:0];
assign cm_hburst[2:0] = cm0_hburst[2:0];
assign cm_hprot[3:0] = cm0_hprot[3:0];
assign cm_hmaster = cm0_hmaster;
assign cm_hmastlock = cm0_hmastlock;
assign cm_hwrite = cm0_hwrite;
assign cm_hwdata[31:0] = cm0_hwdata[31:0];
assign cm_hready = cm0_hready;
assign cm0_hrdata[31:0]= cm_hrdata[31:0];
assign cm0_hready = cm_hreadyout;
assign cm0_hresp = cm_hresp;
end endgenerate
// -------------------------------
// DMA Controller
// -------------------------------
// DMA interface not used in this example system
wire [DMA_CHANNEL_NUM-1:0] dma230_tie0; // tie off signal.
assign dma230_tie0 = {DMA_CHANNEL_NUM{1'b0}};
// DMA done per channel
wire [DMA_CHANNEL_NUM-1:0] dma230_done_ch;
generate if (INCLUDE_DMA != 0) begin : gen_pl230_udma
// DMA controller present
pl230_udma u_pl230_udma (
// Clock and Reset
.hclk (HCLKSYS),
.hresetn (HRESETn),
// DMA Control
.dma_req (dma230_tie0),
.dma_sreq (dma230_tie0),
.dma_waitonreq (dma230_tie0),
.dma_stall (1'b0),
.dma_active (),
.dma_done (dma230_done_ch),
.dma_err (dmac_err),
// AHB-Lite Master Interface
.hready (dmac_hready),
.hresp (dmac_hresp),
.hrdata (dmac_hrdata),
.htrans (dmac_htrans),
.hwrite (dmac_hwrite),
.haddr (dmac_haddr),
.hsize (dmac_hsize),
.hburst (dmac_hburst),
.hmastlock (dmac_hmastlock),
.hprot (dmac_hprot),
.hwdata (dmac_hwdata),
// APB Slave Interface
.pclken (PCLKEN),
.psel (dmac_psel),
.pen (exp_penable),
.pwrite (exp_pwrite),
.paddr (exp_paddr[11:0]),
.pwdata (exp_pwdata[31:0]),
.prdata (dmac_prdata)
);
assign dmac_hready = dmac_hreadyout;
assign dmac_pready = 1'b1;
assign dmac_pslverr = 1'b0;
assign dmac_done = |dma230_done_ch; // OR all the DMA done together
end else begin : gen_no_pl230_udma
// DMA controller not present
assign dmac_htrans = 2'b00;
assign dmac_hwrite = 1'b0;
assign dmac_haddr = 32'h00000000;
assign dmac_hsize = 3'b000;
assign dmac_hburst = 3'b000;
assign dmac_hmastlock = 1'b0;
assign dmac_hprot = 4'b0000;
assign dmac_hwdata = 32'h00000000;
assign dmac_done = 1'b0;
assign dmac_err = 1'b0;
assign dmac_pready = 1'b1;
assign dmac_pslverr = 1'b0;
assign dmac_prdata = 32'h00000000;
assign dma230_done_ch = {DMA_CHANNEL_NUM{1'b0}};
end endgenerate
cmsdk_ahb_master_mux #(
.PORT0_ENABLE (1),
.PORT1_ENABLE (INCLUDE_DMA),
.PORT2_ENABLE (1),
.DW (32)
)
u_ahb_master_mux (
.HCLK (HCLKSYS),
.HRESETn (HRESETn),
.HSELS0 (1'b1),
.HADDRS0 (cm_haddr[31:0]),
.HTRANSS0 (cm_htrans[1:0]),
.HSIZES0 (cm_hsize[2:0]),
.HWRITES0 (cm_hwrite),
.HREADYS0 (cm_hready),
.HPROTS0 (cm_hprot[3:0]),
.HBURSTS0 (cm_hburst[2:0]),
.HMASTLOCKS0 (cm_hmastlock),
.HWDATAS0 (cm_hwdata[31:0]),
.HREADYOUTS0 (cm_hreadyout),
.HRESPS0 (cm_hresp),
.HRDATAS0 (cm_hrdata[31:0]),
.HSELS1 (1'b1),
.HADDRS1 (dmac_haddr[31:0]),
.HTRANSS1 (dmac_htrans[1:0]),
.HSIZES1 (dmac_hsize[2:0]),
.HWRITES1 (dmac_hwrite),
.HREADYS1 (dmac_hready),
.HPROTS1 (dmac_hprot[3:0]),
.HBURSTS1 (dmac_hburst[2:0]),
.HMASTLOCKS1 (dmac_hmastlock),
.HWDATAS1 (dmac_hwdata[31:0]),
.HREADYOUTS1 (dmac_hreadyout),
.HRESPS1 (dmac_hresp),
.HRDATAS1 (dmac_hrdata[31:0]),
.HSELS2 (1'b1),
.HADDRS2 (ahbx_haddr[31:0]),
.HTRANSS2 (ahbx_htrans[1:0]),
.HSIZES2 (ahbx_hsize[2:0]),
.HWRITES2 (ahbx_hwrite),
.HREADYS2 (ahbx_hready),
.HPROTS2 (ahbx_hprot[3:0]),
.HBURSTS2 (ahbx_hburst[2:0]),
.HMASTLOCKS2 (ahbx_hmastlock),
.HWDATAS2 (ahbx_hwdata[31:0]),
.HREADYOUTS2 (ahbx_hready),
.HRESPS2 (ahbx_hresp),
.HRDATAS2 (ahbx_hrdata[31:0]),
// Output master port
.HSELM (sys_hselm), // Note: sys_hselm is not required for this particular example system.
// It is connected to the AHB Lite protocol checker only.
.HADDRM (sys_haddr[31:0]),
.HTRANSM (sys_htrans[1:0]),
.HSIZEM (sys_hsize[2:0]),
.HWRITEM (sys_hwrite),
.HREADYM (sys_hready),
.HPROTM (sys_hprot[3:0]),
.HBURSTM (sys_hburst[2:0]),
.HMASTLOCKM (sys_hmastlock),
.HWDATAM (sys_hwdata[31:0]),
.HMASTERM (sys_hmaster_i[1:0]),
.HREADYOUTM (sys_hreadyout),
.HRESPM (sys_hresp),
.HRDATAM (sys_hrdata[31:0])
);
assign sys_hmaster = (sys_hmaster_i==2'b01); // 2'b00 (core) or 2'b10 (dma)
// This signal is currently not used, but if the customer need to extend the subsystem, this signal may
// be needed
// AHB address decode
cmsdk_mcu_addr_decode #(
.BASEADDR_GPIO0 (BASEADDR_GPIO0),
.BASEADDR_GPIO1 (BASEADDR_GPIO1),
.BOOT_LOADER_PRESENT (BOOT_LOADER_PRESENT),
.BASEADDR_SYSROMTABLE (BASEADDR_SYSROMTABLE)
)
u_addr_decode (
// System Address
.haddr (sys_haddr),
.remap_ctrl (remap_ctrl),
.boot_hsel (boot_hsel),
.flash_hsel (flash_hsel),
.sram_hsel (sram_hsel),
.apbsys_hsel (apbsys_hsel),
.gpio0_hsel (gpio0_hsel),
.gpio1_hsel (gpio1_hsel),
.sysctrl_hsel (sysctrl_hsel),
.sysrom_hsel (sysrom_hsel),
.defslv_hsel (defslv_hsel),
.hselmtb (HSELMTB),
.hselram (HSELRAM),
.hselsfr (HSELSFR)
);
// AHB slave multiplexer
cmsdk_ahb_slave_mux #(
.PORT0_ENABLE (1),
.PORT1_ENABLE (1),
.PORT2_ENABLE (BOOT_LOADER_PRESENT),
.PORT3_ENABLE (1),
.PORT4_ENABLE (1),
.PORT5_ENABLE (1),
.PORT6_ENABLE (1),
.PORT7_ENABLE (1),
.PORT8_ENABLE (1),
.PORT9_ENABLE (0),
.DW (32)
)
u_ahb_slave_mux_sys_bus (
.HCLK (HCLKSYS),
.HRESETn (HRESETn),
.HREADY (sys_hready),
.HSEL0 (flash_hsel), // Input Port 0
.HREADYOUT0 (flash_hreadyout),
.HRESP0 (flash_hresp),
.HRDATA0 (flash_hrdata),
.HSEL1 (sram_hsel), // Input Port 1
.HREADYOUT1 (sram_hreadyout),
.HRESP1 (sram_hresp),
.HRDATA1 (sram_hrdata),
.HSEL2 (boot_hsel), // Input Port 2
.HREADYOUT2 (boot_hreadyout),
.HRESP2 (boot_hresp),
.HRDATA2 (boot_hrdata),
.HSEL3 (defslv_hsel), // Input Port 3
.HREADYOUT3 (defslv_hreadyout),
.HRESP3 (defslv_hresp),
.HRDATA3 (defslv_hrdata),
.HSEL4 (apbsys_hsel), // Input Port 4
.HREADYOUT4 (apbsys_hreadyout),
.HRESP4 (apbsys_hresp),
.HRDATA4 (apbsys_hrdata),
.HSEL5 (gpio0_hsel), // Input Port 5
.HREADYOUT5 (gpio0_hreadyout),
.HRESP5 (gpio0_hresp),
.HRDATA5 (gpio0_hrdata),
.HSEL6 (gpio1_hsel), // Input Port 6
.HREADYOUT6 (gpio1_hreadyout),
.HRESP6 (gpio1_hresp),
.HRDATA6 (gpio1_hrdata),
.HSEL7 (sysctrl_hsel), // Input Port 7
.HREADYOUT7 (sysctrl_hreadyout),
.HRESP7 (sysctrl_hresp),
.HRDATA7 (sysctrl_hrdata),
.HSEL8 (sysrom_hsel), // Input Port 8
.HREADYOUT8 (sysrom_hreadyout),
.HRESP8 (sysrom_hresp),
.HRDATA8 (sysrom_hrdata),
.HSEL9 (HSELMTB), // Input Port 9
.HREADYOUT9 (HREADYOUTMTB),
.HRESP9 (HRESPMTB),
.HRDATA9 (HRDATAMTB),
.HREADYOUT (sys_hreadyout), // Outputs
.HRESP (sys_hresp),
.HRDATA (sys_hrdata)
);
// Default slave
cmsdk_ahb_default_slave u_ahb_default_slave_1 (
.HCLK (HCLKSYS),
.HRESETn (HRESETn),
.HSEL (defslv_hsel),
.HTRANS (sys_htrans),
.HREADY (sys_hready),
.HREADYOUT (defslv_hreadyout),
.HRESP (defslv_hresp)
);
assign defslv_hrdata = 32'h00000000; // Default slave do not have read data
// -------------------------------
// System ROM Table
// -------------------------------
cmsdk_ahb_cs_rom_table
#(//.JEPID (),
//.JEPCONTINUATION (),
//.PARTNUMBER (),
//.REVISION (),
.BASE (BASEADDR_SYSROMTABLE),
// Entry 0 = Cortex-M0+ Processor
.ENTRY0BASEADDR (32'hE00FF000),
.ENTRY0PRESENT (1'b1),
// Entry 1 = CoreSight MTB-M0+
.ENTRY1BASEADDR (32'hF0200000),
.ENTRY1PRESENT (0))
u_system_rom_table
(//Outputs
.HRDATA (sysrom_hrdata[31:0]),
.HREADYOUT (sysrom_hreadyout),
.HRESP (sysrom_hresp),
//Inputs
.HCLK (HCLKSYS),
.HSEL (sysrom_hsel),
.HADDR (sys_haddr[31:0]),
.HBURST (sys_hburst[2:0]),
.HMASTLOCK (sys_hmastlock),
.HPROT (sys_hprot[3:0]),
.HSIZE (sys_hsize[2:0]),
.HTRANS (sys_htrans[1:0]),
.HWDATA (sys_hwdata[31:0]),
.HWRITE (sys_hwrite),
.HREADY (sys_hready),
.ECOREVNUM (4'h0));
// -------------------------------
// Peripherals
// -------------------------------
cmsdk_mcu_sysctrl #(.BE (BE))
u_cmsdk_mcu_sysctrl
(
// AHB Inputs
.HCLK (HCLKSYS),
.HRESETn (HRESETn),
.FCLK (FCLK),
.PORESETn (PORESETn),
.HSEL (sysctrl_hsel),
.HREADY (sys_hready),
.HTRANS (sys_htrans),
.HSIZE (sys_hsize),
.HWRITE (sys_hwrite),
.HADDR (sys_haddr[11:0]),
.HWDATA (sys_hwdata),
// AHB Outputs
.HREADYOUT (sysctrl_hreadyout),
.HRESP (sysctrl_hresp),
.HRDATA (sysctrl_hrdata),
// Reset information
.SYSRESETREQ (SYSRESETREQ),
.WDOGRESETREQ (WDOGRESETREQ),
.LOCKUP (LOCKUP),
// Engineering-change-order revision bits
.ECOREVNUM (4'h0),
// System control signals
.REMAP (remap_ctrl),
.PMUENABLE (PMUENABLE),
.LOCKUPRESET (LOCKUPRESET)
);
// GPIO is driven from the AHB
cmsdk_ahb_gpio #(
.ALTERNATE_FUNC_MASK (16'h0000), // No pin muxing for Port #0
.ALTERNATE_FUNC_DEFAULT (16'h0000), // All pins default to GPIO
.BE (BE)
)
u_ahb_gpio_0 (
// AHB Inputs
.HCLK (HCLKSYS),
.HRESETn (HRESETn),
.FCLK (FCLK),
.HSEL (gpio0_hsel),
.HREADY (sys_hready),
.HTRANS (sys_htrans),
.HSIZE (sys_hsize),
.HWRITE (sys_hwrite),
.HADDR (sys_haddr[11:0]),
.HWDATA (sys_hwdata),
// AHB Outputs
.HREADYOUT (gpio0_hreadyout),
.HRESP (gpio0_hresp),
.HRDATA (gpio0_hrdata),
.ECOREVNUM (4'h0),// Engineering-change-order revision bits
.PORTIN (p0_in), // GPIO Interface inputs
.PORTOUT (p0_out), // GPIO Interface outputs
.PORTEN (p0_outen),
.PORTFUNC (p0_altfunc), // Alternate function control
.GPIOINT (gpio0_intr[15:0]), // Interrupt outputs
.COMBINT (gpio0_combintr)
);
cmsdk_ahb_gpio #(
.ALTERNATE_FUNC_MASK (16'h002A), // pin muxing for Port #1
.ALTERNATE_FUNC_DEFAULT (16'h0000), // All pins default to GPIO
.BE (BE)
)
u_ahb_gpio_1 (
// AHB Inputs
.HCLK (HCLKSYS),
.HRESETn (HRESETn),
.FCLK (FCLK),
.HSEL (gpio1_hsel),
.HREADY (sys_hready),
.HTRANS (sys_htrans),
.HSIZE (sys_hsize),
This page: |
Created: | Wed Nov 16 11:46:43 2022 |
|
From: |
../verilog/cmsdk_mcu_system.v |