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Commit ccc7b74b authored by Daniel Newbrook's avatar Daniel Newbrook
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Fixed ID width for SRAMS

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./logical/*
\ No newline at end of file
logical/
verif/__pycache__
verif/sim_build
verif/*.ini
\ No newline at end of file
verif/makefile.flist
+ 71
− 71
View file @ ccc7b74b
......@@ -10,82 +10,82 @@ VERILOG_SOURCES += ../logical/IntMemAxi_1/design/IntMemAxi/verilog/rtl_source/In
VERILOG_SOURCES += ../logical/IntMemAxi_1/design/IntMemAxi/verilog/rtl_source/IntMemUnpackAddr.v
VERILOG_SOURCES += ../logical/IntMemAxi_1/design/IntMemAxi/verilog/rtl_source/MemModelBhav.v
VERILOG_SOURCES += ../logical/dma350/logical/logical/shared/verilog/ada_gen_regmap_sldma350_pkg.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/shared/verilog/ada_apb_regmap_conv_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/shared/verilog/ada_reg_field_ro_ro_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/shared/verilog/ada_reg_field_rw_ro_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/shared/verilog/ada_reg_field_rw_w1c_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/shared/verilog/ada_reg_field_rw_w1s_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/shared/verilog/ada_reg_field_rw_rw_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/shared/verilog/ada_gen_coreif_dmach_sldma350_pkg.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/shared/verilog/ada_gen_addrmap_dmach_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/shared/verilog/ada_interface_sldma350_pkg.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/shared/verilog/ada_flop_en/verilog/ada_flop_en.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/shared/verilog/ada_or_tree/verilog/ada_or_tree.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/shared/verilog/ada_gen_regif_dmainfo_sldma350_pkg.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/models/cells/generic/ada_arm_flop.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/models/cells/generic/ada_arm_sync.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/models/cells/generic/ada_arm_mux2.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/models/cells/generic/ada_arm_or.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/models/cells/generic/ada_arm_idbit_v1.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/shared/verilog/ada_ecorevnum.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_top_sldma350/verilog/ada_top_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/shared/verilog/ada_gen_regmap_sldma350_pkg.sv
VERILOG_SOURCES += ../logical/dma350/logical/shared/verilog/ada_apb_regmap_conv_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/shared/verilog/ada_reg_field_ro_ro_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/shared/verilog/ada_reg_field_rw_ro_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/shared/verilog/ada_reg_field_rw_w1c_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/shared/verilog/ada_reg_field_rw_w1s_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/shared/verilog/ada_reg_field_rw_rw_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/shared/verilog/ada_gen_coreif_dmach_sldma350_pkg.sv
VERILOG_SOURCES += ../logical/dma350/logical/shared/verilog/ada_gen_addrmap_dmach_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/shared/verilog/ada_interface_sldma350_pkg.sv
VERILOG_SOURCES += ../logical/dma350/logical/shared/verilog/ada_flop_en/verilog/ada_flop_en.sv
VERILOG_SOURCES += ../logical/dma350/logical/shared/verilog/ada_or_tree/verilog/ada_or_tree.sv
VERILOG_SOURCES += ../logical/dma350/logical/shared/verilog/ada_gen_regif_dmainfo_sldma350_pkg.sv
VERILOG_SOURCES += ../logical/dma350/logical/models/cells/generic/ada_arm_flop.sv
VERILOG_SOURCES += ../logical/dma350/logical/models/cells/generic/ada_arm_sync.sv
VERILOG_SOURCES += ../logical/dma350/logical/models/cells/generic/ada_arm_mux2.sv
VERILOG_SOURCES += ../logical/dma350/logical/models/cells/generic/ada_arm_or.sv
VERILOG_SOURCES += ../logical/dma350/logical/models/cells/generic/ada_arm_idbit_v1.sv
VERILOG_SOURCES += ../logical/dma350/logical/shared/verilog/ada_ecorevnum.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_top_sldma350/verilog/ada_top_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_biu_sldma350/verilog/ada_biu_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_biu_sldma350/verilog/ada_biu_read_switch_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_biu_sldma350/verilog/ada_biu_read_switch_wrapper_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_biu_sldma350/verilog/ada_biu_write_switch_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_biu_sldma350/verilog/ada_biu_write_switch_wrapper_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_biu_sldma350/verilog/ada_biu_arbiter_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_biu_sldma350/verilog/ada_biu_qv_cmp_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_biu_sldma350/verilog/ada_biu_grant_queue_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_biu_sldma350/verilog/ada_biu_full_f2s_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_biu_sldma350/verilog/ada_biu_reverse_s2f_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_read_switch_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_read_switch_wrapper_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_write_switch_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_write_switch_wrapper_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_arbiter_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_qv_cmp_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_grant_queue_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_full_f2s_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_reverse_s2f_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_channel_0_sldma350/verilog/ada_gen_regif_dmach_0_sldma350_pkg.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_channel_0_sldma350/verilog/ada_gen_regif_dmach_0_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_channel_0_sldma350/verilog/ada_gen_regmap_dmach_0_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_channel_0_sldma350/verilog/ada_gen_fields_coreif_dmach_0_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_channel_0_sldma350/verilog/ada_gen_coreif_res_dmach_0_sldma350_pkg.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_channel_0_sldma350/verilog/ada_channel_0_sldma350_pkg.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_channel_0_sldma350/verilog/ada_channel_0_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_channel_0_sldma350/verilog/ada_channel_0_ctrl_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_channel_0_sldma350/verilog/ada_channel_0_1d_wr_ctrl_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_channel_0_sldma350/verilog/ada_channel_0_1d_rd_ctrl_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_channel_0_sldma350/verilog/ada_channel_0_fifo_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_channel_0_sldma350/verilog/ada_channel_0_cmdlink_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_channel_0_sldma350/verilog/ada_channel_0_axi_rd_if_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_channel_0_sldma350/verilog/ada_channel_0_axi_wr_if_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_channel_0_sldma350/verilog/ada_channel_0_axi_stop_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_channel_0_sldma350/verilog/ada_channel_0_reg_bank_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_channel_0_sldma350/verilog/ada_channel_0_stream_wrapper_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_channel_0_sldma350/verilog/ada_channel_0_stream_slave_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_channel_0_sldma350/verilog/ada_channel_0_stream_master_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_channel_0_sldma350/verilog/ada_channel_0_stream_bypass_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_channel_0_sldma350/verilog/ada_channel_0_trig_in_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_channel_0_sldma350/verilog/ada_channel_0_trig_out_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_gen_regif_dmach_0_sldma350_pkg.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_gen_regif_dmach_0_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_gen_regmap_dmach_0_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_gen_fields_coreif_dmach_0_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_gen_coreif_res_dmach_0_sldma350_pkg.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_sldma350_pkg.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_ctrl_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_1d_wr_ctrl_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_1d_rd_ctrl_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_fifo_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_cmdlink_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_axi_rd_if_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_axi_wr_if_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_axi_stop_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_reg_bank_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_stream_wrapper_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_stream_slave_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_stream_master_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_stream_bypass_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_trig_in_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_trig_out_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_ctrl_sldma350/verilog/ada_gen_regif_dmainfo_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_ctrl_sldma350/verilog/ada_gen_regmap_dmainfo_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_ctrl_sldma350/verilog/ada_gen_fields_coreif_dmainfo_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_ctrl_sldma350/verilog/ada_gen_addrmap_dmainfo_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_ctrl_sldma350/verilog/ada_gen_coreif_dmansecctrl_sldma350_pkg.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_ctrl_sldma350/verilog/ada_gen_regif_dmansecctrl_sldma350_pkg.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_ctrl_sldma350/verilog/ada_gen_regif_dmansecctrl_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_ctrl_sldma350/verilog/ada_gen_regmap_dmansecctrl_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_ctrl_sldma350/verilog/ada_gen_fields_coreif_dmansecctrl_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_ctrl_sldma350/verilog/ada_gen_addrmap_dmansecctrl_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_ctrl_sldma350/verilog/ada_ctrl_apb_slave_mux_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_ctrl_sldma350/verilog/ada_ctrl_dmainfo_reg_bank_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_ctrl_sldma350/verilog/ada_ctrl_dmansecctrl_reg_bank_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_ctrl_sldma350/verilog/ada_ctrl_trigmask_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_ctrl_sldma350/verilog/ada_ctrl_trigin_used_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_ctrl_sldma350/verilog/ada_ctrl_trigout_used_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_ctrl_sldma350/verilog/ada_ctrl_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_regif_dmainfo_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_regmap_dmainfo_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_fields_coreif_dmainfo_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_addrmap_dmainfo_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_coreif_dmansecctrl_sldma350_pkg.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_regif_dmansecctrl_sldma350_pkg.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_regif_dmansecctrl_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_regmap_dmansecctrl_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_fields_coreif_dmansecctrl_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_addrmap_dmansecctrl_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_ctrl_apb_slave_mux_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_ctrl_dmainfo_reg_bank_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_ctrl_dmansecctrl_reg_bank_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_ctrl_trigmask_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_ctrl_trigin_used_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_ctrl_trigout_used_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_ctrl_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_qctrl_sldma350/verilog/ada_qctrl_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_qctrl_sldma350/verilog/ada_qctrl_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_trigmtx_sldma350/verilog/ada_trigmtx_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/ada_trigmtx_sldma350/verilog/ada_trigmtx_sldma350.sv
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/nic400/verilog/nic400_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/amib_AXI_Master_0/verilog/nic400_amib_AXI_Master_0_1.v
......
verif/nic400_top.v
+ 4
− 1
View file @ ccc7b74b
......@@ -62,9 +62,12 @@ module nic400_top #
inout wire APB_PSLVERR,
inout wire [3:0] APB_PSTRB
);
parameter MEM_ID_WIDTH=6;
defparam u_sram_0.ID_WIDTH=MEM_ID_WIDTH;
defparam u_sram_1.ID_WIDTH=MEM_ID_WIDTH;
// IntMem Axi signals - AXI_MASTER_0
parameter MEM_ID_WIDTH=6;
wire [MEM_ID_WIDTH-1:0] AWID_AXI_Master_0;
wire [SYS_ADDR_WIDTH-1:0] AWADDR_AXI_Master_0;
wire [3:0] AWLEN_AXI_Master_0;
......
verif/results.xml
+ 4
− 2
View file @ ccc7b74b
<testsuites name="results">
<testsuite name="all" package="all">
<property name="random_seed" value="1692283650" />
<testcase classname="test_axi" file="/home/dwn1c21/SoC-Labs/NIC_cocoTB/verif/test_axi.py" lineno="117" name="run_dma_1D_test" ratio_time="4853.842475586658" sim_time_ns="8926.001" time="1.8389556407928467" />
<property name="random_seed" value="1693481213" />
<testcase classname="test_axi" file="/home/dwn1c21/SoC-Labs/cocotb_axi/verif/test_axi.py" lineno="96" name="run_test_write_read" ratio_time="6147.414214780654" sim_time_ns="61642.001" time="10.027305603027344" />
<testcase classname="test_axi" file="/home/dwn1c21/SoC-Labs/cocotb_axi/verif/test_axi.py" lineno="117" name="run_dma_1D_test" ratio_time="4947.855424767505" sim_time_ns="8928.000999999997" time="1.8044183254241943" />
<testcase classname="test_axi" file="/home/dwn1c21/SoC-Labs/cocotb_axi/verif/test_axi.py" lineno="181" name="run_dma_1D_axis_test" ratio_time="4775.362713321283" sim_time_ns="8932.001000000004" time="1.870434045791626" />
</testsuite>
</testsuites>
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