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makefile.flist 21.45 KiB 


#VERILOG_SOURCES += ${XVC_ROOT}/axim/verilog/Axi4MasterXvc.v
#VERILOG_SOURCES += ${XVC_ROOT}/axim/verilog/AxiMasterXvc.v
#VERILOG_SOURCES += ${XVC_ROOT}/axis/verilog/Axi3pSlaveXvc.v

VERILOG_SOURCES += ../logical/IntMemAxi_1/design/IntMemAxi/verilog/rtl_source/IntMemAddrGen.v
VERILOG_SOURCES += ../logical/IntMemAxi_1/design/IntMemAxi/verilog/rtl_source/IntMemAxi.v
VERILOG_SOURCES += ../logical/IntMemAxi_1/design/IntMemAxi/verilog/rtl_source/IntMemBhavAxi.v
VERILOG_SOURCES += ../logical/IntMemAxi_1/design/IntMemAxi/verilog/rtl_source/IntMemUnpackAddr.v
VERILOG_SOURCES += ../logical/IntMemAxi_1/design/IntMemAxi/verilog/rtl_source/MemModelBhav.v

VERILOG_SOURCES += ../logical/dma350/logical/logical/shared/verilog/ada_gen_regmap_sldma350_pkg.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/shared/verilog/ada_apb_regmap_conv_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/shared/verilog/ada_reg_field_ro_ro_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/shared/verilog/ada_reg_field_rw_ro_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/shared/verilog/ada_reg_field_rw_w1c_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/shared/verilog/ada_reg_field_rw_w1s_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/shared/verilog/ada_reg_field_rw_rw_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/shared/verilog/ada_gen_coreif_dmach_sldma350_pkg.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/shared/verilog/ada_gen_addrmap_dmach_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/shared/verilog/ada_interface_sldma350_pkg.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/shared/verilog/ada_flop_en/verilog/ada_flop_en.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/shared/verilog/ada_or_tree/verilog/ada_or_tree.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/shared/verilog/ada_gen_regif_dmainfo_sldma350_pkg.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/models/cells/generic/ada_arm_flop.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/models/cells/generic/ada_arm_sync.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/models/cells/generic/ada_arm_mux2.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/models/cells/generic/ada_arm_or.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/models/cells/generic/ada_arm_idbit_v1.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/shared/verilog/ada_ecorevnum.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_top_sldma350/verilog/ada_top_sldma350.sv

VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_biu_sldma350/verilog/ada_biu_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_biu_sldma350/verilog/ada_biu_read_switch_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_biu_sldma350/verilog/ada_biu_read_switch_wrapper_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_biu_sldma350/verilog/ada_biu_write_switch_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_biu_sldma350/verilog/ada_biu_write_switch_wrapper_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_biu_sldma350/verilog/ada_biu_arbiter_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_biu_sldma350/verilog/ada_biu_qv_cmp_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_biu_sldma350/verilog/ada_biu_grant_queue_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_biu_sldma350/verilog/ada_biu_full_f2s_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_biu_sldma350/verilog/ada_biu_reverse_s2f_sldma350.sv

VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_channel_0_sldma350/verilog/ada_gen_regif_dmach_0_sldma350_pkg.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_channel_0_sldma350/verilog/ada_gen_regif_dmach_0_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_channel_0_sldma350/verilog/ada_gen_regmap_dmach_0_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_channel_0_sldma350/verilog/ada_gen_fields_coreif_dmach_0_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_channel_0_sldma350/verilog/ada_gen_coreif_res_dmach_0_sldma350_pkg.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_channel_0_sldma350/verilog/ada_channel_0_sldma350_pkg.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_channel_0_sldma350/verilog/ada_channel_0_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_channel_0_sldma350/verilog/ada_channel_0_ctrl_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_channel_0_sldma350/verilog/ada_channel_0_1d_wr_ctrl_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_channel_0_sldma350/verilog/ada_channel_0_1d_rd_ctrl_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_channel_0_sldma350/verilog/ada_channel_0_fifo_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_channel_0_sldma350/verilog/ada_channel_0_cmdlink_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_channel_0_sldma350/verilog/ada_channel_0_axi_rd_if_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_channel_0_sldma350/verilog/ada_channel_0_axi_wr_if_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_channel_0_sldma350/verilog/ada_channel_0_axi_stop_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_channel_0_sldma350/verilog/ada_channel_0_reg_bank_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_channel_0_sldma350/verilog/ada_channel_0_stream_wrapper_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_channel_0_sldma350/verilog/ada_channel_0_stream_slave_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_channel_0_sldma350/verilog/ada_channel_0_stream_master_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_channel_0_sldma350/verilog/ada_channel_0_stream_bypass_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_channel_0_sldma350/verilog/ada_channel_0_trig_in_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_channel_0_sldma350/verilog/ada_channel_0_trig_out_sldma350.sv

VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_ctrl_sldma350/verilog/ada_gen_regif_dmainfo_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_ctrl_sldma350/verilog/ada_gen_regmap_dmainfo_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_ctrl_sldma350/verilog/ada_gen_fields_coreif_dmainfo_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_ctrl_sldma350/verilog/ada_gen_addrmap_dmainfo_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_ctrl_sldma350/verilog/ada_gen_coreif_dmansecctrl_sldma350_pkg.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_ctrl_sldma350/verilog/ada_gen_regif_dmansecctrl_sldma350_pkg.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_ctrl_sldma350/verilog/ada_gen_regif_dmansecctrl_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_ctrl_sldma350/verilog/ada_gen_regmap_dmansecctrl_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_ctrl_sldma350/verilog/ada_gen_fields_coreif_dmansecctrl_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_ctrl_sldma350/verilog/ada_gen_addrmap_dmansecctrl_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_ctrl_sldma350/verilog/ada_ctrl_apb_slave_mux_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_ctrl_sldma350/verilog/ada_ctrl_dmainfo_reg_bank_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_ctrl_sldma350/verilog/ada_ctrl_dmansecctrl_reg_bank_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_ctrl_sldma350/verilog/ada_ctrl_trigmask_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_ctrl_sldma350/verilog/ada_ctrl_trigin_used_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_ctrl_sldma350/verilog/ada_ctrl_trigout_used_sldma350.sv
VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_ctrl_sldma350/verilog/ada_ctrl_sldma350.sv

VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_qctrl_sldma350/verilog/ada_qctrl_sldma350.sv

VERILOG_SOURCES += ../logical/dma350/logical/logical/ada_trigmtx_sldma350/verilog/ada_trigmtx_sldma350.sv

VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/nic400/verilog/nic400_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/amib_AXI_Master_0/verilog/nic400_amib_AXI_Master_0_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/amib_AXI_Master_0/verilog/nic400_amib_AXI_Master_0_chan_slice_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/amib_AXI_Master_1/verilog/nic400_amib_AXI_Master_1_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/amib_AXI_Master_1/verilog/nic400_amib_AXI_Master_1_chan_slice_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/asib_AXI4_Slave_0/verilog/nic400_asib_AXI4_Slave_0_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/asib_AXI4_Slave_0/verilog/nic400_asib_AXI4_Slave_0_chan_slice_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/asib_AXI4_Slave_0/verilog/nic400_asib_AXI4_Slave_0_decode_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/asib_AXI4_Slave_0/verilog/nic400_asib_AXI4_Slave_0_maskcntl_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/asib_AXI4_Slave_0/verilog/nic400_asib_AXI4_Slave_0_rd_ss_cdas_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/asib_AXI4_Slave_0/verilog/nic400_asib_AXI4_Slave_0_wr_ss_cdas_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/asib_AXI4_Slave_1/verilog/nic400_asib_AXI4_Slave_1_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/asib_AXI4_Slave_1/verilog/nic400_asib_AXI4_Slave_1_chan_slice_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/asib_AXI4_Slave_1/verilog/nic400_asib_AXI4_Slave_1_decode_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/asib_AXI4_Slave_1/verilog/nic400_asib_AXI4_Slave_1_maskcntl_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/asib_AXI4_Slave_1/verilog/nic400_asib_AXI4_Slave_1_rd_ss_cdas_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/asib_AXI4_Slave_1/verilog/nic400_asib_AXI4_Slave_1_wr_ss_cdas_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/asib_AXI4_Slave_2/verilog/nic400_asib_AXI4_Slave_2_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/asib_AXI4_Slave_2/verilog/nic400_asib_AXI4_Slave_2_chan_slice_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/asib_AXI4_Slave_2/verilog/nic400_asib_AXI4_Slave_2_decode_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/asib_AXI4_Slave_2/verilog/nic400_asib_AXI4_Slave_2_maskcntl_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/asib_AXI4_Slave_2/verilog/nic400_asib_AXI4_Slave_2_rd_ss_cdas_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/asib_AXI4_Slave_2/verilog/nic400_asib_AXI4_Slave_2_wr_ss_cdas_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/busmatrix_bm0/verilog/nic400_bm0_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/busmatrix_bm0/verilog/nic400_bm0_add_arb_ml0_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/busmatrix_bm0/verilog/nic400_bm0_add_arb_ml1_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml0_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml1_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/busmatrix_bm0/verilog/nic400_bm0_lrg_arb_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml0_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml1_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/busmatrix_bm0/verilog/nic400_bm0_ml_blayer_0_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/busmatrix_bm0/verilog/nic400_bm0_ml_blayer_1_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/busmatrix_bm0/verilog/nic400_bm0_ml_blayer_2_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/busmatrix_bm0/verilog/nic400_bm0_ml_build_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/busmatrix_bm0/verilog/nic400_bm0_ml_map_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_0_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_1_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/busmatrix_bm0/verilog/nic400_bm0_qv_cmp_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/busmatrix_bm0/verilog/nic400_bm0_rd_st_tt_s0_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/busmatrix_bm0/verilog/nic400_bm0_rd_st_tt_s1_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/busmatrix_bm0/verilog/nic400_bm0_rd_st_tt_s2_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml0_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml1_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml0_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml1_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/busmatrix_bm0/verilog/nic400_bm0_wr_st_tt_s0_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/busmatrix_bm0/verilog/nic400_bm0_wr_st_tt_s1_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/busmatrix_bm0/verilog/nic400_bm0_wr_st_tt_s2_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/busmatrix_bm1/verilog/nic400_bm1_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/busmatrix_bm1/verilog/nic400_bm1_add_sel_ml0_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/busmatrix_bm1/verilog/nic400_bm1_add_sel_ml1_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/busmatrix_bm1/verilog/nic400_bm1_maskcntl_ml0_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/busmatrix_bm1/verilog/nic400_bm1_maskcntl_ml1_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/busmatrix_bm1/verilog/nic400_bm1_ml_blayer_0_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/busmatrix_bm1/verilog/nic400_bm1_ml_build_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/busmatrix_bm1/verilog/nic400_bm1_ml_map_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/busmatrix_bm1/verilog/nic400_bm1_ml_mlayer_0_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/busmatrix_bm1/verilog/nic400_bm1_ml_mlayer_1_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/busmatrix_bm1/verilog/nic400_bm1_rd_spi_tt_s0_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/busmatrix_bm1/verilog/nic400_bm1_rd_wr_arb_0_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/busmatrix_bm1/verilog/nic400_bm1_rd_wr_arb_1_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/busmatrix_bm1/verilog/nic400_bm1_ret_sel_ml0_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/busmatrix_bm1/verilog/nic400_bm1_ret_sel_ml1_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/busmatrix_bm1/verilog/nic400_bm1_wr_sel_ml0_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/busmatrix_bm1/verilog/nic400_bm1_wr_sel_ml1_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/busmatrix_bm1/verilog/nic400_bm1_wr_spi_tt_s0_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/cdc_blocks/verilog/nic400_cdc_bypass_sync_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/cdc_blocks/verilog/nic400_cdc_capt_nosync_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/cdc_blocks/verilog/nic400_cdc_capt_sync_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/cdc_blocks/verilog/nic400_cdc_comb_and2_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/cdc_blocks/verilog/nic400_cdc_comb_mux2_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/cdc_blocks/verilog/nic400_cdc_comb_or2_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/cdc_blocks/verilog/nic400_cdc_comb_or3_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/cdc_blocks/verilog/nic400_cdc_corrupt_gry_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/cdc_blocks/verilog/nic400_cdc_launch_gry_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/cdc_blocks/verilog/nic400_cdc_random_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/default_slave_ds_3/verilog/nic400_default_slave_ds_3_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/ib_ib2/verilog/nic400_ib_ib2_burstbreaker_rd_addr_fmt_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/ib_ib2/verilog/nic400_ib_ib2_burstbreaker_resp_cam_slice_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/ib_ib2/verilog/nic400_ib_ib2_burstbreaker_wr_addr_fmt_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/ib_ib2/verilog/nic400_ib_ib2_burstbreaker_wr_cntrl_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/ib_ib2/verilog/nic400_ib_ib2_burstbreaker_wr_merge_buffer_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/ib_ib2/verilog/nic400_ib_ib2_burstbreaker_wr_mux_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/ib_ib2/verilog/nic400_ib_ib2_burstbreaker_wr_resp_block_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/ib_ib2/verilog/nic400_ib_ib2_chan_slice_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/ib_ib2/verilog/nic400_ib_ib2_downsize_rd_cam_slice_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/ib_ib2/verilog/nic400_ib_ib2_downsize_rd_chan_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/ib_ib2/verilog/nic400_ib_ib2_downsize_rd_cntrl_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/ib_ib2/verilog/nic400_ib_ib2_maskcntl_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/ib_ib2/verilog/nic400_ib_ib2_master_domain_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/ib_ib2/verilog/nic400_ib_ib2_slave_domain_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/reg_slice/verilog/nic400_ax4_reg_slice_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/reg_slice/verilog/nic400_ax_reg_slice_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/reg_slice/verilog/nic400_buf_reg_slice_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/reg_slice/verilog/nic400_ful_regd_slice_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/reg_slice/verilog/nic400_fwd_regd_slice_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/reg_slice/verilog/nic400_rd_reg_slice_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/reg_slice/verilog/nic400_reg_slice_axi_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/reg_slice/verilog/nic400_rev_regd_slice_1.v
VERILOG_SOURCES += ../logical/nic400_1/logical/nic400_1/reg_slice/verilog/nic400_wr_reg_slice_1.v

# Define the include directory paths for the Auxiliary IP

#-y ./../../../verilog/Axi
#-y ./../../../verilog/AxiPC
#-y ../logical/nic400_1/logical/nic400_1/amib_AXI_Master_0/verilog
#-y ../logical/nic400_1/logical/nic400_1/reg_slice/verilog
#-y ./../../../verilog/Axi4PC
#-y ../logical/nic400_1/logical/nic400_1/asib_AXI4_Slave_0/verilog
#-y ../logical/nic400_1/logical/nic400_1/asib_AXI4_Slave_1/verilog
#-y ../logical/nic400_1/logical/nic400_1/default_slave_ds_1/verilog
#-y ../logical/nic400_1/logical/nic400_1/ib_AXI_Master_0_ib/verilog
#-y ../logical/nic400_1/logical/nic400_1/shared/validation/tb_components
#-y ./../tb_spirit
#-y ../logical/nic400_1/logical/nic400_1/cdc_blocks/verilog
#-y ./../tb_components
EXTRA_ARGS += +incdir+${XVC_ROOT}/axim/verilog
EXTRA_ARGS += +incdir+${XVC_ROOT}/axis/verilog
EXTRA_ARGS += +incdir+../logical/nic400_1/logical/nic400_1/amib_AXI_Master_0/verilog
EXTRA_ARGS += +incdir+../logical/nic400_1/logical/nic400_1/amib_AXI_Master_1/verilog
EXTRA_ARGS += +incdir+../logical/nic400_1/logical/nic400_1/asib_AXI4_Slave_0/verilog
EXTRA_ARGS += +incdir+../logical/nic400_1/logical/nic400_1/asib_AXI4_Slave_1/verilog
EXTRA_ARGS += +incdir+../logical/nic400_1/logical/nic400_1/asib_AXI4_Slave_2/verilog

EXTRA_ARGS += +incdir+../logical/nic400_1/logical/nic400_1/busmatrix_bm0/verilog
EXTRA_ARGS += +incdir+../logical/nic400_1/logical/nic400_1/busmatrix_bm1/verilog
EXTRA_ARGS += +incdir+../logical/nic400_1/logical/nic400_1/cdc_blocks/verilog
EXTRA_ARGS += +incdir+../logical/nic400_1/logical/nic400_1/default_slave_ds_3/verilog
EXTRA_ARGS += +incdir+../logical/nic400_1/logical/nic400_1/ib_ib2/verilog

EXTRA_ARGS += +incdir+../logical/nic400_1/logical/nic400_1/nic400/validation/shared/tb_components/tb_components
EXTRA_ARGS += +incdir+../logical/nic400_1/logical/nic400_1/nic400/verilog
EXTRA_ARGS += +incdir+../logical/nic400_1/logical/nic400_1/reg_slice/verilog
EXTRA_ARGS += +incdir+../logical/nic400_1/logical/nic400_1/shared/validation/tb_components/Axi4Frm
EXTRA_ARGS += +incdir+../logical/nic400_1/logical/nic400_1/shared/validation/tb_components
EXTRA_ARGS += +incdir+../logical/nic400_1/logical/nic400_1/shared/validation/tb_components/AxiFrm
EXTRA_ARGS += +incdir+../logical/nic400_1/logical/nic400_1/shared/validation/tb_components/AxiFrs
EXTRA_ARGS += +incdir+../logical/nic400_1/logical/nic400_1/nic400/verilog/Axi
EXTRA_ARGS += +incdir+../logical/nic400_1/logical/nic400_1/nic400/verilog/AxiPC
EXTRA_ARGS += +incdir+../logical/nic400_1/logical/nic400_1/nic400/verilog/Axi4PC
EXTRA_ARGS += +incdir+./../tb_spirit

EXTRA_ARGS += +incdir+./../logical/IntMemAxi_1/design/IntMemAxi/verilog/rtl_source/