From bace03e4fc05645f3476bf76ae24061740f418c6 Mon Sep 17 00:00:00 2001
From: whatmough <pwhatmough@seas.harvard.edu>
Date: Sun, 12 Jan 2020 20:09:08 -0500
Subject: [PATCH] Update README.md

---
 ip/ahb/README.md | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/ip/ahb/README.md b/ip/ahb/README.md
index a730e53..5bebdb1 100644
--- a/ip/ahb/README.md
+++ b/ip/ahb/README.md
@@ -1,17 +1,17 @@
 # AHB Components
 
-## AHB Interfaces (`ahb_intf.sv`)
+## AHB Interfaces (*ahb_intf.sv*)
 
 Provides SystemVerilog interfaces for the AHB-Lite interconnect standard.  This allows rapid, agile SoC development in RTL without all of the typing and debugging.
 
-## AHB Bus (`AHB_BUS.sv`)
+## AHB Bus (*AHB_BUS.sv*)
 
 An agile AHB bus implementation in a single RTL file!  A single include file defines the memory map for the decoder.  This design has been extensively used for numerous successful chip tape outs.
 
-## AHB Master Mux (`AHB_MASTER_MUX.sv`)
+## AHB Master Mux (*AHB_MASTER_MUX.sv*)
 
 A simple module to mux up to four masters together.
 
-## AHB Memory Example (`AHB_MEM.sv`)
+## AHB Memory Example (*AHB_MEM.sv*)
 
 A simple example of a 64KB SRAM attached to an AHB slave port.
-- 
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