From 64a752c27f8f640a34f9cabf85a340b940434cb2 Mon Sep 17 00:00:00 2001
From: whatmough <pwhatmough@seas.harvard.edu>
Date: Sun, 12 Jan 2020 20:06:40 -0500
Subject: [PATCH] Update README.md

---
 ip/ahb/README.md | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/ip/ahb/README.md b/ip/ahb/README.md
index 8b13789..a730e53 100644
--- a/ip/ahb/README.md
+++ b/ip/ahb/README.md
@@ -1 +1,17 @@
+# AHB Components
 
+## AHB Interfaces (`ahb_intf.sv`)
+
+Provides SystemVerilog interfaces for the AHB-Lite interconnect standard.  This allows rapid, agile SoC development in RTL without all of the typing and debugging.
+
+## AHB Bus (`AHB_BUS.sv`)
+
+An agile AHB bus implementation in a single RTL file!  A single include file defines the memory map for the decoder.  This design has been extensively used for numerous successful chip tape outs.
+
+## AHB Master Mux (`AHB_MASTER_MUX.sv`)
+
+A simple module to mux up to four masters together.
+
+## AHB Memory Example (`AHB_MEM.sv`)
+
+A simple example of a 64KB SRAM attached to an AHB slave port.
-- 
GitLab