From 501fccbc49c32f041eedb602d3f6aebef74d7123 Mon Sep 17 00:00:00 2001
From: whatmough <pwhatmough@seas.harvard.edu>
Date: Sun, 24 May 2020 12:11:42 -0400
Subject: [PATCH] Update README.md

---
 ip/commctrl/README.md | 20 +++++++++-----------
 1 file changed, 9 insertions(+), 11 deletions(-)

diff --git a/ip/commctrl/README.md b/ip/commctrl/README.md
index 3a9458f..265ba5d 100644
--- a/ip/commctrl/README.md
+++ b/ip/commctrl/README.md
@@ -12,19 +12,17 @@ The off-chip hosting uses the standard UART protocol and therefore requires noth
 ## Description
 
 Usage:
-- Initialize SRAMs attached to AHB bus
-    - Load CM0 code memory
-    - Load input and mega memories
-- Control SM2 system controller
-    - Write/Read SRAM Control register (EMA[2:0], EMAW[1:0])
-    - Write/Read PAD Control register (ST[1:0], DS[1:0], SL)
-    - Force internal reset using frcintrst register
-    - Watchdog, system, Lockup reset enables
-- Configure Minerva NN Accelerator
-    - HREGs / FREGs
-    - read out performance counters and status
+- Issues single bus transactions
+    - Write a single 32b location
+    - Read a single 32b location
+- Use to:
+    - read/write control and statue registers
+    - Load SRAMs with binaries or data
+    - Readback SRAMs containing data
 
 
+### Block Diagram
+
 <img src="commctrl_block_diagram.png"/>
 
 
-- 
GitLab