From f81392e6e4a59e33185ade91a86c4968d207b8ff Mon Sep 17 00:00:00 2001
From: Daniel Newbrook <dwn1c21@soton.ac.uk>
Date: Fri, 4 Apr 2025 11:40:27 +0100
Subject: [PATCH] Add TSMC 16nm SRAM wrapper
---
flist/asic_lib_ip_TSMC16nm.flist | 26 ++++++++++
sram/TSMC16nm/verilog/sl_sram.v | 82 ++++++++++++++++++++++++++++++++
2 files changed, 108 insertions(+)
create mode 100644 flist/asic_lib_ip_TSMC16nm.flist
create mode 100644 sram/TSMC16nm/verilog/sl_sram.v
diff --git a/flist/asic_lib_ip_TSMC16nm.flist b/flist/asic_lib_ip_TSMC16nm.flist
new file mode 100644
index 0000000..f7638aa
--- /dev/null
+++ b/flist/asic_lib_ip_TSMC16nm.flist
@@ -0,0 +1,26 @@
+//-----------------------------------------------------------------------------
+// ASIC Library Memory Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// Daniel Newbrook (d.newbrook@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for NanoSoC Testbench
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// ============= NanoSoC Testbench search path =============
+// +incdir+$(SOCLABS_ASIC_LIB_TECH_DIR)/sram/verilog/
+
+// - Memories
+$(SOCLABS_ASIC_LIB_TECH_DIR)/sram/verilog/sl_ahb_sram.v
+$(SOCLABS_ASIC_LIB_TECH_DIR)/sram/TSMC16nm/verilog/sl_sram.v
+$(SOCLABS_ASIC_LIB_TECH_DIR)/rom/verilog/bootrom.v
+
+$(SOCLABS_ASIC_LIB_TECH_DIR)/sync/verilog/SYNCHRONIZER_EDGES.v
\ No newline at end of file
diff --git a/sram/TSMC16nm/verilog/sl_sram.v b/sram/TSMC16nm/verilog/sl_sram.v
new file mode 100644
index 0000000..62173e1
--- /dev/null
+++ b/sram/TSMC16nm/verilog/sl_sram.v
@@ -0,0 +1,82 @@
+//-----------------------------------------------------------------------------
+// SoCLabs ASIC RAM Wrapper
+// - substituted using the same name from the FPGA tech library
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.flynn@soton.ac.uk)
+//
+// Copyright 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module sl_sram #(
+// --------------------------------------------------------------------------
+// Parameter Declarations
+// --------------------------------------------------------------------------
+ parameter AW = 16
+ )
+ (
+ `ifdef POWER_PINS
+ inout wire VDD,
+ inout wire VSS,
+ `endif
+ // Inputs
+ input wire CLK,
+ input wire [AW-1:2] ADDR,
+ input wire [31:0] WDATA,
+ input wire [3:0] WREN,
+ input wire CS,
+
+ // Outputs
+ output wire [31:0] RDATA
+ );
+
+// fixed pre-compiled 16K instance supported
+localparam TIE_EMA = 3'b010;
+localparam TIE_EMAW = 2'b00;
+wire [AW-3:0] ADDR12 = ADDR;
+wire [31:0] WDATA32 = WDATA;
+wire [31:0] RDATA32;
+assign RDATA = RDATA32;
+wire CEN = !CS;
+wire GWEN = &(~WREN);
+wire [31:0] WEN32 = { {8{!WREN[3]}},{8{!WREN[2]}},{8{!WREN[1]}},{8{!WREN[0]}} };
+localparam TIE_RET1N = 1'b1;
+
+generate
+ if (AW==14) begin
+ sram_16k
+ u_sram (
+ .Q (RDATA32),
+ .CLK (CLK),
+ .CEN (CEN),
+ .WEN (WEN32),
+ .A (ADDR12),
+ .D (WDATA32),
+ .EMA (TIE_EMA),
+ .EMAW (TIE_EMAW),
+ .GWEN (GWEN),
+ .RET1N (TIE_RET1N)
+ );
+
+ end
+ else if (AW==15) begin
+ sram_32k
+ u_sram (
+ .Q (RDATA32),
+ .CLK (CLK),
+ .CEN (CEN),
+ .WEN (WEN32),
+ .A (ADDR12),
+ .D (WDATA32),
+ .EMA (TIE_EMA),
+ .EMAW (TIE_EMAW),
+ .GWEN (GWEN),
+ .RET1N (TIE_RET1N)
+ );
+ end
+endgenerate
+
+
+endmodule
--
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