From ce05d1a53ea1478b1b11be15053e3b4e02f9ddb1 Mon Sep 17 00:00:00 2001
From: Daniel Newbrook <dwn1c21@soton.ac.uk>
Date: Tue, 5 Dec 2023 14:10:19 +0000
Subject: [PATCH] Add 16K and 8K options for SRAM
---
sram/verilog/sl_sram.v | 61 +++++++++++++++++++++++++++++-------------
1 file changed, 43 insertions(+), 18 deletions(-)
diff --git a/sram/verilog/sl_sram.v b/sram/verilog/sl_sram.v
index d99ee2d..64b0786 100644
--- a/sram/verilog/sl_sram.v
+++ b/sram/verilog/sl_sram.v
@@ -35,7 +35,7 @@ module sl_sram #(
// fixed pre-compiled 16K instance supported
localparam TIE_EMA = 3'b010;
localparam TIE_EMAW = 2'b00;
-wire [11:0] ADDR12 = ADDR;
+wire [AW-3:0] ADDR12 = ADDR;
wire [31:0] WDATA32 = WDATA;
wire [31:0] RDATA32;
assign RDATA = RDATA32;
@@ -44,22 +44,47 @@ wire GWEN = &(~WREN);
wire [31:0] WEN32 = { {8{!WREN[3]}},{8{!WREN[2]}},{8{!WREN[1]}},{8{!WREN[0]}} };
localparam TIE_RET1N = 1'b1;
- rf_sp_hdf
- u_rf_sp_hdf (
-`ifdef POWER_PINS
- .VDD (VDD),
- .VSS (VSS),
-`endif
- .Q (RDATA32),
- .CLK (HCLK),
- .CEN (CEN),
- .WEN (WEN32),
- .A (ADDR12),
- .D (WDATA32),
- .EMA (TIE_EMA),
- .EMAW (TIE_EMAW),
- .GWEN (GWEN),
- .RET1N (TIE_RET1N)
- );
+generate
+ if (AW==14) begin
+ rf_16k
+ u_rf_sp_hdf (
+ `ifdef POWER_PINS
+ .VDD (VDD),
+ .VSS (VSS),
+ `endif
+ .Q (RDATA32),
+ .CLK (HCLK),
+ .CEN (CEN),
+ .WEN (WEN32),
+ .A (ADDR12),
+ .D (WDATA32),
+ .EMA (TIE_EMA),
+ .EMAW (TIE_EMAW),
+ .GWEN (GWEN),
+ .RET1N (TIE_RET1N)
+ );
+
+ end
+ else if (AW==13) begin
+ rf_08k
+ u_rf_sp_hdf (
+ `ifdef POWER_PINS
+ .VDD (VDD),
+ .VSS (VSS),
+ `endif
+ .Q (RDATA32),
+ .CLK (HCLK),
+ .CEN (CEN),
+ .WEN (WEN32),
+ .A (ADDR12),
+ .D (WDATA32),
+ .EMA (TIE_EMA),
+ .EMAW (TIE_EMAW),
+ .GWEN (GWEN),
+ .RET1N (TIE_RET1N)
+ );
+ end
+endgenerate
+
endmodule
--
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