diff --git a/sram/TSMC28nm/verilog/sl_sram.v b/sram/TSMC28nm/verilog/sl_sram.v
index a6d99a471e86547e296448f84d8ebace877b2d05..192e61b41cb1e275f61a2542ae229fa915213b86 100644
--- a/sram/TSMC28nm/verilog/sl_sram.v
+++ b/sram/TSMC28nm/verilog/sl_sram.v
@@ -61,7 +61,11 @@ generate
       .EMA   (TIE_EMA),
       .EMAW  (TIE_EMAW),
       .GWEN  (GWEN),
-      .RET1N (TIE_RET1N)
+      .RET1N (TIE_RET1N),
+      .EMAS  (1'b0),
+      .STOV  (1'b0),
+      .WABL  (1'b1),
+      .WABLM (2'b00)
     );
 
   end
@@ -81,7 +85,11 @@ generate
       .EMA   (TIE_EMA),
       .EMAW  (TIE_EMAW),
       .GWEN  (GWEN),
-      .RET1N (TIE_RET1N)
+      .RET1N (TIE_RET1N),
+      .EMAS  (1'b0),
+      .STOV  (1'b0),
+      .WABL  (1'b1),
+      .WABLM (2'b00)
     );
   end
 endgenerate