From 5687e4966986706e13dcc9fe14a7ec741a57a022 Mon Sep 17 00:00:00 2001
From: Daniel Newbrook <dwn1c21@soton.ac.uk>
Date: Tue, 3 Oct 2023 14:52:29 +0100
Subject: [PATCH] Add Pad files to override generic_lib
---
...sic_lib_mem_ip.flist => asic_lib_ip.flist} | 8 ++++
pads/verilog/PAD_INOUT8MA_NOE.v | 31 ++++++++++++++
pads/verilog/PAD_VDDIO.v | 18 ++++++++
pads/verilog/PAD_VDDSOC.v | 19 +++++++++
pads/verilog/PAD_VSS.v | 18 ++++++++
pads/verilog/PAD_VSSIO.v | 19 +++++++++
sram/verilog/sl_ahb_sram.v | 5 +--
sram/verilog/sl_sram.v | 10 ++---
sync/verilog/SYNCHRONIZER_EDGES.v | 42 +++++++++++++++++++
9 files changed, 161 insertions(+), 9 deletions(-)
rename flist/{asic_lib_mem_ip.flist => asic_lib_ip.flist} (74%)
create mode 100644 pads/verilog/PAD_INOUT8MA_NOE.v
create mode 100644 pads/verilog/PAD_VDDIO.v
create mode 100644 pads/verilog/PAD_VDDSOC.v
create mode 100644 pads/verilog/PAD_VSS.v
create mode 100644 pads/verilog/PAD_VSSIO.v
create mode 100644 sync/verilog/SYNCHRONIZER_EDGES.v
diff --git a/flist/asic_lib_mem_ip.flist b/flist/asic_lib_ip.flist
similarity index 74%
rename from flist/asic_lib_mem_ip.flist
rename to flist/asic_lib_ip.flist
index dab696b..323a650 100644
--- a/flist/asic_lib_mem_ip.flist
+++ b/flist/asic_lib_ip.flist
@@ -22,3 +22,11 @@
$(SOCLABS_ASIC_LIB_TECH_DIR)/sram/verilog/sl_ahb_sram.v
$(SOCLABS_ASIC_LIB_TECH_DIR)/sram/verilog/sl_sram.v
$(SOCLABS_ASIC_LIB_TECH_DIR)/rom/verilog/bootrom.v
+
+$(SOCLABS_ASIC_LIB_TECH_DIR)/pads/verilog/PAD_INOUT8MA_NOE.v
+$(SOCLABS_ASIC_LIB_TECH_DIR)/pads/verilog/PAD_VDDIO.v
+$(SOCLABS_ASIC_LIB_TECH_DIR)/pads/verilog/PAD_VSSIO.v
+$(SOCLABS_ASIC_LIB_TECH_DIR)/pads/verilog/PAD_VDDSOC.v
+$(SOCLABS_ASIC_LIB_TECH_DIR)/pads/verilog/PAD_VSS.v
+
+$(SOCLABS_ASIC_LIB_TECH_DIR)/sync/verilog/SYNCHRONIZER_EDGES.v
\ No newline at end of file
diff --git a/pads/verilog/PAD_INOUT8MA_NOE.v b/pads/verilog/PAD_INOUT8MA_NOE.v
new file mode 100644
index 0000000..fa9b73f
--- /dev/null
+++ b/pads/verilog/PAD_INOUT8MA_NOE.v
@@ -0,0 +1,31 @@
+// from GLIB_PADLIB.v
+//-----------------------------------------------------------------------------
+// soclabs generic IO pad model
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2022, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+`timescale 1ns/1ps
+
+module PAD_INOUT8MA_NOE (
+ // Inouts
+ PAD,
+ // Outputs
+ O,
+ // Inputs
+ I,
+ NOE
+ );
+ inout PAD;
+ output I;
+ input O;
+ input NOE;
+
+ bufif1 #2 (PAD, O, ~NOE);
+ buf #1 (I, PAD);
+endmodule // PAD_INOUT8MA_NOE
diff --git a/pads/verilog/PAD_VDDIO.v b/pads/verilog/PAD_VDDIO.v
new file mode 100644
index 0000000..e8eda59
--- /dev/null
+++ b/pads/verilog/PAD_VDDIO.v
@@ -0,0 +1,18 @@
+// from GLIB_PADLIB.v
+//-----------------------------------------------------------------------------
+// soclabs generic IO pad model
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2022, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module PAD_VDDIO (
+ PAD
+ );
+ inout PAD;
+ assign PAD = 1'b1;
+ endmodule // PAD_VDDIO
diff --git a/pads/verilog/PAD_VDDSOC.v b/pads/verilog/PAD_VDDSOC.v
new file mode 100644
index 0000000..02de9e9
--- /dev/null
+++ b/pads/verilog/PAD_VDDSOC.v
@@ -0,0 +1,19 @@
+// from GLIB_PADLIB.v
+//-----------------------------------------------------------------------------
+// soclabs generic IO pad model
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2022, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+// core logic supply rails (1V0, 0V)
+module PAD_VDDSOC (
+ PAD
+ );
+ inout PAD;
+ assign PAD = 1'b1;
+endmodule // PAD_VDDSOC
diff --git a/pads/verilog/PAD_VSS.v b/pads/verilog/PAD_VSS.v
new file mode 100644
index 0000000..ea07cca
--- /dev/null
+++ b/pads/verilog/PAD_VSS.v
@@ -0,0 +1,18 @@
+// from GLIB_PADLIB.v
+//-----------------------------------------------------------------------------
+// soclabs generic IO pad model
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2022, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module PAD_VSS (
+ PAD
+ );
+ inout PAD;
+ assign PAD = 1'b0;
+endmodule // PAD_VSS
diff --git a/pads/verilog/PAD_VSSIO.v b/pads/verilog/PAD_VSSIO.v
new file mode 100644
index 0000000..42d9edb
--- /dev/null
+++ b/pads/verilog/PAD_VSSIO.v
@@ -0,0 +1,19 @@
+// from GLIB_PADLIB.v
+//-----------------------------------------------------------------------------
+// soclabs generic IO pad model
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2022, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module PAD_VSSIO (
+ PAD
+ );
+ inout PAD;
+ assign PAD = 1'b0;
+endmodule // PAD_VSSIO
+
diff --git a/sram/verilog/sl_ahb_sram.v b/sram/verilog/sl_ahb_sram.v
index 02f1e52..7ac14f6 100644
--- a/sram/verilog/sl_ahb_sram.v
+++ b/sram/verilog/sl_ahb_sram.v
@@ -79,9 +79,8 @@ module sl_ahb_sram #(
.AW (RAM_ADDR_W)
) u_sram (
`ifdef POWER_PINS
- .VDDCE (VDD),
- .VDDPE (VDD),
- .VSSE (VSS),
+ .VDD (VDD),
+ .VSS (VSS),
`endif
// SRAM Inputs
.CLK (HCLK),
diff --git a/sram/verilog/sl_sram.v b/sram/verilog/sl_sram.v
index 4bf5d9a..f0e05b6 100644
--- a/sram/verilog/sl_sram.v
+++ b/sram/verilog/sl_sram.v
@@ -18,9 +18,8 @@ module sl_sram #(
)
(
`ifdef POWER_PINS
- inout wire VDDCE,
- inout wire VDDPE,
- inout wire VSSE,
+ inout wire VDD,
+ inout wire VSS,
`endif
// Inputs
input wire CLK,
@@ -43,9 +42,8 @@ localparam TIE_RET1N = 1'b1;
rf_sp_hdf
u_rf_sp_hdf (
`ifdef POWER_PINS
- .VDDCE (VDDCE),
- .VDDPE (VDDPE),
- .VSSE (VSSE),
+ .VDD (VDD),
+ .VSS (VSS),
`endif
.Q (RDATA),
.CLK (CLK),
diff --git a/sync/verilog/SYNCHRONIZER_EDGES.v b/sync/verilog/SYNCHRONIZER_EDGES.v
new file mode 100644
index 0000000..c669ec1
--- /dev/null
+++ b/sync/verilog/SYNCHRONIZER_EDGES.v
@@ -0,0 +1,42 @@
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright © 2022, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module SYNCHRONIZER_EDGES (
+ input wire testmode_i
+ ,input wire clk_i
+ ,input wire reset_n_i
+ ,input wire asyn_i
+ ,output wire syn_o
+ ,output wire syn_del_o
+ ,output wire posedge_o
+ ,output wire negedge_o
+ );
+
+reg sync_stage1;
+reg sync_stage2;
+reg sync_stage3;
+
+ always @(posedge clk_i or negedge reset_n_i)
+ if(~reset_n_i) begin
+ sync_stage1 <= 1'b0;
+ sync_stage2 <= 1'b0;
+ sync_stage3 <= 1'b0;
+ end
+ else begin
+ sync_stage1 <= asyn_i;
+ sync_stage2 <= sync_stage1;
+ sync_stage3 <= sync_stage2;
+ end
+
+assign syn_o = (testmode_i) ? asyn_i : sync_stage2;
+assign syn_del_o = (testmode_i) ? asyn_i : sync_stage3;
+assign posedge_o = (testmode_i) ? asyn_i : ( sync_stage2 & !sync_stage3);
+assign negedge_o = (testmode_i) ? asyn_i : (!sync_stage2 & sync_stage3);
+
+endmodule
--
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