diff --git a/flist/asic_lib_mem_ip.flist b/flist/asic_lib_mem_ip.flist
index 8aeef8b8579ad1e196e081eec06a79fb8ca0800e..dab696b4a0d9f5571cda1590dd4cf5b68b01d253 100644
--- a/flist/asic_lib_mem_ip.flist
+++ b/flist/asic_lib_mem_ip.flist
@@ -20,5 +20,5 @@
// - Top-level testbench
$(SOCLABS_ASIC_LIB_TECH_DIR)/sram/verilog/sl_ahb_sram.v
-$(SOCLABS_ASIC_LIB_TECH_DIR)/rom/verilog/sl_ahb_rom.v
$(SOCLABS_ASIC_LIB_TECH_DIR)/sram/verilog/sl_sram.v
+$(SOCLABS_ASIC_LIB_TECH_DIR)/rom/verilog/bootrom.v
diff --git a/rom/verilog/bootrom.v b/rom/verilog/bootrom.v
new file mode 100644
index 0000000000000000000000000000000000000000..c4b465d80a65f9221e7ea642f6e6fb6b53353236
--- /dev/null
+++ b/rom/verilog/bootrom.v
@@ -0,0 +1,46 @@
+//-----------------------------------------------------------------------------
+// SoCLabs ASIC ROM Wrapper
+// - substituded using the same name from the FPGA tech library
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// Daniel Newbrook (d.newbrook@soton.ac.uk)
+//
+// Copyright 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module bootrom #(
+ parameter AW_ADDR_W = 8
+)(
+ `ifdef POWER_PINS
+ inout VDD,
+ inout VSS,
+ `endif
+ input wire CLK,
+ input wire EN,
+ input wire [7:0] W_ADDR,
+ output reg [31:0] RDATA
+);
+
+ rom_via
+ u_sl_rom(
+ `ifdef POWER_PINS
+ .VDDE(VDD),
+ .VSSE(VSS),
+ `endif
+ .Q(RDATA),
+ .CLK(CLK),
+ .CEN(EN),
+ .A(W_ADDR),
+ .EMA(3'b000),
+ .TEN(1'b1),
+ .BEN(1'b1),
+ .TCEN(1'b0),
+ .TA(8'b0),
+ .TQ(32'b0),
+ .PGEN(1'b0),
+ .KEN(1'b1)
+ );
+
+endmodule
\ No newline at end of file
diff --git a/rom/verilog/sl_ahb_rom.v b/rom/verilog/sl_ahb_rom.v
deleted file mode 100644
index 241563c9ca84399f54038e09ad6f6c83cca4a021..0000000000000000000000000000000000000000
--- a/rom/verilog/sl_ahb_rom.v
+++ /dev/null
@@ -1,89 +0,0 @@
-//-----------------------------------------------------------------------------
-// SoCLabs FPGA ROM Wrapper
-// - to be substitued with same name file in filelist when moving to ASIC
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright 2021-3, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-
-module sl_ahb_rom #(
- // System Parameters
- parameter SYS_DATA_W = 32, // System Data Width
- parameter RAM_ADDR_W = 14, // Size of SRAM
- parameter RAM_DATA_W = 32, // Data Width of RAM
- parameter FILENAME = "image.hex" // Initial Image to Populate Memory with
-)(
- // --------------------------------------------------------------------------
- // Port Definitions
- // --------------------------------------------------------------------------
- input wire HCLK, // system bus clock
- input wire HRESETn, // system bus reset
- input wire HSEL, // AHB peripheral select
- input wire HREADY, // AHB ready input
- input wire [1:0] HTRANS, // AHB transfer type
- input wire [2:0] HSIZE, // AHB hsize
- input wire HWRITE, // AHB hwrite
- input wire [RAM_ADDR_W-1:0] HADDR, // AHB address bus
- input wire [SYS_DATA_W-1:0] HWDATA, // AHB write data bus
- output wire HREADYOUT, // AHB ready output to S->M mux
- output wire HRESP, // AHB response
- output wire [SYS_DATA_W-1:0] HRDATA // AHB read data bus
-);
-
- // Internal Wiring
- wire [RAM_ADDR_W-3:0] addr;
- wire [RAM_DATA_W-1:0] wdata;
- wire [RAM_DATA_W-1:0] rdata;
- wire [3:0] wen;
- wire cs;
-
- // AHB to SRAM Conversion
- cmsdk_ahb_to_sram #(
- .AW (RAM_ADDR_W)
- ) u_ahb_to_sram (
- // AHB Inputs
- .HCLK (HCLK),
- .HRESETn (HRESETn),
- .HSEL (HSEL),
- .HADDR (HADDR[RAM_ADDR_W-1:0]),
- .HTRANS (HTRANS),
- .HSIZE (HSIZE),
- .HWRITE (HWRITE),
- .HWDATA (HWDATA),
- .HREADY (HREADY),
-
- // AHB Outputs
- .HREADYOUT (HREADYOUT),
- .HRDATA (HRDATA),
- .HRESP (HRESP),
-
- // SRAM input
- .SRAMRDATA (rdata),
-
- // SRAM Outputs
- .SRAMADDR (addr),
- .SRAMWDATA (wdata),
- .SRAMWEN (wen),
- .SRAMCS (cs)
- );
-
- // FPGA SRAM model
- sl_rom #(
- .AW (RAM_ADDR_W),
- .filename (FILENAME)
- ) u_sram (
- // SRAM Inputs
- .CLK (HCLK),
- .ADDR (addr),
- .WDATA (wdata),
- .WREN (wen),
- .CS (cs),
-
- // SRAM Output
- .RDATA (rdata)
- );
-endmodule
\ No newline at end of file
diff --git a/rom/verilog/sl_rom.v b/rom/verilog/sl_rom.v
deleted file mode 100644
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..0000000000000000000000000000000000000000
diff --git a/sram/verilog/sl_ahb_sram.v b/sram/verilog/sl_ahb_sram.v
index c511881d03125a1b8c937ad70c5e57806a1759b6..02f1e52fe46aec6136290eab30f376fffe34e7a7 100644
--- a/sram/verilog/sl_ahb_sram.v
+++ b/sram/verilog/sl_ahb_sram.v
@@ -17,9 +17,6 @@ module sl_ahb_sram #(
parameter RAM_DATA_W = 32 // Data Width of RAM
)(
`ifdef POWER_PINS
- inout wire VDDCE,
- inout wire VDDPE,
- inout wire VSSE,
inout wire VDD,
inout wire VSS,
`endif
@@ -82,9 +79,9 @@ module sl_ahb_sram #(
.AW (RAM_ADDR_W)
) u_sram (
`ifdef POWER_PINS
- .VDDCE (VDDCE),
- .VDDPE (VDDPE),
- .VSSE (VSSE),
+ .VDDCE (VDD),
+ .VDDPE (VDD),
+ .VSSE (VSS),
`endif
// SRAM Inputs
.CLK (HCLK),
diff --git a/sram/verilog/sl_sram.v b/sram/verilog/sl_sram.v
index 161a58b1457d4bc468cd54dcf0e4c983659697ff..4bf5d9ab7a0d847244b0742e6fa5d7fd9b827e56 100644
--- a/sram/verilog/sl_sram.v
+++ b/sram/verilog/sl_sram.v
@@ -1,3 +1,15 @@
+//-----------------------------------------------------------------------------
+// SoCLabs ASIC RAM Wrapper
+// - substituted using the same name from the FPGA tech library
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.flynn@soton.ac.uk)
+//
+// Copyright 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
module sl_sram #(
// --------------------------------------------------------------------------
// Parameter Declarations