From 28d17f2aa58ecf27e8168e8c5874457caaf29f4f Mon Sep 17 00:00:00 2001
From: Daniel Newbrook <dwn1c21@soton.ac.uk>
Date: Thu, 12 Sep 2024 10:15:04 +0100
Subject: [PATCH] Initial update for 65nm and 28nm flows
---
flist/asic_lib_ip.flist | 12 ++---
flist/asic_lib_ip_TSMC28nm.flist | 26 +++++++++
sram/TSMC28nm/verilog/sl_sram.v | 90 ++++++++++++++++++++++++++++++++
sram/verilog/sl_ahb_sram.v | 2 +-
4 files changed, 120 insertions(+), 10 deletions(-)
create mode 100644 flist/asic_lib_ip_TSMC28nm.flist
create mode 100644 sram/TSMC28nm/verilog/sl_sram.v
diff --git a/flist/asic_lib_ip.flist b/flist/asic_lib_ip.flist
index 323a650..a649b89 100644
--- a/flist/asic_lib_ip.flist
+++ b/flist/asic_lib_ip.flist
@@ -1,5 +1,5 @@
//-----------------------------------------------------------------------------
-// FPGA Library Memory Filelist
+// ASIC Library Memory Filelist
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
@@ -9,7 +9,7 @@
// Copyright � 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
-// Abstract : Verilog Command File for NanoSoC Testbench
+// Abstract : Verilog Command File for ASIC Memories
//-----------------------------------------------------------------------------
// ============= Verilog library extensions ===========
@@ -18,15 +18,9 @@
// ============= NanoSoC Testbench search path =============
// +incdir+$(SOCLABS_ASIC_LIB_TECH_DIR)/sram/verilog/
-// - Top-level testbench
+// - Memories
$(SOCLABS_ASIC_LIB_TECH_DIR)/sram/verilog/sl_ahb_sram.v
$(SOCLABS_ASIC_LIB_TECH_DIR)/sram/verilog/sl_sram.v
$(SOCLABS_ASIC_LIB_TECH_DIR)/rom/verilog/bootrom.v
-$(SOCLABS_ASIC_LIB_TECH_DIR)/pads/verilog/PAD_INOUT8MA_NOE.v
-$(SOCLABS_ASIC_LIB_TECH_DIR)/pads/verilog/PAD_VDDIO.v
-$(SOCLABS_ASIC_LIB_TECH_DIR)/pads/verilog/PAD_VSSIO.v
-$(SOCLABS_ASIC_LIB_TECH_DIR)/pads/verilog/PAD_VDDSOC.v
-$(SOCLABS_ASIC_LIB_TECH_DIR)/pads/verilog/PAD_VSS.v
-
$(SOCLABS_ASIC_LIB_TECH_DIR)/sync/verilog/SYNCHRONIZER_EDGES.v
\ No newline at end of file
diff --git a/flist/asic_lib_ip_TSMC28nm.flist b/flist/asic_lib_ip_TSMC28nm.flist
new file mode 100644
index 0000000..8e2b4a0
--- /dev/null
+++ b/flist/asic_lib_ip_TSMC28nm.flist
@@ -0,0 +1,26 @@
+//-----------------------------------------------------------------------------
+// ASIC Library Memory Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// Daniel Newbrook (d.newbrook@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for NanoSoC Testbench
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// ============= NanoSoC Testbench search path =============
+// +incdir+$(SOCLABS_ASIC_LIB_TECH_DIR)/sram/verilog/
+
+// - Memories
+$(SOCLABS_ASIC_LIB_TECH_DIR)/sram/verilog/sl_ahb_sram.v
+$(SOCLABS_ASIC_LIB_TECH_DIR)/sram/TSMC28nm/verilog/sl_sram.v
+$(SOCLABS_ASIC_LIB_TECH_DIR)/rom/verilog/bootrom.v
+
+$(SOCLABS_ASIC_LIB_TECH_DIR)/sync/verilog/SYNCHRONIZER_EDGES.v
\ No newline at end of file
diff --git a/sram/TSMC28nm/verilog/sl_sram.v b/sram/TSMC28nm/verilog/sl_sram.v
new file mode 100644
index 0000000..a6d99a4
--- /dev/null
+++ b/sram/TSMC28nm/verilog/sl_sram.v
@@ -0,0 +1,90 @@
+//-----------------------------------------------------------------------------
+// SoCLabs ASIC RAM Wrapper
+// - substituted using the same name from the FPGA tech library
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.flynn@soton.ac.uk)
+//
+// Copyright 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module sl_sram #(
+// --------------------------------------------------------------------------
+// Parameter Declarations
+// --------------------------------------------------------------------------
+ parameter AW = 16
+ )
+ (
+ `ifdef POWER_PINS
+ inout wire VDD,
+ inout wire VSS,
+ `endif
+ // Inputs
+ input wire CLK,
+ input wire [AW-1:2] ADDR,
+ input wire [31:0] WDATA,
+ input wire [3:0] WREN,
+ input wire CS,
+
+ // Outputs
+ output wire [31:0] RDATA
+ );
+
+// fixed pre-compiled 16K instance supported
+localparam TIE_EMA = 3'b010;
+localparam TIE_EMAW = 2'b00;
+wire [AW-3:0] ADDR12 = ADDR;
+wire [31:0] WDATA32 = WDATA;
+wire [31:0] RDATA32;
+assign RDATA = RDATA32;
+wire CEN = !CS;
+wire GWEN = &(~WREN);
+wire [31:0] WEN32 = { {8{!WREN[3]}},{8{!WREN[2]}},{8{!WREN[1]}},{8{!WREN[0]}} };
+localparam TIE_RET1N = 1'b1;
+
+generate
+ if (AW==14) begin
+ sram_16k
+ u_sram (
+ `ifdef POWER_PINS
+ .VDD (VDD),
+ .VSS (VSS),
+ `endif
+ .Q (RDATA32),
+ .CLK (CLK),
+ .CEN (CEN),
+ .WEN (WEN32),
+ .A (ADDR12),
+ .D (WDATA32),
+ .EMA (TIE_EMA),
+ .EMAW (TIE_EMAW),
+ .GWEN (GWEN),
+ .RET1N (TIE_RET1N)
+ );
+
+ end
+ else if (AW==15) begin
+ sram_32k
+ u_sram (
+ `ifdef POWER_PINS
+ .VDD (VDD),
+ .VSS (VSS),
+ `endif
+ .Q (RDATA32),
+ .CLK (CLK),
+ .CEN (CEN),
+ .WEN (WEN32),
+ .A (ADDR12),
+ .D (WDATA32),
+ .EMA (TIE_EMA),
+ .EMAW (TIE_EMAW),
+ .GWEN (GWEN),
+ .RET1N (TIE_RET1N)
+ );
+ end
+endgenerate
+
+
+endmodule
diff --git a/sram/verilog/sl_ahb_sram.v b/sram/verilog/sl_ahb_sram.v
index 7ac14f6..c209db4 100644
--- a/sram/verilog/sl_ahb_sram.v
+++ b/sram/verilog/sl_ahb_sram.v
@@ -74,7 +74,7 @@ module sl_ahb_sram #(
.SRAMCS (cs)
);
- // FPGA SRAM model
+ // ASIC SRAM model
sl_sram #(
.AW (RAM_ADDR_W)
) u_sram (
--
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