diff --git a/flist/asic_lib_ip_TSMC28nm.flist b/flist/asic_lib_ip_TSMC28nm.flist index 8e2b4a01ef08e346f8340536e2fc02922c42f384..8e0aca676cd34000ee99dc4f6a25b8738478ccaa 100644 --- a/flist/asic_lib_ip_TSMC28nm.flist +++ b/flist/asic_lib_ip_TSMC28nm.flist @@ -21,6 +21,6 @@ // - Memories $(SOCLABS_ASIC_LIB_TECH_DIR)/sram/verilog/sl_ahb_sram.v $(SOCLABS_ASIC_LIB_TECH_DIR)/sram/TSMC28nm/verilog/sl_sram.v -$(SOCLABS_ASIC_LIB_TECH_DIR)/rom/verilog/bootrom.v +$(SOCLABS_ASIC_LIB_TECH_DIR)/rom/TSMC28nm/verilog/bootrom.v $(SOCLABS_ASIC_LIB_TECH_DIR)/sync/verilog/SYNCHRONIZER_EDGES.v \ No newline at end of file diff --git a/rom/TSMC28nm/verilog/bootrom.v b/rom/TSMC28nm/verilog/bootrom.v new file mode 100644 index 0000000000000000000000000000000000000000..fa7ce4955eae7c717a447aae086501215904c846 --- /dev/null +++ b/rom/TSMC28nm/verilog/bootrom.v @@ -0,0 +1,46 @@ +//----------------------------------------------------------------------------- +// SoCLabs ASIC ROM Wrapper +// - substituded using the same name from the FPGA tech library +// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. +// +// Contributors +// +// Daniel Newbrook (d.newbrook@soton.ac.uk) +// +// Copyright 2021-3, SoC Labs (www.soclabs.org) +//----------------------------------------------------------------------------- + +module bootrom #( + parameter AW_ADDR_W = 8 +)( + `ifdef POWER_PINS + inout VDD, + inout VSS, + `endif + input wire CLK, + input wire EN, + input wire [7:0] W_ADDR, + output reg [31:0] RDATA +); + + rom_via + u_sl_rom( + `ifdef POWER_PINS + .VDD(VDD), + .VSSE(VSS), + `endif + .Q(RDATA), + .CLK(CLK), + .CEN(!EN), + .A(W_ADDR), + .EMA(3'b010), + .TEN(1'b1), + .BEN(1'b1), + .TCEN(1'b0), + .TA(8'b0), + .TQ(32'b0), + .PGEN(1'b0), + .KEN(1'b1) + ); + +endmodule