diff --git a/fpga/pynq_z2/PYNQ-Z2 v1.0.xdc b/fpga/pynq_z2/PYNQ-Z2 v1.0.xdc
index e853b06ec0e68e763ba878ef3d6894118f090c42..052ae19f1a94c1d717589f59cc24317829efdf24 100644
--- a/fpga/pynq_z2/PYNQ-Z2 v1.0.xdc
+++ b/fpga/pynq_z2/PYNQ-Z2 v1.0.xdc
@@ -1,200 +1,14 @@
-set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS33} [get_ports QSPI_nCS_0]
-set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVCMOS33} [get_ports {QSPI_IO_0[0]}]
-set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS33} [get_ports {QSPI_IO_0[1]}]
-set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS33} [get_ports QSPI_SCLK_0]
-set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVCMOS33} [get_ports RESET]
-set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS33} [get_ports {QSPI_IO_0[2]}]
-set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS33} [get_ports {QSPI_IO_0[3]}]
-#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L12P_T1_MRCC_34 Sch=ja_p[3]
+set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports QSPI_nCS_0];
+set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports {QSPI_IO_0[0]}];
+set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports {QSPI_IO_0[1]}];
+set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports QSPI_SCLK_0];
+set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports RESET];
+set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports {QSPI_IO_0[2]}];
+set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports {QSPI_IO_0[3]}];
-## This file is a general .xdc for the PYNQ-Z2 board
-## To use it in a project:
-## - uncomment the lines corresponding to used pins
-## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
-## Clock signal 125 MHz
-
-#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { sysclk }]; #IO_L13P_T2_MRCC_35 Sch=sysclk
-#create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { sysclk }];
-
-##Switches
-
-#set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L7N_T1_AD2N_35 Sch=sw[0]
-#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L7P_T1_AD2P_35 Sch=sw[1]
-
-##RGB LEDs
-
-#set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { led4_b }]; #IO_L22N_T3_AD7N_35 Sch=led4_b
-#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { led4_g }]; #IO_L16P_T2_35 Sch=led4_g
-#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led4_r }]; #IO_L21P_T3_DQS_AD14P_35 Sch=led4_r
-#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led5_b }]; #IO_0_35 Sch=led5_b
-#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { led5_g }]; #IO_L22P_T3_AD7P_35 Sch=led5_g
-#set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { led5_r }]; #IO_L23N_T3_35 Sch=led5_r
-
-##LEDs
-
-#set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L6N_T0_VREF_34 Sch=led[0]
-#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L6P_T0_34 Sch=led[1]
-#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L21N_T3_DQS_AD14N_35 Sch=led[2]
-#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L23P_T3_35 Sch=led[3]
-
-##Buttons
-
-#set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L4P_T0_35 Sch=btn[0]
-#set_property -dict { PACKAGE_PIN D20 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L4N_T0_35 Sch=btn[1]
-#set_property -dict { PACKAGE_PIN L20 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L9N_T1_DQS_AD3N_35 Sch=btn[2]
-#set_property -dict { PACKAGE_PIN L19 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L9P_T1_DQS_AD3P_35 Sch=btn[3]
-
-##PmodA
-
-
-##PmodB
-
-#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L8P_T1_34 Sch=jb_p[1]
-#set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L8N_T1_34 Sch=jb_n[1]
-#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L1P_T0_34 Sch=jb_p[2]
-#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L1N_T0_34 Sch=jb_n[2]
-#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L18P_T2_34 Sch=jb_p[3]
-#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L18N_T2_34 Sch=jb_n[3]
-#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L4P_T0_34 Sch=jb_p[4]
-#set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L4N_T0_34 Sch=jb_n[4]
-
-##Audio
-
-#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { adr0 }]; #IO_L8P_T1_AD10P_35 Sch=adr0
-#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { adr1 }]; #IO_L8N_T1_AD10N_35 Sch=adr1
-
-#set_property -dict { PACKAGE_PIN U5 IOSTANDARD LVCMOS33 } [get_ports { au_mclk_r }]; #IO_L19N_T3_VREF_13 Sch=au_mclk_r
-#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { au_sda_r }]; #IO_L12P_T1_MRCC_13 Sch=au_sda_r
-#set_property -dict { PACKAGE_PIN U9 IOSTANDARD LVCMOS33 } [get_ports { au_scl_r }]; #IO_L17P_T2_13 Sch= au_scl_r
-#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports { au_dout_r }]; #IO_L6N_T0_VREF_35 Sch=au_dout_r
-#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { au_din_r }]; #IO_L16N_T2_35 Sch=au_din_r
-#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { au_wclk_r }]; #IO_L20P_T3_34 Sch=au_wclk_r
-#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { au_bclk_r }]; #IO_L20N_T3_34 Sch=au_bclk_r
-
-
-## Single Ended Analog Inputs
-##NOTE: The ar_an_p pins can be used as single ended analog inputs with voltages from 0-3.3V (Arduino Analog pins a[0]-a[5]).
-## These signals should only be connected to the XADC core. When using these pins as digital I/O, use pins a[0]-a[5].
-
-#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { ar_an0_p }]; #IO_L3P_T0_DQS_AD1P_35 Sch=ar_an0_p
-#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { ar_an0_n }]; #IO_L3P_T0_DQS_AD1P_35 Sch=ar_an0_n
-#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { ar_an1_p }]; #IO_L5N_T0_AD9P_35 Sch=ar_an1_p
-#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports { ar_an1_n }]; #IO_L5N_T0_AD9N_35 Sch=ar_an1_n
-#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { ar_an2_p }]; #IO_L20P_T3_AD6P_35 Sch=ar_an2_p
-#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { ar_an2_n }]; #IO_L20P_T3_AD6N_35 Sch=ar_an2_n
-#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { ar_an3_p }]; #IO_L24P_T3_AD15P_35 Sch=ar_an3_p
-#set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { ar_an3_n }]; #IO_L24P_T3_AD15N_35 Sch=ar_an3_n
-#set_property -dict { PACKAGE_PIN J20 IOSTANDARD LVCMOS33 } [get_ports { ar_an4_p }]; #IO_L17P_T2_AD5P_35 Sch=ar_an4_p
-#set_property -dict { PACKAGE_PIN H20 IOSTANDARD LVCMOS33 } [get_ports { ar_an4_n }]; #IO_L17P_T2_AD5P_35 Sch=ar_an4_n
-#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { ar_an5_p }]; #IO_L18P_T2_AD13P_35 Sch=ar_an5_p
-#set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS33 } [get_ports { ar_an5_n }]; #IO_L18P_T2_AD13P_35 Sch=ar_an5_n
-
-##Arduino Digital I/O
-
-#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { ar[0] }]; #IO_L5P_T0_34 Sch=ar[0]
-#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { ar[1] }]; #IO_L2N_T0_34 Sch=ar[1]
-#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { ar[2] }]; #IO_L3P_T0_DQS_PUDC_B_34 Sch=ar[2]
-#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { ar[3] }]; #IO_L3N_T0_DQS_34 Sch=ar[3]
-#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { ar[4] }]; #IO_L10P_T1_34 Sch=ar[4]
-#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { ar[5] }]; #IO_L5N_T0_34 Sch=ar[5]
-#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { ar[6] }]; #IO_L19P_T3_34 Sch=ar[6]
-#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { ar[7] }]; #IO_L9N_T1_DQS_34 Sch=ar[7]
-#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { ar[8] }]; #IO_L21P_T3_DQS_34 Sch=ar[8]
-#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { ar[9] }]; #IO_L21N_T3_DQS_34 Sch=ar[9]
-#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { ar[10] }]; #IO_L9P_T1_DQS_34 Sch=ar[10]
-#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { ar[11] }]; #IO_L19N_T3_VREF_34 Sch=ar[11]
-#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { ar[12] }]; #IO_L23N_T3_34 Sch=ar[12]
-#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { ar[13] }]; #IO_L23P_T3_34 Sch=ar[13]
-#set_property -dict { PACKAGE_PIN Y13 IOSTANDARD LVCMOS33 } [get_ports { a }]; #IO_L20N_T3_13 Sch=a
-
-##Arduino Digital I/O On Outer Analog Header
-##NOTE: These pins should be used when using the analog header signals A0-A5 as digital I/O
-
-#set_property -dict { PACKAGE_PIN Y11 IOSTANDARD LVCMOS33 } [get_ports { a[0] }]; #IO_L18N_T2_13 Sch=a[0]
-#set_property -dict { PACKAGE_PIN Y12 IOSTANDARD LVCMOS33 } [get_ports { a[1] }]; #IO_L20P_T3_13 Sch=a[1]
-#set_property -dict { PACKAGE_PIN W11 IOSTANDARD LVCMOS33 } [get_ports { a[2] }]; #IO_L18P_T2_13 Sch=a[2]
-#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { a[3] }]; #IO_L21P_T3_DQS_13 Sch=a[3]
-#set_property -dict { PACKAGE_PIN T5 IOSTANDARD LVCMOS33 } [get_ports { a[4] }]; #IO_L19P_T3_13 Sch=a[4]
-#set_property -dict { PACKAGE_PIN U10 IOSTANDARD LVCMOS33 } [get_ports { a[5] }]; #IO_L12N_T1_MRCC_13 Sch=a[5]
-
-## Arduino SPI
-
-#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { ck_miso }]; #IO_L10N_T1_34 Sch=miso
-#set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { ck_mosi }]; #IO_L2P_T0_34 Sch=ar_mosi_r
-#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { ck_sck }]; #IO_L19P_T3_35 Sch=sck
-#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { ck_ss }]; #IO_L6P_T0_35 Sch=ss
-
-## Arduino I2C
-
-#set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { ar_scl }]; #IO_L24N_T3_34 Sch=ar_scl
-#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ar_sda }]; #IO_L24P_T3_34 Sch=ar_sda
-
-##Raspberry Digital I/O
-
-#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { rpio_02_r }]; #IO_L22P_T3_34 Sch=rpio_02_r
-#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { rpio_03_r }]; #IO_L22N_T3_34 Sch=rpio_03_r
-#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { rpio_04_r }]; #IO_L17P_T2_34 Sch=rpio_04_r
-#set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { rpio_05_r }]; #IO_L17N_T2_34 Sch=rpio_05_r
-#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { rpio_06_r }]; #IO_L22P_T3_13 Sch=rpio_06_r
-#set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports { rpio_07_r }]; #IO_L12P_T1_MRCC_34 Sch=rpio_07_r
-#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { rpio_08_r }]; #IO_L12N_T1_MRCC_34 Sch=rpio_08_r
-#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { rpio_09_r }]; #IO_L21N_T3_DQS_13 Sch=rpio_09_r
-#set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 } [get_ports { rpio_10_r }]; #IO_L15P_T2_DQS_13 Sch=rpio_10_r
-#set_property -dict { PACKAGE_PIN W10 IOSTANDARD LVCMOS33 } [get_ports { rpio_11_r }]; #IO_L16P_T2_13 Sch=rpio_11_r
-#set_property -dict { PACKAGE_PIN B20 IOSTANDARD LVCMOS33 } [get_ports { rpio_12_r }]; #IO_L1N_T0_AD0N_35 Sch=rpio_12_r
-#set_property -dict { PACKAGE_PIN W8 IOSTANDARD LVCMOS33 } [get_ports { rpio_13_r }]; #IO_L15N_T2_DQS_13 Sch=rpio_13_r
-#set_property -dict { PACKAGE_PIN V6 IOSTANDARD LVCMOS33 } [get_ports { rpio_14_r }]; #IO_L22P_T3_13 Sch=rpio_14_r
-#set_property -dict { PACKAGE_PIN Y6 IOSTANDARD LVCMOS33 } [get_ports { rpio_15_r }]; #IO_L13N_T2_MRCC_13 Sch=rpio_15_r
-#set_property -dict { PACKAGE_PIN B19 IOSTANDARD LVCMOS33 } [get_ports { rpio_16_r }]; #IO_L2P_T0_AD8P_35 Sch=rpio_16_r
-#set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports { rpio_17_r }]; #IO_L11P_T1_SRCC_13 Sch=rpio_17_r
-#set_property -dict { PACKAGE_PIN C20 IOSTANDARD LVCMOS33 } [get_ports { rpio_18_r }]; #IO_L1P_T0_AD0P_35 Sch=rpio_18_r
-#set_property -dict { PACKAGE_PIN Y8 IOSTANDARD LVCMOS33 } [get_ports { rpio_19_r }]; #IO_L14N_T2_SRCC_13 Sch=rpio_19_r
-#set_property -dict { PACKAGE_PIN A20 IOSTANDARD LVCMOS33 } [get_ports { rpio_20_r }]; #IO_L2N_T0_AD8N_35 Sch=rpio_20_r
-#set_property -dict { PACKAGE_PIN Y9 IOSTANDARD LVCMOS33 } [get_ports { rpio_21_r }]; #IO_L14P_T2_SRCC_13 Sch=rpio_21_r
-#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS33 } [get_ports { rpio_22_r }]; #IO_L17N_T2_13 Sch=rpio_22_r
-#set_property -dict { PACKAGE_PIN W6 IOSTANDARD LVCMOS33 } [get_ports { rpio_23_r }]; #IO_IO_L22N_T3_13 Sch=rpio_23_r
-#set_property -dict { PACKAGE_PIN Y7 IOSTANDARD LVCMOS33 } [get_ports { rpio_24_r }]; #IO_L13P_T2_MRCC_13 Sch=rpio_24_r
-#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { rpio_25_r }]; #IO_L15N_T2_DQS_AD12N_35 Sch=rpio_25_r
-#set_property -dict { PACKAGE_PIN W9 IOSTANDARD LVCMOS33 } [get_ports { rpio_26_r }]; #IO_L16N_T2_13 Sch=rpio_26_r
-#set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { rpio_sd_r }]; #IO_L7P_T1_34 Sch=rpio_sd_r
-#set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { rpio_sc_r }]; #IO_L7N_T1_34 Sch=rpio_sc_r
-
-##HDMI Rx
-
-#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L13N_T2_MRCC_35 Sch=hdmi_rx_cec
-#set_property -dict { PACKAGE_PIN P19 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_n }]; #IO_L13N_T2_MRCC_34 Sch=hdmi_rx_clk_n
-#set_property -dict { PACKAGE_PIN N18 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_p }]; #IO_L13P_T2_MRCC_34 Sch=hdmi_rx_clk_p
-#set_property -dict { PACKAGE_PIN W20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_d_n[0] }]; #IO_L16N_T2_34 Sch=hdmi_rx_d_n[0]
-#set_property -dict { PACKAGE_PIN V20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_d_p[0] }]; #IO_L16P_T2_34 Sch=hdmi_rx_d_p[0]
-#set_property -dict { PACKAGE_PIN U20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_d_n[1] }]; #IO_L15N_T2_DQS_34 Sch=hdmi_rx_d_n[1]
-#set_property -dict { PACKAGE_PIN T20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_d_p[1] }]; #IO_L15P_T2_DQS_34 Sch=hdmi_rx_d_p[1]
-#set_property -dict { PACKAGE_PIN P20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_d_n[2] }]; #IO_L14N_T2_SRCC_34 Sch=hdmi_rx_d_n[2]
-#set_property -dict { PACKAGE_PIN N20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_d_p[2] }]; #IO_L14P_T2_SRCC_34 Sch=hdmi_rx_d_p[2]
-#set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_hpd }]; #IO_25_34 Sch=hdmi_rx_hpd
-#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_scl }]; #IO_L11P_T1_SRCC_34 Sch=hdmi_rx_scl
-#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_sda }]; #IO_L11N_T1_SRCC_34 Sch=hdmi_rx_sda
-
-##HDMI Tx
-
-#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L19N_T3_VREF_35 Sch=hdmi_tx_cec
-#set_property -dict { PACKAGE_PIN L17 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_n }]; #IO_L11N_T1_SRCC_35 Sch=hdmi_tx_clk_n
-#set_property -dict { PACKAGE_PIN L16 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_p }]; #IO_L11P_T1_SRCC_35 Sch=hdmi_tx_clk_p
-#set_property -dict { PACKAGE_PIN K18 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_d_n[0] }]; #IO_L12N_T1_MRCC_35 Sch=hdmi_tx_d_n[0]
-#set_property -dict { PACKAGE_PIN K17 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_d_p[0] }]; #IO_L12P_T1_MRCC_35 Sch=hdmi_tx_d_p[0]
-#set_property -dict { PACKAGE_PIN J19 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_d_n[1] }]; #IO_L10N_T1_AD11N_35 Sch=hdmi_tx_d_n[1]
-#set_property -dict { PACKAGE_PIN K19 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_d_p[1] }]; #IO_L10P_T1_AD11P_35 Sch=hdmi_tx_d_p[1]
-#set_property -dict { PACKAGE_PIN H18 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_d_n[2] }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=hdmi_tx_d_n[2]
-#set_property -dict { PACKAGE_PIN J18 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_d_p[2] }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=hdmi_tx_d_p[2]
-#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_hpdn }]; #IO_0_34 Sch=hdmi_tx_hpdn
-
-
-##Crypto SDA
-
-#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_25_35 Sch=crypto_sda
-
-create_generated_clock -name QSPI_SCLK -source [get_pins {ahb_qspi_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]}] -divide_by 2 [get_pins ahb_qspi_i/AXI_QSPI_0/inst/ahb_qspi_fpga_wrapper_0/inst/u_top_ahb_qspi/u_qspi_controller/u_qspi_clock_div/QSPI_SCLK_i]
-create_generated_clock -name QSPI_CLK_o -source [get_pins ahb_qspi_i/AXI_QSPI_0/inst/ahb_qspi_fpga_wrapper_0/inst/u_top_ahb_qspi/u_qspi_controller/u_qspi_clock_div/QSPI_SCLK_i] -divide_by 1 [get_ports QSPI_SCLK_0]
+create_generated_clock -name QSPI_SCLK -source [get_pins {ahb_qspi_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]}] -divide_by 2 [get_pins ahb_qspi_i/AXI_QSPI_0/inst/ahb_qspi_fpga_wrapper_0/inst/u_top_ahb_qspi/u_qspi_clock_div/QSPI_SCLK_i]
+create_generated_clock -name QSPI_CLK_o -source [get_pins ahb_qspi_i/AXI_QSPI_0/inst/ahb_qspi_fpga_wrapper_0/inst/u_top_ahb_qspi/u_qspi_clock_div/QSPI_SCLK_i] -divide_by 1 [get_ports QSPI_SCLK_0]
set_input_delay -clock [get_clocks QSPI_SCLK] -min 0 [get_ports {QSPI_IO_0[*]}]
set_input_delay -clock [get_clocks QSPI_SCLK] -max 20 [get_ports {QSPI_IO_0[*]}]
diff --git a/logical/ahb_qspi_interface/logical/ahb_qspi_interface.sv b/logical/ahb_qspi_interface/logical/ahb_qspi_interface.sv
index 895c884f606589b2e75def53952cf80c19deea9f..e45a804a615d1dfb83c7f3cd952643e61ff0c9a3 100644
--- a/logical/ahb_qspi_interface/logical/ahb_qspi_interface.sv
+++ b/logical/ahb_qspi_interface/logical/ahb_qspi_interface.sv
@@ -20,12 +20,12 @@ module ahb_qspi_interface #(
output wire HREADYOUT,
output wire HRESP,
- output wire [7:0] AHB_QSPI_CMD,
+ input wire XIP_ACTIVE,
+
output reg AHB_QSPI_ENABLE,
output wire AHB_QSPI_READ,
output wire AHB_QSPI_WRITE,
output wire AHB_QSPI_ADDR_EN,
- output wire [3:0] AHB_QSPI_DUMMY_CYCLES,
output wire [3:0] AHB_QSPI_N_RW_BYTES,
output reg [21:0] AHB_QSPI_ADDR,
output wire [127:0] AHB_QSPI_WDATA,
@@ -37,10 +37,7 @@ module ahb_qspi_interface #(
);
-assign HRESP = 1'b0;
-assign AHB_QSPI_CMD = 8'h0B;
assign AHB_QSPI_ADDR_EN = 1'b1;
-assign AHB_QSPI_DUMMY_CYCLES = 4'h4;
assign AHB_QSPI_READ=1'b1;
assign AHB_QSPI_WRITE=1'b0;
assign AHB_QSPI_WDATA = HWDATA;
@@ -55,7 +52,7 @@ wire [31:0] AHB_QSPI_RDATA_W3 = {AHB_QSPI_RDATA[103:96],AHB_QSPI_RDATA[111:104],
wire [127:0] AHB_QSPI_RDATA_i = {AHB_QSPI_RDATA_W3,AHB_QSPI_RDATA_W0, AHB_QSPI_RDATA_W1, AHB_QSPI_RDATA_W2};
// AHB FSM
-enum {IDLE, WAIT_READ, WAIT_WRITE, WRITE, READ} current_state, next_state;
+enum {IDLE, WAIT_READ, ERR} current_state, next_state;
// AHB lite last regs
reg last_HSEL;
@@ -68,7 +65,8 @@ reg [2:0] last_HSIZE;
reg qspi_ready;
reg qspi_started;
-assign HREADYOUT = (current_state==IDLE && last_HTRANS==2'b00) ? 1'b1: qspi_ready; //(current_state==IDLE)? 1'b1 : qspi_ready;
+assign HREADYOUT = ((current_state==IDLE && last_HTRANS==2'b00)||(current_state==ERR)) ? 1'b1: qspi_ready; //(current_state==IDLE)? 1'b1 : qspi_ready;
+assign HRESP = (current_state == ERR) ? 1'b1 : 1'b0;
always @(posedge HCLK or negedge HRESETn) begin
if(~HRESETn) begin
@@ -96,22 +94,17 @@ always_comb begin
case(current_state)
IDLE: if(HTRANS==2'b00)
next_state = IDLE;
- else if(HSELx & HWRITE & ~qspi_ready) begin
- next_state = WAIT_WRITE;
- end
- else if(HSELx & ~qspi_ready) begin
+ else if(HSELx && HTRANS==2'b10 && ~XIP_ACTIVE)
+ next_state = ERR;
+ else if(HSELx & HWRITE)
+ next_state = ERR;
+ else if(HSELx && HTRANS==2'b10)
next_state = WAIT_READ;
- end
- WAIT_WRITE: if(qspi_ready)
- next_state = WRITE;
- else
- next_state = WAIT_WRITE;
+ ERR: next_state = IDLE;
WAIT_READ: if(qspi_ready)
- next_state = READ;
+ next_state = IDLE;
else
next_state = WAIT_READ;
- READ: next_state = IDLE;
- WRITE: next_state = IDLE;
default: next_state = IDLE;
endcase
end
@@ -138,7 +131,7 @@ always @(posedge HCLK or negedge HRESETn) begin
qspi_ready <= 1'b1;
end
end
- end else begin
+ end else begin
qspi_started <= 1'b0;
qspi_ready <=1'b0;
AHB_QSPI_ADDR <= {HADDR[ADDR_W-1:4],4'b0000};
diff --git a/logical/apb_qspi_regs/logical/apb_qspi_regs.v b/logical/apb_qspi_regs/logical/apb_qspi_regs.v
index edb6383c6d0dd56914391bcef14cc90cc128996c..dff332e22e293be7908d65e2348ad92293199177 100644
--- a/logical/apb_qspi_regs/logical/apb_qspi_regs.v
+++ b/logical/apb_qspi_regs/logical/apb_qspi_regs.v
@@ -30,7 +30,13 @@ module apb_qspi_regs(
output wire XIP_ACTIVE,
output wire QSPI_CONT_READ,
output wire [7:0] QSPI_MODE_CODE,
- output wire QSPI_NO_CMD
+ output wire QSPI_NO_CMD,
+
+ output wire [7:0] QSPI_CLK_DIV,
+
+ // AHB Control Signals
+ output wire [7:0] AHB_QSPI_CMD,
+ output wire [3:0] AHB_QSPI_DUMMY_CYCLES
);
// Registers
// reg0 Control 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
@@ -55,6 +61,25 @@ module apb_qspi_regs(
// QSPI_ADDR [21:0] |<-------------------------------------------------->|-> QSPI_ADDR [21:0]
+// reg12 AHB SPI setup 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+// reg12 SPI Commands 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+// AHN_QSPI_CMD [7:0] | | | | | | | | | |----> QSPI_CMD [7:0]
+// AHB_QSPI_DUMMY_CYCLES[15:12] | | | |<------>|-------> QSPI_DUMMY_CYCLES [15:12]
+
+// reg13 QSPI_clk_div [7:0]
+
+localparam [7:0] PIDR0 = 8'h59;
+localparam [7:0] PIDR1 = 8'h16;
+localparam [7:0] PIDR2 = 8'h15;
+localparam [7:0] PIDR3 = 8'h00;
+localparam [7:0] PIDR4 = 8'h00;
+localparam [7:0] PIDR5 = 8'h00;
+localparam [7:0] PIDR6 = 8'h00;
+localparam [7:0] PIDR7 = 8'h00;
+localparam [7:0] CIDR0 = 8'h50;
+localparam [7:0] CIDR1 = 8'h51;
+localparam [7:0] CIDR2 = 8'h4C;
+localparam [7:0] CIDR3 = 8'h53;
reg [31:0] reg0;
reg [31:0] reg1;
@@ -65,6 +90,8 @@ reg [31:0] reg8;
reg [31:0] reg9;
reg [31:0] reg10;
reg [31:0] reg11;
+reg [31:0] reg12;
+reg [7:0] reg13;
assign QSPI_QIO_MODE = reg0[0];
@@ -88,6 +115,11 @@ assign QSPI_WDATA[63:32] = {reg9[27:24],reg9[31:28],reg9[19:16],reg9[23:20],reg
assign QSPI_WDATA[95:64] = {reg10[27:24],reg10[31:28],reg10[19:16],reg10[23:20],reg10[11:8],reg10[15:12],reg10[3:0],reg10[7:4]};
assign QSPI_WDATA[127:96] = {reg11[27:24],reg11[31:28],reg11[19:16],reg11[23:20],reg11[11:8],reg11[15:12],reg11[3:0],reg11[7:4]};
+assign AHB_QSPI_CMD = reg12[7:0];
+assign AHB_QSPI_DUMMY_CYCLES = reg12[15:12];
+
+assign QSPI_CLK_DIV = reg13;
+
always @(posedge PCLK or negedge PRESETn) begin
if(~PRESETn) begin
reg0 = 32'd0;
@@ -98,6 +130,8 @@ always @(posedge PCLK or negedge PRESETn) begin
reg9 = 32'd0;
reg10 = 32'd0;
reg11 = 32'd0;
+ reg12 = 32'd0;
+ reg13 = 8'h01;
end else begin
if(PSEL & PENABLE & PWRITE) begin
case(PADDR)
@@ -109,6 +143,8 @@ always @(posedge PCLK or negedge PRESETn) begin
10'h009: reg9 = PWDATA;
10'h00A: reg10 = PWDATA;
10'h00B: reg11 = PWDATA;
+ 10'h00C: reg12 = PWDATA;
+ 10'h00D: reg13 = PWDATA[7:0];
endcase
end
if(QSPI_ENABLE_ACK)
@@ -117,7 +153,7 @@ always @(posedge PCLK or negedge PRESETn) begin
end
end
-always @(PCLK, PADDR) begin
+always @(PCLK, PADDR, QSPI_RDATA, reg0, reg1, reg2, reg3, reg8, reg9, reg10, reg11, reg12) begin
if(PCLK) begin
case(PADDR)
10'h000: PRDATA = reg0;
@@ -132,6 +168,20 @@ always @(PCLK, PADDR) begin
10'h009: PRDATA = reg9;
10'h00A: PRDATA = reg10;
10'h00B: PRDATA = reg11;
+ 10'h00C: PRDATA = reg12;
+ 10'h00D: PRDATA = {24'd0, reg13};
+ 10'h3F4: PRDATA = {24'd0, PIDR4};
+ 10'h3F5: PRDATA = {24'd0, PIDR5};
+ 10'h3F6: PRDATA = {24'd0, PIDR6};
+ 10'h3F7: PRDATA = {24'd0, PIDR7};
+ 10'h3F8: PRDATA = {24'd0, PIDR0};
+ 10'h3F9: PRDATA = {24'd0, PIDR1};
+ 10'h3FA: PRDATA = {24'd0, PIDR2};
+ 10'h3FB: PRDATA = {24'd0, PIDR3};
+ 10'h3FC: PRDATA = {24'd0, CIDR0};
+ 10'h3FD: PRDATA = {24'd0, CIDR1};
+ 10'h3FE: PRDATA = {24'd0, CIDR2};
+ 10'h3FF: PRDATA = {24'd0, CIDR3};
default: PRDATA = 32'hDEADCAFE;
endcase
end
diff --git a/logical/qspi_controller/logical/qspi_controller.sv b/logical/qspi_controller/logical/qspi_controller.sv
index 46cf8c3e27a59b6aaa5bc4d55f8c73d834bc7b53..6e239ef70d1f59a35e90399db4be3781f2c1076d 100644
--- a/logical/qspi_controller/logical/qspi_controller.sv
+++ b/logical/qspi_controller/logical/qspi_controller.sv
@@ -3,7 +3,8 @@ module qspi_controller (
input wire HCLK,
input wire HRESETn,
- input wire [7:0] QSPI_CLK_DIV,
+ input wire QSPI_SCLK_i,
+
input wire [1:0] QSPI_SPI_MODE, // {CPOL, CPHA}
input wire [7:0] QSPI_CMD,
@@ -31,18 +32,8 @@ module qspi_controller (
);
-wire QSPI_SCLK_i;
reg QSPI_SCLK_e;
-qspi_clock_div u_qspi_clock_div(
- .HCLK(HCLK),
- .HRESETn(HRESETn),
- .QSPI_CLK_DIV(QSPI_CLK_DIV),
- .QSPI_SPI_MODE(QSPI_SPI_MODE),
- .QSPI_SCLK_i(QSPI_SCLK_i)
-);
-
-
assign QSPI_SCLK = (QSPI_SCLK_e==1'b1) ? QSPI_SCLK_i : QSPI_SPI_MODE[1];
typedef enum {IDLE, NO_FETCH, OP, ADDR, MODE, DUMMY, DATA_O, DATA_I} fsm_state_e;
@@ -169,6 +160,8 @@ always_comb begin
end
else if(QSPI_QIO_MODE==1'b0) begin
next_state = IDLE;
+ end else begin
+ next_state = MODE;
end
end
DUMMY: begin
diff --git a/logical/top_ahb_qspi/logical/top_ahb_qspi.v b/logical/top_ahb_qspi/logical/top_ahb_qspi.v
index be3ea393e9bed9ce143118085e01e044f7519901..073c931eaa1b958c9cadfd3e11264205fde37a0b 100644
--- a/logical/top_ahb_qspi/logical/top_ahb_qspi.v
+++ b/logical/top_ahb_qspi/logical/top_ahb_qspi.v
@@ -286,6 +286,8 @@ wire [7:0] QSPI_MODE_CODE;
wire QSPI_NO_CMD;
wire XIP_ACTIVE;
+wire [7:0] QSPI_CLK_DIV;
+
qspi_controller_mux u_qspi_controller_mux(
.XIP_ACTIVE(XIP_ACTIVE),
@@ -360,7 +362,11 @@ apb_qspi_regs u_apb_qspi_regs(
.XIP_ACTIVE(XIP_ACTIVE),
.QSPI_CONT_READ(QSPI_CONT_READ),
.QSPI_MODE_CODE(QSPI_MODE_CODE),
- .QSPI_NO_CMD(QSPI_NO_CMD)
+ .QSPI_NO_CMD(QSPI_NO_CMD),
+
+ .QSPI_CLK_DIV(QSPI_CLK_DIV),
+ .AHB_QSPI_CMD(AHB_QSPI_CMD),
+ .AHB_QSPI_DUMMY_CYCLES(AHB_QSPI_DUMMY_CYCLES)
);
ahb_qspi_interface #(
@@ -381,12 +387,11 @@ ahb_qspi_interface #(
.HREADY(flash_HREADYM),
.HREADYOUT(flash_HREADYOUTM),
.HRESP(flash_HRESPM),
- .AHB_QSPI_CMD(AHB_QSPI_CMD),
+ .XIP_ACTIVE(XIP_ACTIVE),
.AHB_QSPI_ENABLE(AHB_QSPI_ENABLE),
.AHB_QSPI_READ(AHB_QSPI_READ),
.AHB_QSPI_WRITE(AHB_QSPI_WRITE),
.AHB_QSPI_ADDR_EN(AHB_QSPI_ADDR_EN),
- .AHB_QSPI_DUMMY_CYCLES(AHB_QSPI_DUMMY_CYCLES),
.AHB_QSPI_N_RW_BYTES(AHB_QSPI_N_RW_BYTES),
.AHB_QSPI_ADDR(AHB_QSPI_ADDR),
.AHB_QSPI_WDATA(AHB_QSPI_WDATA),
@@ -395,10 +400,21 @@ ahb_qspi_interface #(
.AHB_QSPI_RDATA(AHB_QSPI_RDATA)
);
+wire QSPI_SCLK_i;
+
+qspi_clock_div u_qspi_clock_div(
+ .HCLK(HCLK),
+ .HRESETn(HRESETn),
+ .QSPI_CLK_DIV(QSPI_CLK_DIV),
+ .QSPI_SPI_MODE(2'b00),
+ .QSPI_SCLK_i(QSPI_SCLK_i)
+);
+
+
qspi_controller u_qspi_controller(
.HCLK(HCLK),
.HRESETn(HRESETn),
- .QSPI_CLK_DIV(8'h01),
+ .QSPI_SCLK_i(QSPI_SCLK_i),
.QSPI_SPI_MODE(2'b00),
.QSPI_CMD(QSPI_CMD),
.QSPI_ENABLE(QSPI_ENABLE),
diff --git a/makefile b/makefile
index a874931cbba3ba0ec21a9b9e0fd54991da29b608..f78f8c1d68b31c605115b5306db585551fbe14cc 100644
--- a/makefile
+++ b/makefile
@@ -29,6 +29,7 @@ documentation:
mv ./docs/tex/ahb_qspi.pdf ./docs/ahb_qspi.pdf
get_flash_model:
+ @mkdir -p $(SOCLABS_AHB_QSPI_DIR)/verif/VIP
@cd $(SOCLABS_AHB_QSPI_DIR)/verif/VIP; wget https://ww1.microchip.com/downloads/en/DeviceDoc/SST26VF064B.zip
@cd $(SOCLABS_AHB_QSPI_DIR)/verif/VIP; unzip SST26VF064B.zip
@cd $(SOCLABS_AHB_QSPI_DIR)/verif/VIP; rm SST26VF064B.zip
diff --git a/verif/README.md b/verif/README.md
index 90d5a80782813920d327d697f8c09fd627aac599..c2595668fd6411ac9b05e7ddb9537d0aaf9d0170 100644
--- a/verif/README.md
+++ b/verif/README.md
@@ -38,7 +38,7 @@ Identification
Write
- [x] (0x06) Write Enable
-- [ ] (0x04) Write Disable
+- [x] (0x04) Write Disable
- [ ] (0x20) SE: Erase 4 KBytes of memory array
- [ ] (0xD8) BE: Erase 64, 32, or 8 KBytes of memory array
- [ ] (0xC7) CE: Full chip erase
diff --git a/verif/cocotb/ahb_qspi_tests.py b/verif/cocotb/ahb_qspi_tests.py
index df3878e971c125764c2821712d642c31b108ca79..4e81f93935f4455dcbd1f5bda230d681f53d8f99 100644
--- a/verif/cocotb/ahb_qspi_tests.py
+++ b/verif/cocotb/ahb_qspi_tests.py
@@ -216,15 +216,12 @@ async def QSPI_READ_TESTS(dut):
CACHE_STATUS_tmp = await tb.config_ahb_master.read(CACHE_CONFIG_ADDR+0x04,4)
CACHE_STATUS = int(CACHE_STATUS_tmp[0]['data'],16)
await Timer(time=10, units='us')
- print(CACHE_STATUS)
- print(CACHE_STATUS)
-
-
tb.log.info("Read %d x 16-bytes over AHB (uncached)",n_reads)
start_time_uncached = cocotb.utils.get_sim_time(units='ns')
for i in range(0,n_reads*4):
- data = await tb.data_ahb_master.read(i*4 + base_addr,4)
+ rdata = await tb.data_ahb_master.read(i*4 + base_addr,4)
+ assert int(rdata[0]['data'],16)==data[i%4]
end_time_uncached = cocotb.utils.get_sim_time(units='ns')
dt_uncached = end_time_uncached - start_time_uncached
await Timer(time=10, units='us')
@@ -232,7 +229,8 @@ async def QSPI_READ_TESTS(dut):
tb.log.info("Read 512x 16-bytes over AHB (cached)")
start_time_cached = cocotb.utils.get_sim_time(units='ns')
for i in range(0,n_reads*4):
- data = await tb.data_ahb_master.read(i*4+ base_addr,4)
+ rdata = await tb.data_ahb_master.read(i*4+ base_addr,4)
+ assert int(rdata[0]['data'],16)==data[i%4]
end_time_cached = cocotb.utils.get_sim_time(units='ns')
dt_cached = end_time_cached - start_time_cached
@@ -267,3 +265,16 @@ async def CACHE_CONFIG(dut):
assert int(data[0]['data'],16) == 0x40
data = await tb.config_ahb_master.read(CACHE_CONFIG_ADDR+0x20,4)
print(data)
+
+@cocotb.test()
+async def AHB_BAD_BEHAVIOUR(dut):
+ tb = TB(dut)
+ await tb.cycle_reset()
+
+ tb.log.info("Try write over AHB, expect ERROR")
+ resp = await tb.data_ahb_master.write(0x000,0xCAFECAFE)
+ tb.log.info(resp[0]['resp'])
+
+ tb.log.info("Try read over AHB when in APB mode, expect ERROR")
+ data = await tb.data_ahb_master.read(0x100,4)
+ tb.log.info(data[0]['resp'])
\ No newline at end of file