diff --git a/.gitmodules b/.gitmodules
index b9b9e6772bd93c78bca4435ad5522bf1a6a9a0d1..4ab49125c06bff68c9c4395eea0c4f900f736d1e 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -22,9 +22,6 @@
path = rtl_primitives_tech
url = https://git.soton.ac.uk/soclabs/rtl_primitives_tech.git
branch = main
-[submodule "secworks-aes"]
- path = secworks-aes
- url = https://github.com/secworks/aes.git
[submodule "asic_lib_tech"]
path = asic_lib_tech
url = https://git.soton.ac.uk/soclabs/asic_library_tech
diff --git a/asic_lib_tech b/asic_lib_tech
index 5687e4966986706e13dcc9fe14a7ec741a57a022..ddda4a64c07b133b6d60c539ac403fb6644bb55f 160000
--- a/asic_lib_tech
+++ b/asic_lib_tech
@@ -1 +1 @@
-Subproject commit 5687e4966986706e13dcc9fe14a7ec741a57a022
+Subproject commit ddda4a64c07b133b6d60c539ac403fb6644bb55f
diff --git a/flist/project/system.flist b/flist/project/system.flist
index 1b65e446df1dc10e19004c08dc051247e6a515e7..e7f9758e2798f4cf897bb85b03fd0c5641ddc4f7 100644
--- a/flist/project/system.flist
+++ b/flist/project/system.flist
@@ -29,7 +29,7 @@
-f $(SOCLABS_FPGA_LIB_TECH_DIR)/flist/fpga_lib_mem_ip.flist
// - Accelerator Wrapper IP
-///-f $(SOCLABS_WRAPPER_TECH_DIR)/flist/accelerator_wrapper_ip.flist
+//-f $(SOCLABS_WRAPPER_TECH_DIR)/flist/accelerator_wrapper_ip.flist
// - Bootrom Code RTL
$(SOCLABS_PROJECT_DIR)/system/src/bootrom/verilog/bootrom.v
diff --git a/flist/project/system_ASIC.flist b/flist/project/system_ASIC.flist
index 7330052510779ba01d61b9887040fc5ad192b189..dcd438920c03fda5e9fb5ede2a67ef52786a1016 100644
--- a/flist/project/system_ASIC.flist
+++ b/flist/project/system_ASIC.flist
@@ -22,11 +22,9 @@
// - Primitives IP
-f $(SOCLABS_PRIMITIVES_TECH_DIR)/flist/rtl_primitives_ip.flist
-// - Generic Pad Library
--f $(SOCLABS_GENERIC_LIB_TECH_DIR)/flist/generic_lib_ip.flist
-
-// - FPGA sram
--f $(SOCLABS_ASIC_LIB_TECH_DIR)/flist/asic_lib_mem_ip.flist
+// - ASIC memories and pads
+-f $(SOCLABS_ASIC_LIB_TECH_DIR)/flist/asic_lib_ip.flist
// - Accelerator Wrapper IP
-f $(SOCLABS_WRAPPER_TECH_DIR)/flist/accelerator_wrapper_ip.flist
+
diff --git a/flist/project/top.flist b/flist/project/top.flist
index c87d9bec9506e498c15bfcddee635d3463533e3b..0b24f7c23e3f9d4ba36a066719a7317c788e4481 100644
--- a/flist/project/top.flist
+++ b/flist/project/top.flist
@@ -32,4 +32,8 @@
// - CMSDK IP
-f $(SOCLABS_PROJECT_DIR)/flist/ahb/ahb_ip.flist
--f $(SOCLABS_PROJECT_DIR)/flist/apb/apb_ip.flist
\ No newline at end of file
+-f $(SOCLABS_PROJECT_DIR)/flist/apb/apb_ip.flist
+
+// the chosen DMA controller
+//-f $(SOCLABS_SLDMA350_TECH_DIR)/flist/sldma350_ahb.flist
+-f $(SOCLABS_SLDMA230_TECH_DIR)/flist/sldma230_ip.flist
\ No newline at end of file
diff --git a/flist/project/top_ASIC.flist b/flist/project/top_ASIC.flist
index 7b9d4f993202ca7b3d7298c93a5f7694b8cc7e75..dd1da6ca6c7f922ee1eedad31585c24e5ee0c8a1 100644
--- a/flist/project/top_ASIC.flist
+++ b/flist/project/top_ASIC.flist
@@ -31,4 +31,8 @@
-f $(SOCLABS_PROJECT_DIR)/flist/ahb/ahb_ip.flist
-f $(SOCLABS_PROJECT_DIR)/flist/apb/apb_ip.flist
-$(SOCLABS_PROJECT_DIR)/system/src/defines/gen_defines.v
\ No newline at end of file
+$(SOCLABS_PROJECT_DIR)/system/src/defines/gen_defines.v
+
+// the chosen DMA controller
+-f $(SOCLABS_SLDMA350_TECH_DIR)/flist/sldma350_ahb.flist
+//-f $(SOCLABS_SLDMA230_TECH_DIR)/flist/sldma230_ip.flist
diff --git a/nanosoc_tech b/nanosoc_tech
index f2193c6c86d6e17b94d97f59489415f9aab53947..62a44820d495ed04647627e6fb1b5308f0c3c678 160000
--- a/nanosoc_tech
+++ b/nanosoc_tech
@@ -1 +1 @@
-Subproject commit f2193c6c86d6e17b94d97f59489415f9aab53947
+Subproject commit 62a44820d495ed04647627e6fb1b5308f0c3c678
diff --git a/projbranch b/projbranch
index 1d14a8b18cb92593334ba4e09dfca1ddfada4ac2..38d87897e02b83afbe62429b39fa046a12cb24a6 100644
--- a/projbranch
+++ b/projbranch
@@ -11,7 +11,6 @@
# Each Repo needs to have its branch set manually in here - they will defaultly be checked out to main
# Project Repository Subrepository Branch Index
# Add your Accelerator Repository here
-secworks-aes: master
nanosoc_tech: main
accelerator_wrapper_tech: main
diff --git a/secworks-aes b/secworks-aes
deleted file mode 160000
index b9a3f1965b4e0568f0ca9b2d575ce6ea6fec2f36..0000000000000000000000000000000000000000
--- a/secworks-aes
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit b9a3f1965b4e0568f0ca9b2d575ce6ea6fec2f36
diff --git a/set_env.sh b/set_env.sh
index 392e8cb4ca4dfc3c1d9f43bc15e6991bf00c86d9..2afe7f5ec9a0e5770b7e4abf7e6050e99858f600 100755
--- a/set_env.sh
+++ b/set_env.sh
@@ -16,4 +16,4 @@ if [ ! -f .dma350_configured ]; then
cp nanosoc_tech/nanosoc/sldma350_tech/config/address_map_m1_nanosoc.sv $ARM_IP_LIBRARY_PATH/DMA-350/CG096-r0p0-00rel0/CG096-BU-50000-r0p0-00rel0/dma350/logical/models/modules/generic/address_map_m1_nanosoc.sv
make -C nanosoc_tech/nanosoc/sldma350_tech/ config_dma_ahb
touch .dma350_configured
-fi
\ No newline at end of file
+fi
diff --git a/simulate/socsim/regression_accelerator.sh b/simulate/socsim/regression_accelerator.sh
new file mode 100755
index 0000000000000000000000000000000000000000..737c8ae3ac20a8dadf5f225d81560b2d081223f9
--- /dev/null
+++ b/simulate/socsim/regression_accelerator.sh
@@ -0,0 +1,31 @@
+#-----------------------------------------------------------------------------
+# SoC Labs Simulation script for system level verification
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# David Mapstone (d.a.mapstone@soton.ac.uk)
+#
+# Copyright 2023, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+
+#!/usr/bin/env bash
+
+# Get simulation name from name of script
+SIM_NAME=`basename -s .sh "$0"`
+
+# Directory to put simulation files
+SIM_DIR=$SOCLABS_PROJECT_DIR/simulate/sim/$SIM_NAME
+
+# Create Directory to put simulation files
+mkdir -p $SIM_DIR
+cd $SOCLABS_PROJECT_DIR/simulate/sim/$SIM_NAME
+
+# Compile Simulation
+# Call makefile in NanoSoC Repo with options
+echo ${2}
+make -C $SOCLABS_NANOSOC_TECH_DIR regression_mti \
+ SIM_DIR=$SIM_DIR \
+ ACCELERATOR=yes \
+ ${@:2}
+
diff --git a/simulate/socsim/test_accelerator.sh b/simulate/socsim/test_accelerator.sh
new file mode 100755
index 0000000000000000000000000000000000000000..1bfacd413d1a7326dee7254953312d535c2a755a
--- /dev/null
+++ b/simulate/socsim/test_accelerator.sh
@@ -0,0 +1,31 @@
+#-----------------------------------------------------------------------------
+# SoC Labs Simulation script for system level verification
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# David Mapstone (d.a.mapstone@soton.ac.uk)
+#
+# Copyright 2023, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+
+#!/usr/bin/env bash
+
+# Get simulation name from name of script
+SIM_NAME=`basename -s .sh "$0"`
+
+# Directory to put simulation files
+SIM_DIR=$SOCLABS_PROJECT_DIR/simulate/sim/$SIM_NAME
+
+# Create Directory to put simulation files
+mkdir -p $SIM_DIR
+cd $SOCLABS_PROJECT_DIR/simulate/sim/$SIM_NAME
+
+# Compile Simulation
+# Call makefile in NanoSoC Repo with options
+echo ${2}
+make -C $SOCLABS_NANOSOC_TECH_DIR run_mti \
+ SIM_DIR=$SIM_DIR \
+ ACCELERATOR=yes \
+ ${@:2}
+
diff --git a/soctools_flow b/soctools_flow
index 73a86713b7fb0b98ef3fd59032b6c6326a20041f..1fec0158c729f99888c692dc85696069be8e4006 160000
--- a/soctools_flow
+++ b/soctools_flow
@@ -1 +1 @@
-Subproject commit 73a86713b7fb0b98ef3fd59032b6c6326a20041f
+Subproject commit 1fec0158c729f99888c692dc85696069be8e4006
diff --git a/system/src/accelerator_subsystem.v b/system/src/accelerator_subsystem.v
index 0957c7cbfd9fca47408e9b99607ffa56c68d7794..6e68edad48b81fb3e96af758649229329eaf826c 100644
--- a/system/src/accelerator_subsystem.v
+++ b/system/src/accelerator_subsystem.v
@@ -9,7 +9,6 @@
//
// Copyright (C) 2023; SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
-`include "gen_defines.v"
module accelerator_subsystem #(
parameter SYS_ADDR_W = 32,
@@ -37,35 +36,7 @@ module accelerator_subsystem #(
// Data Request Signal to DMAC
output wire [1:0] EXP_DRQ,
input wire [1:0] EXP_DLAST,
- // DMAC Stream interfaces
-`ifdef DMAC_DMA350
- input wire EXP_STR_IN_0_TVALID,
- output wire EXP_STR_IN_0_TREADY,
- input wire [SYS_DATA_W-1:0] EXP_STR_IN_0_TDATA,
- input wire [15:0] EXP_STR_IN_0_TSTRB,
- input wire EXP_STR_IN_0_TLAST,
-
- output wire EXP_STR_OUT_0_TVALID,
- input wire EXP_STR_OUT_0_TREADY,
- output wire [SYS_DATA_W-1:0] EXP_STR_OUT_0_TDATA,
- output wire [15:0] EXP_STR_OUT_0_TSTRB,
- output wire EXP_STR_OUT_0_TLAST,
- input wire EXP_STR_OUT_0_FLUSH,
-
- input wire EXP_STR_IN_1_TVALID,
- output wire EXP_STR_IN_1_TREADY,
- input wire [SYS_DATA_W-1:0] EXP_STR_IN_1_TDATA,
- input wire [15:0] EXP_STR_IN_1_TSTRB,
- input wire EXP_STR_IN_1_TLAST,
-
- output wire EXP_STR_OUT_1_TVALID,
- input wire EXP_STR_OUT_1_TREADY,
- output wire [SYS_DATA_W-1:0] EXP_STR_OUT_1_TDATA,
- output wire [15:0] EXP_STR_OUT_1_TSTRB,
- output wire EXP_STR_OUT_1_TLAST,
- input wire EXP_STR_OUT_1_FLUSH,
-`endif
-
+
// Interrupts
output wire [IRQ_NUM-1:0] EXP_IRQ
);
diff --git a/system/testcodes/aes128_tests_dma230/aes128_tests_dma230.hex b/system/testcodes/aes128_tests_dma230/aes128_tests_dma230.hex
index 83ddb957e67e16e2be71003d4558afd27ab8913a..e4dca2583571f8ac0bba3fdddbc7c3151136b42f 100644
--- a/system/testcodes/aes128_tests_dma230/aes128_tests_dma230.hex
+++ b/system/testcodes/aes128_tests_dma230/aes128_tests_dma230.hex
@@ -250,12 +250,12 @@ AB
43
18
47
-84
+F4
1B
00
00
-A4
-1B
+14
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00
00
00
@@ -294,8 +294,8 @@ B5
D1
01
F0
-D9
-F9
+11
+FA
10
BD
78
@@ -304,7 +304,7 @@ BD
D1
01
F0
-0A
+42
FA
10
BD
@@ -314,7 +314,7 @@ BD
D1
01
F0
-B2
+EA
FB
10
BD
@@ -332,8 +332,8 @@ B5
BD
01
F0
-EE
-FB
+26
+FC
11
46
FF
@@ -346,7 +346,7 @@ AE
FA
01
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-06
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FC
03
B4
@@ -506,7 +506,7 @@ EC
A0
01
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-11
+49
F9
6D
1C
@@ -552,7 +552,7 @@ EE
A0
01
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-56
+8E
FA
F6
4C
@@ -602,12 +602,12 @@ EE
A0
01
F0
-3D
+75
FA
01
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-D2
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28
46
0E
@@ -674,7 +674,7 @@ EA
48
01
F0
-2F
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FA
E0
69
@@ -704,7 +704,7 @@ E4
48
01
F0
-20
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FA
10
2C
@@ -720,7 +720,7 @@ E0
18
01
F0
-75
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FA
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20
@@ -740,7 +740,7 @@ DC
46
01
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@@ -866,7 +866,7 @@ BD
A0
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A0
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1C
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48
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@@ -1498,8 +1498,8 @@ E0
00
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44
@@ -1642,7 +1642,7 @@ C0
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FE
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@@ -1894,19 +1894,19 @@ CF
A0
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@@ -1998,13 +1998,13 @@ A0
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@@ -2038,7 +2038,7 @@ FC
A0
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@@ -2080,14 +2080,14 @@ F9
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FC
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@@ -3670,12 +3670,12 @@ D1
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6B
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@@ -4174,16 +4174,16 @@ F0
00
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@@ -4490,7 +4490,7 @@ A0
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@@ -4534,7 +4534,7 @@ B5
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@@ -4550,7 +4550,7 @@ A0
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@@ -4570,7 +4570,7 @@ C9
A0
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@@ -4592,7 +4592,7 @@ D0
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@@ -4608,7 +4608,7 @@ FA
A0
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A0
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diff --git a/system/testcodes/aes128_tests_memcpy/aes128_tests_memcpy.hex b/system/testcodes/aes128_tests_memcpy/aes128_tests_memcpy.hex
index 470c6d0046dbcc707fb809b2e7ebc5da006fb877..cc234191d303cae66b4b88f5584c19888b1c9934 100644
--- a/system/testcodes/aes128_tests_memcpy/aes128_tests_memcpy.hex
+++ b/system/testcodes/aes128_tests_memcpy/aes128_tests_memcpy.hex
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