From 2aa2a83d1fa3341f87bd375ade3e927e9c14b177 Mon Sep 17 00:00:00 2001
From: dwf1m12 <d.w.flynn@soton.ac.uk>
Date: Wed, 4 Oct 2023 13:44:35 +0100
Subject: [PATCH] Repair flist files to get aes-128 project building and
 running correctly again

---
 flist/project/accelerator.flist | 6 +++---
 flist/project/system.flist      | 4 ++--
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/flist/project/accelerator.flist b/flist/project/accelerator.flist
index 2166f19..b531759 100644
--- a/flist/project/accelerator.flist
+++ b/flist/project/accelerator.flist
@@ -14,10 +14,10 @@
 // =============    Accelerator Module search path    =============
 
 // ! Point this to your Accelerator RTL
-//+incdir+$(ACCELERATOR_DIR)/src/rtl
++incdir+$(ACCELERATOR_DIR)/src/rtl
 
 // ! Point this to your Wrapper RTL
-///$(SOCLABS_PROJECT_DIR)/wrapper/src/soclabs_ahb_aes128_ctrl.v
+$(SOCLABS_PROJECT_DIR)/wrapper/src/soclabs_ahb_aes128_ctrl.v
 
 // ! Point this to your Subsystem RTL
-///$(SOCLABS_PROJECT_DIR)/system/src/accelerator_subsystem.v
+$(SOCLABS_PROJECT_DIR)/system/src/accelerator_subsystem.v
diff --git a/flist/project/system.flist b/flist/project/system.flist
index d5a2331..9aa3e58 100644
--- a/flist/project/system.flist
+++ b/flist/project/system.flist
@@ -29,7 +29,7 @@
 -f $(SOCLABS_FPGA_LIB_TECH_DIR)/flist/fpga_lib_mem_ip.flist
 
 // - Accelerator Wrapper IP
--f $(SOCLABS_WRAPPER_TECH_DIR)/flist/accelerator_wrapper_ip.flist
+///-f $(SOCLABS_WRAPPER_TECH_DIR)/flist/accelerator_wrapper_ip.flist
 
 // - Bootrom Code RTL
-$(SOCLABS_PROJECT_DIR)/system/src/bootrom/verilog/bootrom.v
\ No newline at end of file
+$(SOCLABS_PROJECT_DIR)/system/src/bootrom/verilog/bootrom.v
-- 
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