diff --git a/flist/project/accelerator.flist b/flist/project/accelerator.flist
index 2166f19484e22e37ea462156c7efa1967fbf7d53..b531759cd136c8d8d4db69280441aae860f011dd 100644
--- a/flist/project/accelerator.flist
+++ b/flist/project/accelerator.flist
@@ -14,10 +14,10 @@
 // =============    Accelerator Module search path    =============
 
 // ! Point this to your Accelerator RTL
-//+incdir+$(ACCELERATOR_DIR)/src/rtl
++incdir+$(ACCELERATOR_DIR)/src/rtl
 
 // ! Point this to your Wrapper RTL
-///$(SOCLABS_PROJECT_DIR)/wrapper/src/soclabs_ahb_aes128_ctrl.v
+$(SOCLABS_PROJECT_DIR)/wrapper/src/soclabs_ahb_aes128_ctrl.v
 
 // ! Point this to your Subsystem RTL
-///$(SOCLABS_PROJECT_DIR)/system/src/accelerator_subsystem.v
+$(SOCLABS_PROJECT_DIR)/system/src/accelerator_subsystem.v
diff --git a/flist/project/system.flist b/flist/project/system.flist
index d5a2331282074eec794511815c9fdb51b3ac9ca6..9aa3e584bac1399bec4529640fec2c6f5d59901b 100644
--- a/flist/project/system.flist
+++ b/flist/project/system.flist
@@ -29,7 +29,7 @@
 -f $(SOCLABS_FPGA_LIB_TECH_DIR)/flist/fpga_lib_mem_ip.flist
 
 // - Accelerator Wrapper IP
--f $(SOCLABS_WRAPPER_TECH_DIR)/flist/accelerator_wrapper_ip.flist
+///-f $(SOCLABS_WRAPPER_TECH_DIR)/flist/accelerator_wrapper_ip.flist
 
 // - Bootrom Code RTL
-$(SOCLABS_PROJECT_DIR)/system/src/bootrom/verilog/bootrom.v
\ No newline at end of file
+$(SOCLABS_PROJECT_DIR)/system/src/bootrom/verilog/bootrom.v