From f64ea90c64c16285815437f7a6068aff2b834c09 Mon Sep 17 00:00:00 2001 From: David Mapstone <david@mapstone.me> Date: Tue, 21 Feb 2023 17:38:53 +0000 Subject: [PATCH] Modified stimgen to end simulation. Updated testbench files to finish simulaiton instead of stop --- flow/stimgen.py | 1 + hdl/verif/cmsdk_ahb_filereadcore.v | 4 ++-- hdl/verif/tb_wrapper_top.sv | 4 ++-- simulate/stimulus/ahb_input_hash_stim.fri | 3 ++- simulate/stimulus/ahb_input_hash_stim.m2d | 1 + 5 files changed, 8 insertions(+), 5 deletions(-) diff --git a/flow/stimgen.py b/flow/stimgen.py index 9cf26c3..b8cc6ea 100644 --- a/flow/stimgen.py +++ b/flow/stimgen.py @@ -54,6 +54,7 @@ def fri_output(out_file, word_list): with open(out_file, "w", encoding="UTF8", newline='') as f: f.write(soclabs_header + "\n;") f.write(table_str) + f.write("\nQ") # Add End of Simulation Flag def stimulus_generation(in_file, start_address, size): """ diff --git a/hdl/verif/cmsdk_ahb_filereadcore.v b/hdl/verif/cmsdk_ahb_filereadcore.v index ca4bc71..3ea41e0 100644 --- a/hdl/verif/cmsdk_ahb_filereadcore.v +++ b/hdl/verif/cmsdk_ahb_filereadcore.v @@ -889,8 +889,8 @@ module cmsdk_ahb_filereadcore #( // if simulation ended by Quit command then halt simulation if ( cmd_reg ===`ARM_FRBM_CMD_QUIT ) begin - $display (" Simulation halted."); - $stop; + $display (" Simulation Ended."); + $finish; end end // if begin end // always begin diff --git a/hdl/verif/tb_wrapper_top.sv b/hdl/verif/tb_wrapper_top.sv index f66d282..8c4c945 100644 --- a/hdl/verif/tb_wrapper_top.sv +++ b/hdl/verif/tb_wrapper_top.sv @@ -116,11 +116,11 @@ always //******************************************************************************** // Address decoder, need to be changed for other configuration //******************************************************************************** -// 0x10000000 - 0x10000FFF : HSEL #0 - Hash Accelerator +// 0x60010000 - 0x60010FFF : HSEL #0 - Hash Accelerator // 0x11000000 - 0x11000FFF : HSEL #1 - SRAM // Other addresses : HSEL #2 - Default slave - assign hsel0 = (haddr[31:20] == 20'h600)? 1'b1:1'b0; + assign hsel0 = (haddr[31:12] == 20'h60010)? 1'b1:1'b0; assign hsel1 = (haddr[31:12] == 20'h11000)? 1'b1:1'b0; assign hsel2 = (hsel0|hsel1)? 1'b0:1'b1; diff --git a/simulate/stimulus/ahb_input_hash_stim.fri b/simulate/stimulus/ahb_input_hash_stim.fri index 650357d..00d4de1 100644 --- a/simulate/stimulus/ahb_input_hash_stim.fri +++ b/simulate/stimulus/ahb_input_hash_stim.fri @@ -857,4 +857,5 @@ W 0x600107ec 0x903c2743 word W 0x600107f0 0xff5d4bb0 word W 0x600107f4 0xa1da47c5 word W 0x600107f8 0xc8285c6e word -W 0x600107fc 0xcfe0cd25 word \ No newline at end of file +W 0x600107fc 0xcfe0cd25 word +Q \ No newline at end of file diff --git a/simulate/stimulus/ahb_input_hash_stim.m2d b/simulate/stimulus/ahb_input_hash_stim.m2d index 49cae3c..b6f7c67 100644 --- a/simulate/stimulus/ahb_input_hash_stim.m2d +++ b/simulate/stimulus/ahb_input_hash_stim.m2d @@ -4243,3 +4243,4 @@ c8285c6e cfe0cd25 00000000 +80000001 -- GitLab