diff --git a/flow/stimgen.py b/flow/stimgen.py
index 9cf26c3cd33813b83481779b757696e55c8ae7d9..b8cc6ea538b999b12852adb871ea07162c0a63d9 100644
--- a/flow/stimgen.py
+++ b/flow/stimgen.py
@@ -54,6 +54,7 @@ def fri_output(out_file, word_list):
     with open(out_file, "w", encoding="UTF8", newline='') as f:
         f.write(soclabs_header + "\n;")
         f.write(table_str)
+        f.write("\nQ") # Add End of Simulation Flag
 
 def stimulus_generation(in_file, start_address, size):
     """ 
diff --git a/hdl/verif/cmsdk_ahb_filereadcore.v b/hdl/verif/cmsdk_ahb_filereadcore.v
index ca4bc715b61f3023a287105cd930a55ab2d377c3..3ea41e09babb8f0eff547077f1d7afffaec07df6 100644
--- a/hdl/verif/cmsdk_ahb_filereadcore.v
+++ b/hdl/verif/cmsdk_ahb_filereadcore.v
@@ -889,8 +889,8 @@ module cmsdk_ahb_filereadcore #(
           // if simulation ended by Quit command then halt simulation
           if  ( cmd_reg ===`ARM_FRBM_CMD_QUIT )
             begin
-              $display (" Simulation halted.");
-              $stop;
+              $display (" Simulation Ended.");
+              $finish;
             end
         end // if begin
     end  // always begin
diff --git a/hdl/verif/tb_wrapper_top.sv b/hdl/verif/tb_wrapper_top.sv
index f66d2825c98113f14862c349625679cc384dc9ee..8c4c945cc3bce16ef62dd7b4ebc86724b2e05346 100644
--- a/hdl/verif/tb_wrapper_top.sv
+++ b/hdl/verif/tb_wrapper_top.sv
@@ -116,11 +116,11 @@ always
 //********************************************************************************
 // Address decoder, need to be changed for other configuration
 //********************************************************************************
-// 0x10000000 - 0x10000FFF : HSEL #0 - Hash Accelerator
+// 0x60010000 - 0x60010FFF : HSEL #0 - Hash Accelerator
 // 0x11000000 - 0x11000FFF : HSEL #1 - SRAM
 // Other addresses         : HSEL #2 - Default slave
 
-  assign hsel0 = (haddr[31:20] == 20'h600)? 1'b1:1'b0;
+  assign hsel0 = (haddr[31:12] == 20'h60010)? 1'b1:1'b0;
   assign hsel1 = (haddr[31:12] == 20'h11000)? 1'b1:1'b0;
   assign hsel2 = (hsel0|hsel1)? 1'b0:1'b1;
 
diff --git a/simulate/stimulus/ahb_input_hash_stim.fri b/simulate/stimulus/ahb_input_hash_stim.fri
index 650357d2e1c2e2768cf65502d0bac0fc7203df99..00d4de12c81f159c6858a46e9fa262de79a99b32 100644
--- a/simulate/stimulus/ahb_input_hash_stim.fri
+++ b/simulate/stimulus/ahb_input_hash_stim.fri
@@ -857,4 +857,5 @@ W              0x600107ec  0x903c2743  word
 W              0x600107f0  0xff5d4bb0  word
 W              0x600107f4  0xa1da47c5  word
 W              0x600107f8  0xc8285c6e  word
-W              0x600107fc  0xcfe0cd25  word
\ No newline at end of file
+W              0x600107fc  0xcfe0cd25  word
+Q
\ No newline at end of file
diff --git a/simulate/stimulus/ahb_input_hash_stim.m2d b/simulate/stimulus/ahb_input_hash_stim.m2d
index 49cae3c55ae48c3755e676b2c9e4ecd9544b39bb..b6f7c673fa1790ae64d12f4cc5c07a653b3d7d01 100644
--- a/simulate/stimulus/ahb_input_hash_stim.m2d
+++ b/simulate/stimulus/ahb_input_hash_stim.m2d
@@ -4243,3 +4243,4 @@ c8285c6e
 cfe0cd25
 00000000
 
+80000001