From f33876352d5d872d599cea73360287a86e99b6ab Mon Sep 17 00:00:00 2001
From: David Mapstone <david@mapstone.me>
Date: Wed, 15 Mar 2023 15:51:25 +0000
Subject: [PATCH] SOC1-141: Updated Filelists to work with Icarus Verilog and
changed accelerator environment variable name
---
flist/accelerator-wrapper_src.flist | 13 +++++++------
flow/simulators/ivlog_sim.sh | 2 +-
flow/stimgen.py | 4 ++--
hdl/src/wrapper_sha256_hashing_stream.sv | 4 ----
4 files changed, 10 insertions(+), 13 deletions(-)
diff --git a/flist/accelerator-wrapper_src.flist b/flist/accelerator-wrapper_src.flist
index 1ab862a..813546e 100644
--- a/flist/accelerator-wrapper_src.flist
+++ b/flist/accelerator-wrapper_src.flist
@@ -16,10 +16,11 @@
+libext+.v+.vlib
// ============= Accelerator Module search path =============
--y $DESIGN/accelerator-wrapper/hdl/src/
-+incdir+$DESIGN/accelerator-wrapper/hdl/src/
+-y $(WRAP_ACC_DIR)/hdl/src/
++incdir+$(WRAP_ACC_DIR)/hdl/src/
-$DESIGN/accelerator-wrapper/hdl/src/wrapper_ahb_interface.sv
-$DESIGN/accelerator-wrapper/hdl/src/wrapper_packet_construct.sv
-$DESIGN/accelerator-wrapper/hdl/src/wrapper_packet_deconstruct.sv
-$DESIGN/accelerator-wrapper/hdl/src/wrapper_sha256_hashing_stream.sv
\ No newline at end of file
+$(WRAP_ACC_DIR)/hdl/src/wrapper_ahb_reg_interface.sv
+$(WRAP_ACC_DIR)/hdl/src/wrapper_ahb_to_vr_interface.sv
+$(WRAP_ACC_DIR)/hdl/src/wrapper_packet_construct.sv
+$(WRAP_ACC_DIR)/hdl/src/wrapper_packet_deconstruct.sv
+$(WRAP_ACC_DIR)/hdl/src/wrapper_sha256_hashing_stream.sv
\ No newline at end of file
diff --git a/flow/simulators/ivlog_sim.sh b/flow/simulators/ivlog_sim.sh
index a956e4d..48dbfcd 100755
--- a/flow/simulators/ivlog_sim.sh
+++ b/flow/simulators/ivlog_sim.sh
@@ -12,5 +12,5 @@
#!/usr/bin/env bash
mkdir -p $SOC_TOP/simulate/sim/
-iverilog -I $SOC_TOP/hdl/verif/ -I $SOC_TOP/hdl/verif/submodules -I $SOC_TOP/hdl/src/ -I $SHA_2_ACC_DIR/hdl/src/ -g2012 -o $SOC_TOP/simulate/sim/$1.vvp $SOC_TOP/hdl/verif/tb_$1.sv
+iverilog -c $WRAP_ACC_DIR/flist/*.flist -c $ACC_ENGINE_DIR/flist/*.flist -I $SOC_TOP/hdl/verif/ -I $SOC_TOP/hdl/verif/submodules -I $SOC_TOP/hdl/src/ -I $ACC_ENGINE_DIR/hdl/src/ -g2012 -o $SOC_TOP/simulate/sim/$1.vvp $SOC_TOP/hdl/verif/tb_$1.sv
cd $SOC_TOP/simulate/sim/ && vvp $1.vvp $2
\ No newline at end of file
diff --git a/flow/stimgen.py b/flow/stimgen.py
index 2201b73..5e3c556 100644
--- a/flow/stimgen.py
+++ b/flow/stimgen.py
@@ -205,6 +205,6 @@ if __name__ == "__main__":
accelerator_input_size = 0x0000_0800
accelerator_output_address = 0x6001_0800
accelerator_output_size = 0x0000_0800
- stim_file = os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/system/" + "input_data_32bit_stim.csv"
- ref_file = os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/system/" + "output_hash_32bit_ref.csv"
+ stim_file = os.environ["ACC_ENGINE_DIR"] + "/simulate/stimulus/system/" + "input_data_32bit_stim.csv"
+ ref_file = os.environ["ACC_ENGINE_DIR"] + "/simulate/stimulus/system/" + "output_hash_32bit_ref.csv"
stimulus_generation(stim_file, ref_file, accelerator_input_address, accelerator_input_size, accelerator_output_address, accelerator_output_size)
\ No newline at end of file
diff --git a/hdl/src/wrapper_sha256_hashing_stream.sv b/hdl/src/wrapper_sha256_hashing_stream.sv
index ae9fa89..81ff2a9 100644
--- a/hdl/src/wrapper_sha256_hashing_stream.sv
+++ b/hdl/src/wrapper_sha256_hashing_stream.sv
@@ -35,10 +35,6 @@
// each register can be accessed by byte, half word or word.
// The example slave always output ready and OKAY response to the master
//-----------------------------------------------------------------------------
-// `include "wrapper_packet_construct.sv"
-// `include "wrapper_packet_deconstruct.sv"
-// `include "wrapper_ahb_interface.sv"
-// `include "sha256_hashing_stream.sv"
module wrapper_sha256_hashing_stream #(
parameter ADDRWIDTH=12
--
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