diff --git a/hdl/src/wrapper_ahb_deconstruct.sv b/hdl/src/wrapper_packet_construct.sv
similarity index 87%
rename from hdl/src/wrapper_ahb_deconstruct.sv
rename to hdl/src/wrapper_packet_construct.sv
index e46ecc957eb6e506088a8acd08617a1fd22b83ce..97e00594ec584a4f979c90b3dc633b35632d8db9 100644
--- a/hdl/src/wrapper_ahb_deconstruct.sv
+++ b/hdl/src/wrapper_packet_construct.sv
@@ -1,4 +1,15 @@
-module wrapper_ahb_deconstruct #(
+//-----------------------------------------------------------------------------
+// SoC Labs Wrapper Files
+// - Accelerator Packet Construction from AHB Write Transactions
+// A joint work commissioned on behalf of SoC Labs; under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright 2023; SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+module wrapper_packet_construct #(
parameter ADDRWIDTH=11,
parameter PACKETWIDTH=512
)(
@@ -70,8 +81,6 @@ always_ff @(posedge hclk or negedge hresetn) begin
// Reset Construction Buffer
const_buffer <= 512'd0;
end
- end else begin
- // TODO: Implement Error Propogation/Waitstates
end
end
end
diff --git a/hdl/src/wrapper_packet_deconstruct.sv b/hdl/src/wrapper_packet_deconstruct.sv
new file mode 100644
index 0000000000000000000000000000000000000000..438a9ed925eb9b58a171da49b76e5a7a30a208cc
--- /dev/null
+++ b/hdl/src/wrapper_packet_deconstruct.sv
@@ -0,0 +1,112 @@
+//-----------------------------------------------------------------------------
+// SoC Labs Wrapper Files
+// - Accelerator Packet Deconstruction from AHB Read Transactions
+// A joint work commissioned on behalf of SoC Labs; under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright 2023; SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+module wrapper_packet_deconstruct #(
+ parameter ADDRWIDTH=11,
+ parameter PACKETWIDTH=256
+)(
+ input logic hclk, // clock
+ input logic hresetn, // reset
+
+ //Register interface
+ input logic [ADDRWIDTH-1:0] addr,
+ input logic read_en,
+ input logic write_en,
+ input logic [3:0] byte_strobe,
+ input logic [31:0] wdata,
+ output logic [31:0] rdata,
+ output logic wready,
+ output logic rready,
+
+ // Valid/Ready interface
+ input logic [PACKETWIDTH-1:0] data_in,
+ input logic data_in_last,
+ input logic data_in_valid,
+ output logic data_in_ready
+);
+
+// Create Deconstruction Buffer
+// logic [PACKETWIDTH-1:0] deconst_buffer;
+logic [(PACKETWIDTH/32)-1:0][31:0] deconst_buf;
+
+// Create Array to Flag which buffers have been read
+logic [(PACKETWIDTH/32)-1:0] deconst_buf_flag;
+
+// Curent Buffer Flag
+logic [(PACKETWIDTH/32)-1:0] cur_deconst_buf_flag;
+assign cur_deconst_buf_flag = 1'b1 << buf_word_sel;
+
+// Check All Flags are High
+logic deconst_buf_flag_reduced;
+assign deconst_buf_flag_reduced = &(deconst_buf_flag | (cur_deconst_buf_flag));
+
+// Select which word in buffer to read
+logic [$clog2(PACKETWIDTH/32)-1:0] buf_word_sel;
+assign buf_word_sel = addr[4:2];
+
+logic deconst_buf_valid;
+// Dump data on one of two conditions
+// - An address ends [5:0] in 0x3C i.e. [5:2] == 0xF
+// - Address Moved to different 512 bit word
+// Write Condition
+always_ff @(posedge hclk or negedge hresetn) begin
+ if (~hresetn) begin
+ // Reset Construction Buffer
+ deconst_buf <= {PACKETWIDTH{1'b0}};
+ // Reset Values
+ data_in_ready <= 1'b0;
+ deconst_buf_valid <= 1'b0;
+ deconst_buf_flag <= {(PACKETWIDTH/32){1'b0}};
+ end else begin
+ // If ready is low and theres no valid data in buffer, asser ready
+ if (!data_in_ready && !deconst_buf_valid) begin
+ data_in_ready <= 1'b1;
+ end
+ // Read Packet into Deconstruction Buffer
+ if (data_in_valid && data_in_ready) begin
+ data_in_ready <= 1'b0;
+ deconst_buf <= data_in;
+ deconst_buf_valid <= 1'b1;
+ deconst_buf_flag <= {(PACKETWIDTH/32){1'b0}};
+ end
+ if (read_en) begin
+ // Register which words in the Deconstruction buffer have been read
+ // Check if All Words have been Read
+ if (deconst_buf_flag_reduced && !(data_in_valid && data_in_ready)) begin
+ // Set Ready High To Get more Data into Buffer
+ deconst_buf_valid <= 1'b0;
+ data_in_ready <= 1'b1;
+ end else begin
+ deconst_buf_flag <= deconst_buf_flag | cur_deconst_buf_flag;
+ end
+ end
+ end
+end
+
+// Read Condition
+always_comb begin
+ if (read_en) begin
+ // Read appropriate 32 bits from buffer - wrapping behaviour
+ rdata = deconst_buf[buf_word_sel];
+ end else begin
+ rdata = 32'd0;
+ end
+end
+
+// Register Ready Control
+always_comb begin
+ // Not Ready Out when waiting for Valid Data on Input
+ rready = ~data_in_ready;
+ // Write Ready always high but doesn't do anywthing
+ wready = 1'b1;
+end
+
+endmodule
\ No newline at end of file
diff --git a/hdl/src/wrapper_top.sv b/hdl/src/wrapper_top.sv
index 49b4b261bdff2f2968054ad4ccb8be1c903d7e8c..81fd1f7b38fbf357b967bbe3e517c9f14d0bb5ff 100644
--- a/hdl/src/wrapper_top.sv
+++ b/hdl/src/wrapper_top.sv
@@ -1,5 +1,5 @@
//-----------------------------------------------------------------------------
-// SoC Labs Basic Top-level AHB Wrapper
+// SoC Labs Basic Top-level Accelerator Wrapper
// A joint work commissioned on behalf of SoC Labs; under Arm Academic Access license.
//
// Contributors
@@ -36,7 +36,8 @@
// The example slave always output ready and OKAY response to the master
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
-`include "wrapper_ahb_deconstruct.sv"
+`include "wrapper_packet_construct.sv"
+`include "wrapper_packet_deconstruct.sv"
`include "wrapper_ahb_interface.sv"
module wrapper_top #(
@@ -92,11 +93,22 @@ module wrapper_top #(
logic output_rready;
// Internal Wiring
- logic [511:0] data_out;
- logic data_out_last;
- logic data_out_valid;
- logic data_out_ready;
+ logic [511:0] packet_data_out;
+ logic packet_data_out_last;
+ logic packet_data_out_valid;
+ logic packet_data_out_ready;
+ // Internal Wiring
+ logic [511:0] packet_data_in;
+ logic packet_data_in_last;
+ logic packet_data_in_valid;
+ logic packet_data_in_ready;
+
+ // Test Wire Assignments
+ assign packet_data_in = packet_data_out;
+ assign packet_data_in_last = packet_data_out_last;
+ assign packet_data_in_valid = packet_data_out_valid;
+ assign packet_data_out_ready = packet_data_in_ready;
//-----------------------------------------------------------
// Module logic start
//----------------------------------------------------------
@@ -143,27 +155,52 @@ module wrapper_top #(
.output_rready (output_rready)
);
- wrapper_ahb_deconstruct
- #(ADDRWIDTH-1) // Only half address map allocated to this device
- u_wrapper_ahb_deconstruct (
- .hclk (HCLK),
- .hresetn (HRESETn),
-
- // Register interface
- .addr (input_addr),
- .read_en (input_read_en),
- .write_en (input_write_en),
- .byte_strobe (input_byte_strobe),
- .wdata (input_wdata),
- .rdata (input_rdata),
- .wready (input_wready),
- .rready (input_rready),
-
- // Valid/Ready Interface
- .data_out (data_out),
- .data_out_last (data_out_last),
- .data_out_valid (data_out_valid),
- .data_out_ready (data_out_ready)
+ wrapper_packet_construct #(
+ (ADDRWIDTH - 1), // Only half address map allocated to this device
+ 512 // Packet Width
+ ) u_wrapper_packet_construct (
+ .hclk (HCLK),
+ .hresetn (HRESETn),
+
+ // Register interface
+ .addr (input_addr),
+ .read_en (input_read_en),
+ .write_en (input_write_en),
+ .byte_strobe (input_byte_strobe),
+ .wdata (input_wdata),
+ .rdata (input_rdata),
+ .wready (input_wready),
+ .rready (input_rready),
+
+ // Valid/Ready Interface
+ .data_out (packet_data_out),
+ .data_out_last (packet_data_out_last),
+ .data_out_valid (packet_data_out_valid),
+ .data_out_ready (packet_data_out_ready)
+ );
+
+ wrapper_packet_deconstruct #(
+ (ADDRWIDTH - 1), // Only half address map allocated to this device
+ 512 // Ouptut Packet WIdth
+ ) u_wrapper_packet_deconstruct (
+ .hclk (HCLK),
+ .hresetn (HRESETn),
+
+ // Register interface
+ .addr (output_addr),
+ .read_en (output_read_en),
+ .write_en (output_write_en),
+ .byte_strobe (output_byte_strobe),
+ .wdata (output_wdata),
+ .rdata (output_rdata),
+ .wready (output_wready),
+ .rready (output_rready),
+
+ // Valid/Ready Interface
+ .data_in (packet_data_in),
+ .data_in_last (packet_data_in_last),
+ .data_in_valid (packet_data_in_valid),
+ .data_in_ready (packet_data_in_ready)
);
//-----------------------------------------------------------
@@ -173,9 +210,11 @@ module wrapper_top #(
//---------------------
//Test Logic
//---------------------
- assign data_out_ready = 1'b1;
- assign output_wready = 1'b1;
- assign output_rready = 1'b1;
+ // assign data_out_ready = 1'b1;
+ // assign output_wready = 1'b1;
+ // assign output_rready = 1'b1;
+ // assign output_wready = 1'b1;
+ // assign output_rready = 1'b1;
`ifdef ARM_AHB_ASSERT_ON
`include "std_ovl_defines.h"
diff --git a/hdl/verif/tb_wrapper_top.sv b/hdl/verif/tb_wrapper_top.sv
index 8c4c945cc3bce16ef62dd7b4ebc86724b2e05346..1d535499c8fe71017f62ff4ea7edfdefedf05a8c 100644
--- a/hdl/verif/tb_wrapper_top.sv
+++ b/hdl/verif/tb_wrapper_top.sv
@@ -39,7 +39,6 @@
`include "cmsdk_ahb_fileread_funnel.v"
`include "cmsdk_ahb_fileread_master32.v"
`include "cmsdk_ahb_default_slave.v"
-`include "cmsdk_ahb_ram_beh.v"
`include "cmsdk_ahb_slave_mux.v"
`include "wrapper_top.sv"
@@ -74,22 +73,18 @@ wire hmastlock;
wire [31:0] haddr;
wire [31:0] hwdata;
-// AHB Multiplexor signals, currently 3 slaves : example AHB slave, SRAM and default slave
+// Accelerator AHB Signals
wire hsel0;
wire hreadyout0;
wire hresp0;
wire [31:0] hrdata0;
+// Default Slave AHB Signals
wire hsel1;
wire hreadyout1;
wire hresp1;
wire [31:0] hrdata1;
-wire hsel2;
-wire hreadyout2;
-wire hresp2;
-wire [31:0] hrdata2;
-
reg HCLK;
reg HRESETn;
@@ -117,12 +112,10 @@ always
// Address decoder, need to be changed for other configuration
//********************************************************************************
// 0x60010000 - 0x60010FFF : HSEL #0 - Hash Accelerator
-// 0x11000000 - 0x11000FFF : HSEL #1 - SRAM
-// Other addresses : HSEL #2 - Default slave
+// Other addresses : HSEL #1 - Default slave
assign hsel0 = (haddr[31:12] == 20'h60010)? 1'b1:1'b0;
- assign hsel1 = (haddr[31:12] == 20'h11000)? 1'b1:1'b0;
- assign hsel2 = (hsel0|hsel1)? 1'b0:1'b1;
+ assign hsel1 = hsel0 ? 1'b0:1'b1;
//********************************************************************************
// File read bus master:
@@ -186,10 +179,10 @@ cmsdk_ahb_fileread_master32 #(InputFileName,
.HREADYOUT1 (hreadyout1),
.HRESP1 (hresp1),
.HRDATA1 (hrdata1),
- .HSEL2 (hsel2), // Input Port 2
- .HREADYOUT2 (hreadyout2),
- .HRESP2 (hresp2),
- .HRDATA2 (hrdata2),
+ .HSEL2 (1'b0), // Input Port 2
+ .HREADYOUT2 (),
+ .HRESP2 (),
+ .HRDATA2 (),
.HSEL3 (1'b0), // Input Port 3
.HREADYOUT3 (),
.HRESP3 (),
@@ -248,46 +241,20 @@ cmsdk_ahb_fileread_master32 #(InputFileName,
);
-//********************************************************************************
-// Slave module 2: Behaviour AHB SRAM slave module
-//********************************************************************************
-
- // Behavioral SRAM model
- cmsdk_ahb_ram_beh
- #(20, //AW
- "", //filename
- 5, //WS_N // First access wait state
- 5 //WS_S // Subsequent access wait state
- ) u_ahb_ram_beh (
- .HCLK (HCLK),
- .HRESETn (HRESETn),
- .HSEL (hsel1), // AHB inputs
- .HADDR (haddr[19:0]),
- .HTRANS (htrans),
- .HSIZE (hsize),
- .HWRITE (hwrite),
- .HWDATA (hwdata),
- .HREADY (hready),
-
- .HREADYOUT (hreadyout1), // Outputs
- .HRDATA (hrdata1),
- .HRESP (hresp1)
- );
-
//********************************************************************************
-// Slave module 3: AHB default slave module
+// Slave module 2: AHB default slave module
//********************************************************************************
cmsdk_ahb_default_slave u_ahb_default_slave(
.HCLK (HCLK),
.HRESETn (HRESETn),
- .HSEL (hsel2),
+ .HSEL (hsel1),
.HTRANS (htrans),
.HREADY (hready),
- .HREADYOUT (hreadyout2),
- .HRESP (hresp2)
+ .HREADYOUT (hreadyout1),
+ .HRESP (hresp1)
);
- assign hrdata2 = {32{1'b0}}; // Default slave don't have data
+ assign hrdata1 = {32{1'b0}}; // Default slave don't have data
endmodule
\ No newline at end of file