From a51dddead317f88afdf266458383501d96429ae3 Mon Sep 17 00:00:00 2001
From: David Mapstone <david@mapstone.me>
Date: Thu, 16 Mar 2023 11:15:41 +0000
Subject: [PATCH] SOC1-121: Reworked simulation flow, updated RTL to fix
simulation bugs and moved modified CMSDK files
---
...er_src.flist => accelerator_wrapper.flist} | 14 +++++-----
flist/ahb_ip.flist | 28 +++++++++++++++++++
flow/simulators/ivlog_sim.sh | 16 -----------
flow/socsim | 18 ------------
hdl/src/wrapper_ahb_reg_interface.sv | 22 +++++++++------
hdl/src/wrapper_packet_construct.sv | 4 +--
.../cmsdk_ahb_default_slave.v | 0
.../cmsdk_ahb_fileread_funnel.v | 0
.../cmsdk_ahb_fileread_master32.v | 0
.../cmsdk_ahb_filereadcore.v | 2 --
.../{submodules => cmsdk}/cmsdk_ahb_ram_beh.v | 0
.../cmsdk_ahb_slave_mux.v | 0
hdl/verif/tb_wrapper_sha256_hashing_stream.sv | 8 +-----
.../socsim/wrapper_sha256_hashing_stream.sh | 16 +++++++++++
socsim | 1 +
15 files changed, 69 insertions(+), 60 deletions(-)
rename flist/{accelerator-wrapper_src.flist => accelerator_wrapper.flist} (68%)
create mode 100644 flist/ahb_ip.flist
delete mode 100755 flow/simulators/ivlog_sim.sh
delete mode 100755 flow/socsim
rename hdl/verif/{submodules => cmsdk}/cmsdk_ahb_default_slave.v (100%)
rename hdl/verif/{submodules => cmsdk}/cmsdk_ahb_fileread_funnel.v (100%)
rename hdl/verif/{submodules => cmsdk}/cmsdk_ahb_fileread_master32.v (100%)
rename hdl/verif/{submodules => cmsdk}/cmsdk_ahb_filereadcore.v (99%)
rename hdl/verif/{submodules => cmsdk}/cmsdk_ahb_ram_beh.v (100%)
rename hdl/verif/{submodules => cmsdk}/cmsdk_ahb_slave_mux.v (100%)
create mode 100755 simulate/socsim/wrapper_sha256_hashing_stream.sh
create mode 160000 socsim
diff --git a/flist/accelerator-wrapper_src.flist b/flist/accelerator_wrapper.flist
similarity index 68%
rename from flist/accelerator-wrapper_src.flist
rename to flist/accelerator_wrapper.flist
index 813546e..1323194 100644
--- a/flist/accelerator-wrapper_src.flist
+++ b/flist/accelerator_wrapper.flist
@@ -16,11 +16,11 @@
+libext+.v+.vlib
// ============= Accelerator Module search path =============
--y $(WRAP_ACC_DIR)/hdl/src/
-+incdir+$(WRAP_ACC_DIR)/hdl/src/
+-y $(ACC_WRAPPER_DIR)/hdl/src/
++incdir+$(ACC_WRAPPER_DIR)/hdl/src/
-$(WRAP_ACC_DIR)/hdl/src/wrapper_ahb_reg_interface.sv
-$(WRAP_ACC_DIR)/hdl/src/wrapper_ahb_to_vr_interface.sv
-$(WRAP_ACC_DIR)/hdl/src/wrapper_packet_construct.sv
-$(WRAP_ACC_DIR)/hdl/src/wrapper_packet_deconstruct.sv
-$(WRAP_ACC_DIR)/hdl/src/wrapper_sha256_hashing_stream.sv
\ No newline at end of file
+$(ACC_WRAPPER_DIR)/hdl/src/wrapper_ahb_reg_interface.sv
+$(ACC_WRAPPER_DIR)/hdl/src/wrapper_ahb_to_vr_interface.sv
+$(ACC_WRAPPER_DIR)/hdl/src/wrapper_packet_construct.sv
+$(ACC_WRAPPER_DIR)/hdl/src/wrapper_packet_deconstruct.sv
+$(ACC_WRAPPER_DIR)/hdl/src/wrapper_sha256_hashing_stream.sv
\ No newline at end of file
diff --git a/flist/ahb_ip.flist b/flist/ahb_ip.flist
new file mode 100644
index 0000000..693b870
--- /dev/null
+++ b/flist/ahb_ip.flist
@@ -0,0 +1,28 @@
+//-----------------------------------------------------------------------------
+// Accelerator Wrapper CMSDK Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for Accelerator CMSDK Wrapper Components
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// ============= Accelerator Module search path =============
+-y $(ACC_WRAPPER_DIR)/hdl/verif/
+-y $(ACC_WRAPPER_DIR)/hdl/verif/cmsdk
++incdir+$(ACC_WRAPPER_DIR)/hdl/verif/
++incdir+$(ACC_WRAPPER_DIR)/hdl/verif/cmsdk/
+
+$(ACC_WRAPPER_DIR)/hdl/verif/cmsdk/cmsdk_ahb_filereadcore.v
+$(ACC_WRAPPER_DIR)/hdl/verif/cmsdk/cmsdk_ahb_fileread_funnel.v
+$(ACC_WRAPPER_DIR)/hdl/verif/cmsdk/cmsdk_ahb_fileread_master32.v
+$(ACC_WRAPPER_DIR)/hdl/verif/cmsdk/cmsdk_ahb_default_slave.v
+$(ACC_WRAPPER_DIR)/hdl/verif/cmsdk/cmsdk_ahb_slave_mux.v
\ No newline at end of file
diff --git a/flow/simulators/ivlog_sim.sh b/flow/simulators/ivlog_sim.sh
deleted file mode 100755
index 48dbfcd..0000000
--- a/flow/simulators/ivlog_sim.sh
+++ /dev/null
@@ -1,16 +0,0 @@
-#-----------------------------------------------------------------------------
-# SoC Labs icarus verilog simulation script for engine testbench
-# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-#
-# Contributors
-#
-# David Mapstone (d.a.mapstone@soton.ac.uk)
-#
-# Copyright 2022, SoC Labs (www.soclabs.org)
-#-----------------------------------------------------------------------------
-
-#!/usr/bin/env bash
-
-mkdir -p $SOC_TOP/simulate/sim/
-iverilog -c $WRAP_ACC_DIR/flist/*.flist -c $ACC_ENGINE_DIR/flist/*.flist -I $SOC_TOP/hdl/verif/ -I $SOC_TOP/hdl/verif/submodules -I $SOC_TOP/hdl/src/ -I $ACC_ENGINE_DIR/hdl/src/ -g2012 -o $SOC_TOP/simulate/sim/$1.vvp $SOC_TOP/hdl/verif/tb_$1.sv
-cd $SOC_TOP/simulate/sim/ && vvp $1.vvp $2
\ No newline at end of file
diff --git a/flow/socsim b/flow/socsim
deleted file mode 100755
index 4b2d7f1..0000000
--- a/flow/socsim
+++ /dev/null
@@ -1,18 +0,0 @@
-#-----------------------------------------------------------------------------
-# SoC Labs socsim script to run required simulation
-# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-#
-# Contributors
-#
-# David Mapstone (d.a.mapstone@soton.ac.uk)
-#
-# Copyright 2022, SoC Labs (www.soclabs.org)
-#-----------------------------------------------------------------------------
-
-#!/usr/bin/env bash
-
-DEFAULT_SIMULATOR="ivlog"
-if [[ -z "${SIMULATOR}" ]]; then
- SIMULATOR=$DEFAULT_SIMULATOR
-fi
-$SOC_TOP_DIR"/flow/simulators/"$SIMULATOR"_sim.sh" $@
diff --git a/hdl/src/wrapper_ahb_reg_interface.sv b/hdl/src/wrapper_ahb_reg_interface.sv
index 5f0747c..4239ac6 100644
--- a/hdl/src/wrapper_ahb_reg_interface.sv
+++ b/hdl/src/wrapper_ahb_reg_interface.sv
@@ -76,12 +76,18 @@ module wrapper_ahb_reg_interface #(
logic update_read_req; // To update the read enable register
logic update_write_req; // To update the write enable register
- reg [ADDRWIDTH-1:0] addr_reg; // address signal, registered
- reg read_en_reg; // read enable signal, registered
- reg write_en_reg; // write enable signal, registered
+ logic [ADDRWIDTH-1:0] addr_reg; // address signal, registered
+ logic read_en_reg; // read enable signal, registered
+ logic write_en_reg; // write enable signal, registered
- reg [3:0] byte_strobe_reg; // registered output for byte strobe
- reg [3:0] byte_strobe_nxt; // next state for byte_strobe_reg
+ logic [3:0] byte_strobe_reg; // registered output for byte strobe
+ logic [3:0] byte_strobe_nxt; // next state for byte_strobe_reg
+
+ logic [1:0] haddrs_byte_sel; // Select which byte to enable
+ logic haddrs_halfword_sel; // Select which byte to enable
+
+ assign haddrs_byte_sel = haddrs[1:0];
+ assign haddrs_halfword_sel = haddrs[1];
//-----------------------------------------------------------
// Module logic start
//----------------------------------------------------------
@@ -131,11 +137,11 @@ module wrapper_ahb_reg_interface #(
end
// byte strobe signal
- always_ff @(hsizes or haddrs)
+ always_comb
begin
if (hsizes == 3'b000) //byte
begin
- case(haddrs[1:0])
+ case(haddrs_byte_sel)
2'b00: byte_strobe_nxt = 4'b0001;
2'b01: byte_strobe_nxt = 4'b0010;
2'b10: byte_strobe_nxt = 4'b0100;
@@ -145,7 +151,7 @@ module wrapper_ahb_reg_interface #(
end
else if (hsizes == 3'b001) //half word
begin
- if(haddrs[1]==1'b1)
+ if(haddrs_halfword_sel == 1'b1)
byte_strobe_nxt = 4'b1100;
else
byte_strobe_nxt = 4'b0011;
diff --git a/hdl/src/wrapper_packet_construct.sv b/hdl/src/wrapper_packet_construct.sv
index 7d2f944..f556605 100644
--- a/hdl/src/wrapper_packet_construct.sv
+++ b/hdl/src/wrapper_packet_construct.sv
@@ -58,8 +58,8 @@ assign addr_top_bit = (addr[PACKETBYTEWIDTH-1:REGDBYTEWIDTH] * REGDWIDTH) + (REG
// Check if current Register address is last word in packet
logic packet_last_word, prev_packet_last_word;
-assign packet_last_word = &addr[PACKETBYTEWIDTH-1:REGDBYTEWIDTH];
-assign packet_last_word = &addr[PACKETBYTEWIDTH-1:REGDBYTEWIDTH];
+assign packet_last_word = &addr [PACKETBYTEWIDTH-1:REGDBYTEWIDTH];
+assign prev_packet_last_word = &prev_wr_addr [PACKETBYTEWIDTH-1:REGDBYTEWIDTH];
// Packet Address - Address of Packet
logic [ADDRWIDTH-1:PACKETBYTEWIDTH] packet_addr, prev_packet_addr;
diff --git a/hdl/verif/submodules/cmsdk_ahb_default_slave.v b/hdl/verif/cmsdk/cmsdk_ahb_default_slave.v
similarity index 100%
rename from hdl/verif/submodules/cmsdk_ahb_default_slave.v
rename to hdl/verif/cmsdk/cmsdk_ahb_default_slave.v
diff --git a/hdl/verif/submodules/cmsdk_ahb_fileread_funnel.v b/hdl/verif/cmsdk/cmsdk_ahb_fileread_funnel.v
similarity index 100%
rename from hdl/verif/submodules/cmsdk_ahb_fileread_funnel.v
rename to hdl/verif/cmsdk/cmsdk_ahb_fileread_funnel.v
diff --git a/hdl/verif/submodules/cmsdk_ahb_fileread_master32.v b/hdl/verif/cmsdk/cmsdk_ahb_fileread_master32.v
similarity index 100%
rename from hdl/verif/submodules/cmsdk_ahb_fileread_master32.v
rename to hdl/verif/cmsdk/cmsdk_ahb_fileread_master32.v
diff --git a/hdl/verif/submodules/cmsdk_ahb_filereadcore.v b/hdl/verif/cmsdk/cmsdk_ahb_filereadcore.v
similarity index 99%
rename from hdl/verif/submodules/cmsdk_ahb_filereadcore.v
rename to hdl/verif/cmsdk/cmsdk_ahb_filereadcore.v
index 3ea41e0..91855da 100644
--- a/hdl/verif/submodules/cmsdk_ahb_filereadcore.v
+++ b/hdl/verif/cmsdk/cmsdk_ahb_filereadcore.v
@@ -291,14 +291,12 @@ module cmsdk_ahb_filereadcore #(
// Open Command File
//----------------------------------------------------------------------------
// Reads the command file into an array. This process is only executed once.
-
initial
begin : p_open_file_bhav
// report the stimulus file name to the simulation environment
$display (`ARM_FRBM_OPENFILE_MSG, $time, message_tag, input_filename);
$readmemh(input_filename, file_array);
-
end
diff --git a/hdl/verif/submodules/cmsdk_ahb_ram_beh.v b/hdl/verif/cmsdk/cmsdk_ahb_ram_beh.v
similarity index 100%
rename from hdl/verif/submodules/cmsdk_ahb_ram_beh.v
rename to hdl/verif/cmsdk/cmsdk_ahb_ram_beh.v
diff --git a/hdl/verif/submodules/cmsdk_ahb_slave_mux.v b/hdl/verif/cmsdk/cmsdk_ahb_slave_mux.v
similarity index 100%
rename from hdl/verif/submodules/cmsdk_ahb_slave_mux.v
rename to hdl/verif/cmsdk/cmsdk_ahb_slave_mux.v
diff --git a/hdl/verif/tb_wrapper_sha256_hashing_stream.sv b/hdl/verif/tb_wrapper_sha256_hashing_stream.sv
index 3730176..364d316 100644
--- a/hdl/verif/tb_wrapper_sha256_hashing_stream.sv
+++ b/hdl/verif/tb_wrapper_sha256_hashing_stream.sv
@@ -35,11 +35,6 @@
// Abstract : Example for File Reader Bus Master
// Testbench for the example AHB Lite slave.
//=========================================================================--
-`include "cmsdk_ahb_filereadcore.v"
-`include "cmsdk_ahb_fileread_funnel.v"
-`include "cmsdk_ahb_fileread_master32.v"
-`include "cmsdk_ahb_default_slave.v"
-`include "cmsdk_ahb_slave_mux.v"
`include "wrapper_sha256_hashing_stream.sv"
`timescale 1ns/1ps
@@ -49,8 +44,7 @@ module tb_wrapper_sha256_hashing_stream;
parameter CLK_PERIOD = 10;
parameter ADDRWIDTH = 12;
-// parameter InputFileName = "ahb_input_hash_stim.m2d";
-parameter InputFileName = ("../stimulus/ahb_input_hash_stim.m2d");
+parameter InputFileName = ("../../accelerator-wrapper/simulate/stimulus/ahb_input_hash_stim.m2d");
parameter MessageTag = "FileReader:";
parameter StimArraySize = 10000;
diff --git a/simulate/socsim/wrapper_sha256_hashing_stream.sh b/simulate/socsim/wrapper_sha256_hashing_stream.sh
new file mode 100755
index 0000000..008ebf2
--- /dev/null
+++ b/simulate/socsim/wrapper_sha256_hashing_stream.sh
@@ -0,0 +1,16 @@
+#-----------------------------------------------------------------------------
+# SoC Labs icarus verilog simulation script for engine testbench
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# David Mapstone (d.a.mapstone@soton.ac.uk)
+#
+# Copyright 2022, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+
+#!/usr/bin/env bash
+
+mkdir -p $SOC_TOP_DIR/simulate/sim/
+iverilog -c $ACC_WRAPPER_DIR/flist/accelerator_wrapper.flist -c $ACC_WRAPPER_DIR/flist/ahb_ip.flist -c $ACC_ENGINE_DIR/flist/*.flist -I $ACC_WRAPPER_DIR/hdl/verif/ -I $ACC_WRAPPER_DIR/hdl/verif/submodules -I $ACC_WRAPPER_DIR/hdl/src/ -I $ACC_ENGINE_DIR/hdl/src/ -g2012 -o $SOC_TOP_DIR/simulate/sim/wrapper_sha256_hashing_stream.vvp $ACC_WRAPPER_DIR/hdl/verif/tb_wrapper_sha256_hashing_stream.sv
+cd $SOC_TOP_DIR/simulate/sim/ && vvp wrapper_sha256_hashing_stream.vvp +STIMFILE=$ACC_WRAPPER_DIR/simulate/stimulus/ahb_input_hash_stim.m2d
\ No newline at end of file
diff --git a/socsim b/socsim
new file mode 160000
index 0000000..27329d3
--- /dev/null
+++ b/socsim
@@ -0,0 +1 @@
+Subproject commit 27329d3afac51fbf2762428e12f2635d1137c549
--
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