From 9d47f0f713de861761af6e7d091f1366d0bf4b50 Mon Sep 17 00:00:00 2001
From: David Mapstone <david@mapstone.me>
Date: Wed, 22 Feb 2023 11:41:12 +0000
Subject: [PATCH] Moved Wrapper Veriifcation Components
---
flow/simulators/ivlog_sim.sh | 2 +-
hdl/verif/{ => submodules}/cmsdk_ahb_default_slave.v | 0
hdl/verif/{ => submodules}/cmsdk_ahb_fileread_funnel.v | 0
hdl/verif/{ => submodules}/cmsdk_ahb_fileread_master32.v | 0
hdl/verif/{ => submodules}/cmsdk_ahb_filereadcore.v | 0
hdl/verif/{ => submodules}/cmsdk_ahb_ram_beh.v | 0
hdl/verif/{ => submodules}/cmsdk_ahb_slave_mux.v | 0
7 files changed, 1 insertion(+), 1 deletion(-)
rename hdl/verif/{ => submodules}/cmsdk_ahb_default_slave.v (100%)
rename hdl/verif/{ => submodules}/cmsdk_ahb_fileread_funnel.v (100%)
rename hdl/verif/{ => submodules}/cmsdk_ahb_fileread_master32.v (100%)
rename hdl/verif/{ => submodules}/cmsdk_ahb_filereadcore.v (100%)
rename hdl/verif/{ => submodules}/cmsdk_ahb_ram_beh.v (100%)
rename hdl/verif/{ => submodules}/cmsdk_ahb_slave_mux.v (100%)
diff --git a/flow/simulators/ivlog_sim.sh b/flow/simulators/ivlog_sim.sh
index ec8c7d6..a956e4d 100755
--- a/flow/simulators/ivlog_sim.sh
+++ b/flow/simulators/ivlog_sim.sh
@@ -12,5 +12,5 @@
#!/usr/bin/env bash
mkdir -p $SOC_TOP/simulate/sim/
-iverilog -I $SOC_TOP/hdl/verif/ -I $SOC_TOP/hdl/src/ -I $SHA_2_ACC_DIR/hdl/src/ -g2012 -o $SOC_TOP/simulate/sim/$1.vvp $SOC_TOP/hdl/verif/tb_$1.sv
+iverilog -I $SOC_TOP/hdl/verif/ -I $SOC_TOP/hdl/verif/submodules -I $SOC_TOP/hdl/src/ -I $SHA_2_ACC_DIR/hdl/src/ -g2012 -o $SOC_TOP/simulate/sim/$1.vvp $SOC_TOP/hdl/verif/tb_$1.sv
cd $SOC_TOP/simulate/sim/ && vvp $1.vvp $2
\ No newline at end of file
diff --git a/hdl/verif/cmsdk_ahb_default_slave.v b/hdl/verif/submodules/cmsdk_ahb_default_slave.v
similarity index 100%
rename from hdl/verif/cmsdk_ahb_default_slave.v
rename to hdl/verif/submodules/cmsdk_ahb_default_slave.v
diff --git a/hdl/verif/cmsdk_ahb_fileread_funnel.v b/hdl/verif/submodules/cmsdk_ahb_fileread_funnel.v
similarity index 100%
rename from hdl/verif/cmsdk_ahb_fileread_funnel.v
rename to hdl/verif/submodules/cmsdk_ahb_fileread_funnel.v
diff --git a/hdl/verif/cmsdk_ahb_fileread_master32.v b/hdl/verif/submodules/cmsdk_ahb_fileread_master32.v
similarity index 100%
rename from hdl/verif/cmsdk_ahb_fileread_master32.v
rename to hdl/verif/submodules/cmsdk_ahb_fileread_master32.v
diff --git a/hdl/verif/cmsdk_ahb_filereadcore.v b/hdl/verif/submodules/cmsdk_ahb_filereadcore.v
similarity index 100%
rename from hdl/verif/cmsdk_ahb_filereadcore.v
rename to hdl/verif/submodules/cmsdk_ahb_filereadcore.v
diff --git a/hdl/verif/cmsdk_ahb_ram_beh.v b/hdl/verif/submodules/cmsdk_ahb_ram_beh.v
similarity index 100%
rename from hdl/verif/cmsdk_ahb_ram_beh.v
rename to hdl/verif/submodules/cmsdk_ahb_ram_beh.v
diff --git a/hdl/verif/cmsdk_ahb_slave_mux.v b/hdl/verif/submodules/cmsdk_ahb_slave_mux.v
similarity index 100%
rename from hdl/verif/cmsdk_ahb_slave_mux.v
rename to hdl/verif/submodules/cmsdk_ahb_slave_mux.v
--
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