diff --git a/flow/simulators/ivlog_sim.sh b/flow/simulators/ivlog_sim.sh
new file mode 100755
index 0000000000000000000000000000000000000000..674d71ecca3550cc0005a66fc2ef877bc747fa63
--- /dev/null
+++ b/flow/simulators/ivlog_sim.sh
@@ -0,0 +1,16 @@
+#-----------------------------------------------------------------------------
+# SoC Labs icarus verilog simulation script for engine testbench
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# David Mapstone (d.a.mapstone@soton.ac.uk)
+#
+# Copyright 2022, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+
+#!/usr/bin/env bash
+
+mkdir -p $SOC_TOP/simulate/sim/
+iverilog -I $SOC_TOP/hdl/verif/ -I $SOC_TOP/hdl/src/ -g2012 -o $SOC_TOP/simulate/sim/$1.vvp $SOC_TOP/hdl/verif/tb_$1.sv
+cd $SOC_TOP/simulate/sim/ && vvp $1.vvp $2
\ No newline at end of file
diff --git a/flow/socsim b/flow/socsim
new file mode 100755
index 0000000000000000000000000000000000000000..42c6196bc101419a6a108eba4865be67a760d076
--- /dev/null
+++ b/flow/socsim
@@ -0,0 +1,18 @@
+#-----------------------------------------------------------------------------
+# SoC Labs socsim script to run required simulation
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# David Mapstone (d.a.mapstone@soton.ac.uk)
+#
+# Copyright 2022, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+
+#!/usr/bin/env bash
+
+DEFAULT_SIMULATOR="ivlog"
+if [[ -z "${SIMULATOR}" ]]; then
+ SIMULATOR=$DEFAULT_SIMULATOR
+fi
+$SOC_TOP"/flow/simulators/"$SIMULATOR"_sim.sh" $@
diff --git a/simulate/sim/wrapper_top.vvp b/simulate/sim/wrapper_top.vvp
new file mode 100755
index 0000000000000000000000000000000000000000..ede1122464107288b3e9607920c2123e541aadca
--- /dev/null
+++ b/simulate/sim/wrapper_top.vvp
@@ -0,0 +1,3088 @@
+#! /opt/homebrew/Cellar/icarus-verilog/11.0/bin/vvp
+:ivl_version "11.0 (stable)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision + 0;
+:vpi_module "/opt/homebrew/Cellar/icarus-verilog/11.0/lib/ivl/system.vpi";
+:vpi_module "/opt/homebrew/Cellar/icarus-verilog/11.0/lib/ivl/vhdl_sys.vpi";
+:vpi_module "/opt/homebrew/Cellar/icarus-verilog/11.0/lib/ivl/vhdl_textio.vpi";
+:vpi_module "/opt/homebrew/Cellar/icarus-verilog/11.0/lib/ivl/v2005_math.vpi";
+:vpi_module "/opt/homebrew/Cellar/icarus-verilog/11.0/lib/ivl/va_math.vpi";
+:vpi_module "/opt/homebrew/Cellar/icarus-verilog/11.0/lib/ivl/v2009.vpi";
+S_0x12ef050f0 .scope package, "$unit" "$unit" 2 1;
+ .timescale 0 0;
+S_0x12ef05380 .scope module, "cmsdk_ahb_default_slave" "cmsdk_ahb_default_slave" 3 30;
+ .timescale 0 0;
+ .port_info 0 /INPUT 1 "HCLK";
+ .port_info 1 /INPUT 1 "HRESETn";
+ .port_info 2 /INPUT 1 "HSEL";
+ .port_info 3 /INPUT 2 "HTRANS";
+ .port_info 4 /INPUT 1 "HREADY";
+ .port_info 5 /OUTPUT 1 "HREADYOUT";
+ .port_info 6 /OUTPUT 1 "HRESP";
+o0x120040100 .functor BUFZ 1, C4<z>; HiZ drive
+L_0x12ef058f0 .functor AND 1, o0x120040100, L_0x12ef24130, C4<1>, C4<1>;
+o0x120040040 .functor BUFZ 1, C4<z>; HiZ drive
+L_0x12ef24270 .functor AND 1, L_0x12ef058f0, o0x120040040, C4<1>, C4<1>;
+L_0x12ef24420 .functor NOT 1, L_0x12ef24340, C4<0>, C4<0>, C4<0>;
+L_0x12ef244f0 .functor OR 1, L_0x12ef24270, L_0x12ef24420, C4<0>, C4<0>;
+L_0x12ef24620 .functor NOT 1, L_0x12ef24270, C4<0>, C4<0>, C4<0>;
+o0x120040010 .functor BUFZ 1, C4<z>; HiZ drive
+v0x12ef05b00_0 .net "HCLK", 0 0, o0x120040010; 0 drivers
+v0x12ef15b40_0 .net "HREADY", 0 0, o0x120040040; 0 drivers
+v0x12ef15be0_0 .net "HREADYOUT", 0 0, L_0x12ef247e0; 1 drivers
+o0x1200400a0 .functor BUFZ 1, C4<z>; HiZ drive
+v0x12ef15c70_0 .net "HRESETn", 0 0, o0x1200400a0; 0 drivers
+v0x12ef15d10_0 .net "HRESP", 0 0, L_0x12ef248c0; 1 drivers
+v0x12ef15df0_0 .net "HSEL", 0 0, o0x120040100; 0 drivers
+o0x120040130 .functor BUFZ 2, C4<zz>; HiZ drive
+v0x12ef15e90_0 .net "HTRANS", 1 0, o0x120040130; 0 drivers
+v0x12ef15f40_0 .net *"_ivl_1", 0 0, L_0x12ef24130; 1 drivers
+v0x12ef15ff0_0 .net *"_ivl_10", 0 0, L_0x12ef244f0; 1 drivers
+v0x12ef16100_0 .net *"_ivl_12", 0 0, L_0x12ef24620; 1 drivers
+v0x12ef161b0_0 .net *"_ivl_2", 0 0, L_0x12ef058f0; 1 drivers
+v0x12ef16260_0 .net *"_ivl_7", 0 0, L_0x12ef24340; 1 drivers
+v0x12ef16310_0 .net *"_ivl_8", 0 0, L_0x12ef24420; 1 drivers
+v0x12ef163c0_0 .net "next_state", 1 0, L_0x12ef246c0; 1 drivers
+v0x12ef16470_0 .var "resp_state", 1 0;
+v0x12ef16520_0 .net "trans_req", 0 0, L_0x12ef24270; 1 drivers
+E_0x12ef04f90/0 .event negedge, v0x12ef15c70_0;
+E_0x12ef04f90/1 .event posedge, v0x12ef05b00_0;
+E_0x12ef04f90 .event/or E_0x12ef04f90/0, E_0x12ef04f90/1;
+L_0x12ef24130 .part o0x120040130, 1, 1;
+L_0x12ef24340 .part v0x12ef16470_0, 0, 1;
+L_0x12ef246c0 .concat [ 1 1 0 0], L_0x12ef24620, L_0x12ef244f0;
+L_0x12ef247e0 .part v0x12ef16470_0, 0, 1;
+L_0x12ef248c0 .part v0x12ef16470_0, 1, 1;
+S_0x12ef055a0 .scope module, "cmsdk_ahb_fileread_master32" "cmsdk_ahb_fileread_master32" 4 37;
+ .timescale 0 0;
+ .port_info 0 /INPUT 1 "HCLK";
+ .port_info 1 /INPUT 1 "HRESETn";
+ .port_info 2 /INPUT 1 "HREADY";
+ .port_info 3 /INPUT 1 "HRESP";
+ .port_info 4 /INPUT 32 "HRDATA";
+ .port_info 5 /INPUT 1 "EXRESP";
+ .port_info 6 /OUTPUT 2 "HTRANS";
+ .port_info 7 /OUTPUT 3 "HBURST";
+ .port_info 8 /OUTPUT 4 "HPROT";
+ .port_info 9 /OUTPUT 1 "EXREQ";
+ .port_info 10 /OUTPUT 2 "MEMATTR";
+ .port_info 11 /OUTPUT 3 "HSIZE";
+ .port_info 12 /OUTPUT 1 "HWRITE";
+ .port_info 13 /OUTPUT 1 "HMASTLOCK";
+ .port_info 14 /OUTPUT 32 "HADDR";
+ .port_info 15 /OUTPUT 32 "HWDATA";
+ .port_info 16 /OUTPUT 32 "LINENUM";
+P_0x12ef05710 .param/str "InputFileName" 0 4 39, "filestim.m2d";
+P_0x12ef05750 .param/str "MessageTag" 0 4 40, "FileReader:";
+P_0x12ef05790 .param/l "StimArraySize" 0 4 41, +C4<00000000000000000001001110001000>;
+L_0x12ef2b210 .functor BUFZ 32, L_0x12ef26b40, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+v0x12ef22df0_0 .net "EXREQ", 0 0, L_0x12ef2b660; 1 drivers
+o0x120043160 .functor BUFZ 1, C4<z>; HiZ drive
+v0x12ef22ea0_0 .net "EXRESP", 0 0, o0x120043160; 0 drivers
+v0x12ef22f40_0 .net "HADDR", 31 0, L_0x12ef2b210; 1 drivers
+v0x12ef22fd0_0 .net "HBURST", 2 0, L_0x12ef289f0; 1 drivers
+o0x120040490 .functor BUFZ 1, C4<z>; HiZ drive
+v0x12ef23060_0 .net "HCLK", 0 0, o0x120040490; 0 drivers
+v0x12ef23170_0 .net "HMASTLOCK", 0 0, L_0x12ef28870; 1 drivers
+v0x12ef23200_0 .net "HPROT", 3 0, L_0x12ef2b5c0; 1 drivers
+o0x1200404c0 .functor BUFZ 32, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0x12ef23290_0 .net "HRDATA", 31 0, o0x1200404c0; 0 drivers
+o0x120040520 .functor BUFZ 1, C4<z>; HiZ drive
+v0x12ef23320_0 .net "HREADY", 0 0, o0x120040520; 0 drivers
+o0x120040550 .functor BUFZ 1, C4<z>; HiZ drive
+v0x12ef23430_0 .net "HRESETn", 0 0, o0x120040550; 0 drivers
+o0x1200431f0 .functor BUFZ 1, C4<z>; HiZ drive
+v0x12ef23500_0 .net "HRESP", 0 0, o0x1200431f0; 0 drivers
+v0x12ef23590_0 .net "HSIZE", 2 0, L_0x12ef28310; 1 drivers
+v0x12ef23620_0 .net "HTRANS", 1 0, L_0x12ef27b30; 1 drivers
+v0x12ef236b0_0 .net "HWDATA", 31 0, v0x12ef17120_0; 1 drivers
+v0x12ef23760_0 .net "HWRITE", 0 0, L_0x12ef286c0; 1 drivers
+v0x12ef23810_0 .net "LINENUM", 31 0, L_0x12ef28920; 1 drivers
+v0x12ef238c0_0 .net "MEMATTR", 1 0, L_0x12ef2b820; 1 drivers
+v0x12ef23a50_0 .net *"_ivl_11", 0 0, L_0x12ef2b780; 1 drivers
+L_0x120079018 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0x12ef23b00_0 .net/2u *"_ivl_14", 0 0, L_0x120079018; 1 drivers
+L_0x120078fd0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0x12ef23bb0_0 .net/2u *"_ivl_8", 0 0, L_0x120078fd0; 1 drivers
+v0x12ef23c60_0 .net "haddr_core", 31 0, L_0x12ef26b40; 1 drivers
+v0x12ef23d20_0 .net "hprot_core", 5 0, v0x12ef22a40_0; 1 drivers
+v0x12ef23db0_0 .net "hrdata_core", 63 0, L_0x12ef2b0d0; 1 drivers
+v0x12ef23e40_0 .net "hresp_core", 2 0, L_0x12ef2b900; 1 drivers
+v0x12ef23ed0_0 .net "hwdata_core", 63 0, L_0x12ef2af40; 1 drivers
+L_0x12ef2b170 .part L_0x12ef26b40, 2, 1;
+L_0x12ef2b5c0 .part v0x12ef22a40_0, 0, 4;
+L_0x12ef2b660 .part v0x12ef22a40_0, 5, 1;
+L_0x12ef2b780 .part v0x12ef22a40_0, 4, 1;
+L_0x12ef2b820 .concat [ 1 1 0 0], L_0x12ef2b780, L_0x120078fd0;
+L_0x12ef2b900 .concat [ 1 1 1 0], o0x1200431f0, L_0x120079018, o0x120043160;
+S_0x12ef16630 .scope module, "u_ahb_fileread_funnel" "cmsdk_ahb_fileread_funnel" 4 107, 5 32 0, S_0x12ef055a0;
+ .timescale 0 0;
+ .port_info 0 /INPUT 1 "HCLK";
+ .port_info 1 /INPUT 1 "HRESETn";
+ .port_info 2 /INPUT 1 "HADDR2S";
+ .port_info 3 /INPUT 64 "HWDATAS";
+ .port_info 4 /INPUT 1 "HREADYS";
+ .port_info 5 /OUTPUT 64 "HRDATAS";
+ .port_info 6 /OUTPUT 32 "HWDATAM";
+ .port_info 7 /INPUT 32 "HRDATAM";
+v0x12ef16cf0_0 .net "HADDR2S", 0 0, L_0x12ef2b170; 1 drivers
+v0x12ef16d90_0 .net "HCLK", 0 0, o0x120040490; alias, 0 drivers
+v0x12ef16e30_0 .net "HRDATAM", 31 0, o0x1200404c0; alias, 0 drivers
+v0x12ef16ef0_0 .net "HRDATAS", 63 0, L_0x12ef2b0d0; alias, 1 drivers
+v0x12ef16fa0_0 .net "HREADYS", 0 0, o0x120040520; alias, 0 drivers
+v0x12ef17080_0 .net "HRESETn", 0 0, o0x120040550; alias, 0 drivers
+v0x12ef17120_0 .var "HWDATAM", 31 0;
+v0x12ef171d0_0 .net "HWDATAS", 63 0, L_0x12ef2af40; alias, 1 drivers
+v0x12ef17280_0 .var "haddr2s_reg", 0 0;
+E_0x12ef168c0 .event edge, v0x12ef171d0_0, v0x12ef17280_0;
+E_0x12ef16910/0 .event negedge, v0x12ef17080_0;
+E_0x12ef16910/1 .event posedge, v0x12ef16d90_0;
+E_0x12ef16910 .event/or E_0x12ef16910/0, E_0x12ef16910/1;
+L_0x12ef2b0d0 .concat [ 32 32 0 0], o0x1200404c0, o0x1200404c0;
+S_0x12ef16950 .scope begin, "p_haddr2s_reg" "p_haddr2s_reg" 5 59, 5 59 0, S_0x12ef16630;
+ .timescale 0 0;
+S_0x12ef16b20 .scope begin, "p_write_mux" "p_write_mux" 5 76, 5 76 0, S_0x12ef16630;
+ .timescale 0 0;
+S_0x12ef17400 .scope module, "u_ahb_filereadcore" "cmsdk_ahb_filereadcore" 4 84, 6 32 0, S_0x12ef055a0;
+ .timescale 0 0;
+ .port_info 0 /INPUT 1 "HCLK";
+ .port_info 1 /INPUT 1 "HRESETn";
+ .port_info 2 /INPUT 1 "HREADY";
+ .port_info 3 /INPUT 3 "HRESP";
+ .port_info 4 /INPUT 64 "HRDATA";
+ .port_info 5 /OUTPUT 2 "HTRANS";
+ .port_info 6 /OUTPUT 3 "HBURST";
+ .port_info 7 /OUTPUT 6 "HPROT";
+ .port_info 8 /OUTPUT 3 "HSIZE";
+ .port_info 9 /OUTPUT 1 "HWRITE";
+ .port_info 10 /OUTPUT 1 "HMASTLOCK";
+ .port_info 11 /OUTPUT 32 "HADDR";
+ .port_info 12 /OUTPUT 64 "HWDATA";
+ .port_info 13 /OUTPUT 1 "HUNALIGN";
+ .port_info 14 /OUTPUT 8 "HBSTRB";
+ .port_info 15 /OUTPUT 32 "LINENUM";
+P_0x12ef175d0 .param/str "input_filename" 0 6 34, "filestim.m2d";
+P_0x12ef17610 .param/str "message_tag" 0 6 35, "FileReader:";
+P_0x12ef17650 .param/l "stim_array_size" 0 6 36, +C4<00000000000000000001001110001000>;
+L_0x12ef24a50 .functor AND 3, L_0x12ef24990, v0x12ef20410_0, C4<111>, C4<111>;
+L_0x12ef24fd0 .functor AND 1, L_0x12ef24d80, L_0x12ef24ea0, C4<1>, C4<1>;
+L_0x12ef25360 .functor AND 1, L_0x12ef250e0, L_0x12ef25200, C4<1>, C4<1>;
+L_0x12ef25470 .functor OR 1, L_0x12ef24fd0, L_0x12ef25360, C4<0>, C4<0>;
+L_0x12ef257b0 .functor AND 1, L_0x12ef255a0, L_0x12ef25680, C4<1>, C4<1>;
+L_0x12ef258b0 .functor OR 1, L_0x12ef25470, L_0x12ef257b0, C4<0>, C4<0>;
+L_0x12ef25c40 .functor AND 1, L_0x12ef259a0, L_0x12ef25ac0, C4<1>, C4<1>;
+L_0x12ef25d50 .functor OR 1, L_0x12ef258b0, L_0x12ef25c40, C4<0>, C4<0>;
+L_0x12ef260b0 .functor AND 1, L_0x12ef25ec0, L_0x12ef25f60, C4<1>, C4<1>;
+L_0x12ef261d0 .functor OR 1, L_0x12ef25d50, L_0x12ef260b0, C4<0>, C4<0>;
+L_0x12ef26040 .functor AND 1, L_0x12ef26280, L_0x12ef26360, C4<1>, C4<1>;
+L_0x12ef265c0 .functor OR 1, L_0x12ef261d0, L_0x12ef26040, C4<0>, C4<0>;
+L_0x12ef25a40 .functor OR 1, L_0x12ef26aa0, L_0x12ef26ce0, C4<0>, C4<0>;
+L_0x12ef26b40 .functor BUFZ 32, L_0x12ef26ef0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+L_0x12ef275b0 .functor OR 1, L_0x12ef273a0, L_0x12ef27280, C4<0>, C4<0>;
+L_0x12ef26e80 .functor AND 1, L_0x12ef26f90, L_0x12ef275b0, C4<1>, C4<1>;
+L_0x12ef277c0 .functor OR 1, L_0x12ef271a0, L_0x12ef26e80, C4<0>, C4<0>;
+L_0x12ef27940 .functor AND 1, L_0x12ef270c0, L_0x12ef277c0, C4<1>, C4<1>;
+L_0x12ef27b30 .functor BUFZ 2, v0x12ef21440_0, C4<00>, C4<00>, C4<00>;
+L_0x12ef27eb0 .functor OR 1, L_0x12ef27c80, L_0x12ef27d20, C4<0>, C4<0>;
+L_0x12ef28200 .functor AND 1, L_0x12ef27fe0, L_0x12ef27dc0, C4<1>, C4<1>;
+L_0x12ef283c0 .functor OR 1, L_0x12ef27f40, L_0x12ef28200, C4<0>, C4<0>;
+L_0x12ef286c0 .functor BUFZ 1, L_0x12ef285e0, C4<0>, C4<0>, C4<0>;
+L_0x12ef28870 .functor BUFZ 1, v0x12ef229a0_0, C4<0>, C4<0>, C4<0>;
+L_0x12ef28310 .functor BUFZ 3, v0x12ef22af0_0, C4<000>, C4<000>, C4<000>;
+L_0x12ef289f0 .functor BUFZ 3, v0x12ef22640_0, C4<000>, C4<000>, C4<000>;
+L_0x12ef28b80 .functor BUFZ 1, v0x12ef223a0_0, C4<0>, C4<0>, C4<0>;
+L_0x12ef28920 .functor BUFZ 32, v0x12ef220e0_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+L_0x12ef28ce0 .functor BUFZ 8, v0x12ef21390_0, C4<00000000>, C4<00000000>, C4<00000000>;
+L_0x12ef2a3e0 .functor AND 64, v0x12ef22850_0, L_0x12ef29e80, C4<1111111111111111111111111111111111111111111111111111111111111111>, C4<1111111111111111111111111111111111111111111111111111111111111111>;
+L_0x12ef2a630 .functor AND 1, L_0x12ef2a0a0, L_0x12ef2a180, C4<1>, C4<1>;
+L_0x12ef2a860 .functor OR 1, L_0x12ef2a720, L_0x12ef2aaa0, C4<0>, C4<0>;
+L_0x12ef2a950 .functor AND 1, L_0x12ef2a630, L_0x12ef2a860, C4<1>, C4<1>;
+L_0x12ef2af40 .functor BUFZ 64, v0x12ef21190_0, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>;
+v0x12ef1a2b0_0 .net "HADDR", 31 0, L_0x12ef26b40; alias, 1 drivers
+v0x12ef1a360_0 .net "HBSTRB", 7 0, L_0x12ef28ce0; 1 drivers
+v0x12ef1a400_0 .net "HBURST", 2 0, L_0x12ef289f0; alias, 1 drivers
+v0x12ef1a490_0 .net "HCLK", 0 0, o0x120040490; alias, 0 drivers
+v0x12ef1a520_0 .net "HMASTLOCK", 0 0, L_0x12ef28870; alias, 1 drivers
+v0x12ef1a5f0_0 .net "HPROT", 5 0, v0x12ef22a40_0; alias, 1 drivers
+v0x12ef1a680_0 .net "HRDATA", 63 0, L_0x12ef2b0d0; alias, 1 drivers
+v0x12ef1a720_0 .net "HREADY", 0 0, o0x120040520; alias, 0 drivers
+v0x12ef1a7d0_0 .net "HRESETn", 0 0, o0x120040550; alias, 0 drivers
+v0x12ef1a900_0 .net "HRESP", 2 0, L_0x12ef2b900; alias, 1 drivers
+v0x12ef1a990_0 .net "HSIZE", 2 0, L_0x12ef28310; alias, 1 drivers
+v0x12ef1aa20_0 .net "HTRANS", 1 0, L_0x12ef27b30; alias, 1 drivers
+v0x12ef1aab0_0 .net "HUNALIGN", 0 0, L_0x12ef28b80; 1 drivers
+v0x12ef1ab40_0 .net "HWDATA", 63 0, L_0x12ef2af40; alias, 1 drivers
+v0x12ef1ac00_0 .net "HWRITE", 0 0, L_0x12ef286c0; alias, 1 drivers
+v0x12ef1ac90_0 .net "LINENUM", 31 0, L_0x12ef28920; alias, 1 drivers
+v0x12ef1ad40_0 .net *"_ivl_1", 2 0, L_0x12ef24990; 1 drivers
+v0x12ef1aef0_0 .net *"_ivl_10", 0 0, L_0x12ef24d80; 1 drivers
+L_0x1200784d8 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
+v0x12ef1af90_0 .net/2u *"_ivl_104", 1 0, L_0x1200784d8; 1 drivers
+v0x12ef1b040_0 .net *"_ivl_106", 0 0, L_0x12ef270c0; 1 drivers
+L_0x120078520 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0x12ef1b0e0_0 .net/2u *"_ivl_108", 0 0, L_0x120078520; 1 drivers
+v0x12ef1b190_0 .net *"_ivl_110", 0 0, L_0x12ef271a0; 1 drivers
+L_0x120078568 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0x12ef1b230_0 .net/2u *"_ivl_112", 0 0, L_0x120078568; 1 drivers
+v0x12ef1b2e0_0 .net *"_ivl_114", 0 0, L_0x12ef26f90; 1 drivers
+L_0x1200785b0 .functor BUFT 1, C4<00110000>, C4<0>, C4<0>, C4<0>;
+v0x12ef1b380_0 .net/2u *"_ivl_116", 7 0, L_0x1200785b0; 1 drivers
+v0x12ef1b430_0 .net *"_ivl_118", 0 0, L_0x12ef273a0; 1 drivers
+L_0x120078058 .functor BUFT 1, C4<00100000>, C4<0>, C4<0>, C4<0>;
+v0x12ef1b4d0_0 .net/2u *"_ivl_12", 7 0, L_0x120078058; 1 drivers
+L_0x1200785f8 .functor BUFT 1, C4<01000000>, C4<0>, C4<0>, C4<0>;
+v0x12ef1b580_0 .net/2u *"_ivl_120", 7 0, L_0x1200785f8; 1 drivers
+v0x12ef1b630_0 .net *"_ivl_122", 0 0, L_0x12ef27280; 1 drivers
+v0x12ef1b6d0_0 .net *"_ivl_125", 0 0, L_0x12ef275b0; 1 drivers
+v0x12ef1b770_0 .net *"_ivl_127", 0 0, L_0x12ef26e80; 1 drivers
+v0x12ef1b810_0 .net *"_ivl_129", 0 0, L_0x12ef277c0; 1 drivers
+v0x12ef1b8b0_0 .net *"_ivl_131", 0 0, L_0x12ef27940; 1 drivers
+L_0x120078640 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0x12ef1ade0_0 .net/2u *"_ivl_132", 0 0, L_0x120078640; 1 drivers
+L_0x120078688 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0x12ef1bb40_0 .net/2u *"_ivl_134", 0 0, L_0x120078688; 1 drivers
+v0x12ef1bbd0_0 .net *"_ivl_14", 0 0, L_0x12ef24ea0; 1 drivers
+L_0x1200786d0 .functor BUFT 1, C4<00110000>, C4<0>, C4<0>, C4<0>;
+v0x12ef1bc60_0 .net/2u *"_ivl_140", 7 0, L_0x1200786d0; 1 drivers
+v0x12ef1bd00_0 .net *"_ivl_142", 0 0, L_0x12ef27c80; 1 drivers
+L_0x120078718 .functor BUFT 1, C4<00100000>, C4<0>, C4<0>, C4<0>;
+v0x12ef1bda0_0 .net/2u *"_ivl_144", 7 0, L_0x120078718; 1 drivers
+v0x12ef1be50_0 .net *"_ivl_146", 0 0, L_0x12ef27d20; 1 drivers
+v0x12ef1bef0_0 .net *"_ivl_149", 0 0, L_0x12ef27eb0; 1 drivers
+L_0x120078760 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
+v0x12ef1bf90_0 .net/2u *"_ivl_150", 7 0, L_0x120078760; 1 drivers
+v0x12ef1c040_0 .net *"_ivl_152", 0 0, L_0x12ef27f40; 1 drivers
+L_0x1200787a8 .functor BUFT 1, C4<01000000>, C4<0>, C4<0>, C4<0>;
+v0x12ef1c0e0_0 .net/2u *"_ivl_154", 7 0, L_0x1200787a8; 1 drivers
+v0x12ef1c190_0 .net *"_ivl_156", 0 0, L_0x12ef27fe0; 1 drivers
+L_0x1200787f0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0x12ef1c230_0 .net/2u *"_ivl_158", 0 0, L_0x1200787f0; 1 drivers
+v0x12ef1c2e0_0 .net *"_ivl_160", 0 0, L_0x12ef27dc0; 1 drivers
+v0x12ef1c380_0 .net *"_ivl_163", 0 0, L_0x12ef28200; 1 drivers
+v0x12ef1c420_0 .net *"_ivl_165", 0 0, L_0x12ef283c0; 1 drivers
+L_0x120078838 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0x12ef1c4c0_0 .net/2u *"_ivl_166", 0 0, L_0x120078838; 1 drivers
+L_0x120078880 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0x12ef1c570_0 .net/2u *"_ivl_168", 0 0, L_0x120078880; 1 drivers
+v0x12ef1c620_0 .net *"_ivl_17", 0 0, L_0x12ef24fd0; 1 drivers
+v0x12ef1c6c0_0 .net *"_ivl_170", 0 0, L_0x12ef28430; 1 drivers
+L_0x1200780a0 .functor BUFT 1, C4<00100000>, C4<0>, C4<0>, C4<0>;
+v0x12ef1c770_0 .net/2u *"_ivl_18", 7 0, L_0x1200780a0; 1 drivers
+v0x12ef1c820_0 .net *"_ivl_193", 0 0, L_0x12ef28aa0; 1 drivers
+L_0x1200788c8 .functor BUFT 1, C4<11111111>, C4<0>, C4<0>, C4<0>;
+v0x12ef1c8d0_0 .net/2u *"_ivl_194", 7 0, L_0x1200788c8; 1 drivers
+L_0x120078910 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
+v0x12ef1c980_0 .net/2u *"_ivl_196", 7 0, L_0x120078910; 1 drivers
+v0x12ef1ca30_0 .net *"_ivl_198", 7 0, L_0x12ef26bd0; 1 drivers
+v0x12ef1cae0_0 .net *"_ivl_20", 0 0, L_0x12ef250e0; 1 drivers
+v0x12ef1cb80_0 .net *"_ivl_203", 0 0, L_0x12ef29070; 1 drivers
+L_0x120078958 .functor BUFT 1, C4<11111111>, C4<0>, C4<0>, C4<0>;
+v0x12ef1cc30_0 .net/2u *"_ivl_204", 7 0, L_0x120078958; 1 drivers
+L_0x1200789a0 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
+v0x12ef1cce0_0 .net/2u *"_ivl_206", 7 0, L_0x1200789a0; 1 drivers
+v0x12ef1cd90_0 .net *"_ivl_208", 7 0, L_0x12ef28d50; 1 drivers
+v0x12ef1ce40_0 .net *"_ivl_213", 0 0, L_0x12ef29240; 1 drivers
+L_0x1200789e8 .functor BUFT 1, C4<11111111>, C4<0>, C4<0>, C4<0>;
+v0x12ef1cef0_0 .net/2u *"_ivl_214", 7 0, L_0x1200789e8; 1 drivers
+L_0x120078a30 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
+v0x12ef1b960_0 .net/2u *"_ivl_216", 7 0, L_0x120078a30; 1 drivers
+v0x12ef1ba10_0 .net *"_ivl_218", 7 0, L_0x12ef29110; 1 drivers
+L_0x1200780e8 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
+v0x12ef1cf80_0 .net/2u *"_ivl_22", 7 0, L_0x1200780e8; 1 drivers
+v0x12ef1d010_0 .net *"_ivl_223", 0 0, L_0x12ef294a0; 1 drivers
+L_0x120078a78 .functor BUFT 1, C4<11111111>, C4<0>, C4<0>, C4<0>;
+v0x12ef1d0a0_0 .net/2u *"_ivl_224", 7 0, L_0x120078a78; 1 drivers
+L_0x120078ac0 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
+v0x12ef1d130_0 .net/2u *"_ivl_226", 7 0, L_0x120078ac0; 1 drivers
+v0x12ef1d1c0_0 .net *"_ivl_228", 7 0, L_0x12ef29360; 1 drivers
+v0x12ef1d270_0 .net *"_ivl_233", 0 0, L_0x12ef296d0; 1 drivers
+L_0x120078b08 .functor BUFT 1, C4<11111111>, C4<0>, C4<0>, C4<0>;
+v0x12ef1d320_0 .net/2u *"_ivl_234", 7 0, L_0x120078b08; 1 drivers
+L_0x120078b50 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
+v0x12ef1d3d0_0 .net/2u *"_ivl_236", 7 0, L_0x120078b50; 1 drivers
+v0x12ef1d480_0 .net *"_ivl_238", 7 0, L_0x12ef29540; 1 drivers
+v0x12ef1d530_0 .net *"_ivl_24", 0 0, L_0x12ef25200; 1 drivers
+v0x12ef1d5d0_0 .net *"_ivl_243", 0 0, L_0x12ef29910; 1 drivers
+L_0x120078b98 .functor BUFT 1, C4<11111111>, C4<0>, C4<0>, C4<0>;
+v0x12ef1d680_0 .net/2u *"_ivl_244", 7 0, L_0x120078b98; 1 drivers
+L_0x120078be0 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
+v0x12ef1d730_0 .net/2u *"_ivl_246", 7 0, L_0x120078be0; 1 drivers
+v0x12ef1d7e0_0 .net *"_ivl_248", 7 0, L_0x12ef29770; 1 drivers
+v0x12ef1d890_0 .net *"_ivl_253", 0 0, L_0x12ef29b60; 1 drivers
+L_0x120078c28 .functor BUFT 1, C4<11111111>, C4<0>, C4<0>, C4<0>;
+v0x12ef1d940_0 .net/2u *"_ivl_254", 7 0, L_0x120078c28; 1 drivers
+L_0x120078c70 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
+v0x12ef1d9f0_0 .net/2u *"_ivl_256", 7 0, L_0x120078c70; 1 drivers
+v0x12ef1daa0_0 .net *"_ivl_258", 7 0, L_0x12ef299b0; 1 drivers
+v0x12ef1db50_0 .net *"_ivl_264", 0 0, L_0x12ef29d00; 1 drivers
+L_0x120078cb8 .functor BUFT 1, C4<11111111>, C4<0>, C4<0>, C4<0>;
+v0x12ef1dc00_0 .net/2u *"_ivl_265", 7 0, L_0x120078cb8; 1 drivers
+L_0x120078d00 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
+v0x12ef1dcb0_0 .net/2u *"_ivl_267", 7 0, L_0x120078d00; 1 drivers
+v0x12ef1dd60_0 .net *"_ivl_269", 7 0, L_0x12ef29da0; 1 drivers
+v0x12ef1de10_0 .net *"_ivl_27", 0 0, L_0x12ef25360; 1 drivers
+L_0x120078d48 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0x12ef1deb0_0 .net/2u *"_ivl_271", 0 0, L_0x120078d48; 1 drivers
+v0x12ef1df60_0 .net *"_ivl_273", 0 0, L_0x12ef2a300; 1 drivers
+v0x12ef1e000_0 .net *"_ivl_275", 63 0, L_0x12ef2a3e0; 1 drivers
+L_0x120078d90 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0x12ef1e0b0_0 .net/2u *"_ivl_279", 0 0, L_0x120078d90; 1 drivers
+v0x12ef1e160_0 .net *"_ivl_281", 0 0, L_0x12ef2a0a0; 1 drivers
+L_0x120078dd8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0x12ef1e200_0 .net/2u *"_ivl_283", 0 0, L_0x120078dd8; 1 drivers
+v0x12ef1e2b0_0 .net *"_ivl_285", 0 0, L_0x12ef2a180; 1 drivers
+v0x12ef1e350_0 .net *"_ivl_288", 0 0, L_0x12ef2a630; 1 drivers
+L_0x120078e20 .functor BUFT 1, C4<10>, C4<0>, C4<0>, C4<0>;
+v0x12ef1e3f0_0 .net/2u *"_ivl_289", 1 0, L_0x120078e20; 1 drivers
+v0x12ef1e4a0_0 .net *"_ivl_29", 0 0, L_0x12ef25470; 1 drivers
+v0x12ef1e540_0 .net *"_ivl_291", 0 0, L_0x12ef2a720; 1 drivers
+L_0x120078e68 .functor BUFT 1, C4<11>, C4<0>, C4<0>, C4<0>;
+v0x12ef1e5e0_0 .net/2u *"_ivl_293", 1 0, L_0x120078e68; 1 drivers
+v0x12ef1e690_0 .net *"_ivl_295", 0 0, L_0x12ef2aaa0; 1 drivers
+v0x12ef1e730_0 .net *"_ivl_298", 0 0, L_0x12ef2a860; 1 drivers
+L_0x120078130 .functor BUFT 1, C4<00100000>, C4<0>, C4<0>, C4<0>;
+v0x12ef1e7d0_0 .net/2u *"_ivl_30", 7 0, L_0x120078130; 1 drivers
+v0x12ef1e880_0 .net *"_ivl_300", 0 0, L_0x12ef2a950; 1 drivers
+L_0x120078eb0 .functor BUFT 1, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0x12ef1e920_0 .net/2u *"_ivl_301", 63 0, L_0x120078eb0; 1 drivers
+L_0x120078ef8 .functor BUFT 1, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0x12ef1e9d0_0 .net/2u *"_ivl_307", 63 0, L_0x120078ef8; 1 drivers
+v0x12ef1ea80_0 .net *"_ivl_309", 0 0, L_0x12ef2ad50; 1 drivers
+L_0x120078f40 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0x12ef1eb20_0 .net/2u *"_ivl_311", 0 0, L_0x120078f40; 1 drivers
+L_0x120078f88 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0x12ef1ebd0_0 .net/2u *"_ivl_313", 0 0, L_0x120078f88; 1 drivers
+v0x12ef1ec80_0 .net *"_ivl_32", 0 0, L_0x12ef255a0; 1 drivers
+L_0x120078178 .functor BUFT 1, C4<00010000>, C4<0>, C4<0>, C4<0>;
+v0x12ef1ed20_0 .net/2u *"_ivl_34", 7 0, L_0x120078178; 1 drivers
+v0x12ef1edd0_0 .net *"_ivl_357", 2 0, L_0x12ef2b2b0; 1 drivers
+v0x12ef1ee80_0 .net *"_ivl_36", 0 0, L_0x12ef25680; 1 drivers
+v0x12ef1ef20_0 .net *"_ivl_39", 0 0, L_0x12ef257b0; 1 drivers
+v0x12ef1efc0_0 .net *"_ivl_41", 0 0, L_0x12ef258b0; 1 drivers
+L_0x1200781c0 .functor BUFT 1, C4<00110000>, C4<0>, C4<0>, C4<0>;
+v0x12ef1f060_0 .net/2u *"_ivl_42", 7 0, L_0x1200781c0; 1 drivers
+v0x12ef1f110_0 .net *"_ivl_44", 0 0, L_0x12ef259a0; 1 drivers
+L_0x120078208 .functor BUFT 1, C4<00100000>, C4<0>, C4<0>, C4<0>;
+v0x12ef1f1b0_0 .net/2u *"_ivl_46", 7 0, L_0x120078208; 1 drivers
+v0x12ef1f260_0 .net *"_ivl_48", 0 0, L_0x12ef25ac0; 1 drivers
+v0x12ef1f300_0 .net *"_ivl_5", 28 0, L_0x12ef24b40; 1 drivers
+v0x12ef1f3b0_0 .net *"_ivl_51", 0 0, L_0x12ef25c40; 1 drivers
+v0x12ef1f450_0 .net *"_ivl_53", 0 0, L_0x12ef25d50; 1 drivers
+L_0x120078250 .functor BUFT 1, C4<00110000>, C4<0>, C4<0>, C4<0>;
+v0x12ef1f4f0_0 .net/2u *"_ivl_54", 7 0, L_0x120078250; 1 drivers
+v0x12ef1f5a0_0 .net *"_ivl_56", 0 0, L_0x12ef25ec0; 1 drivers
+L_0x120078298 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
+v0x12ef1f640_0 .net/2u *"_ivl_58", 7 0, L_0x120078298; 1 drivers
+v0x12ef1f6f0_0 .net *"_ivl_60", 0 0, L_0x12ef25f60; 1 drivers
+v0x12ef1f790_0 .net *"_ivl_63", 0 0, L_0x12ef260b0; 1 drivers
+v0x12ef1f830_0 .net *"_ivl_65", 0 0, L_0x12ef261d0; 1 drivers
+L_0x1200782e0 .functor BUFT 1, C4<00110000>, C4<0>, C4<0>, C4<0>;
+v0x12ef1f8d0_0 .net/2u *"_ivl_66", 7 0, L_0x1200782e0; 1 drivers
+v0x12ef1f980_0 .net *"_ivl_68", 0 0, L_0x12ef26280; 1 drivers
+L_0x120078328 .functor BUFT 1, C4<00010000>, C4<0>, C4<0>, C4<0>;
+v0x12ef1fa20_0 .net/2u *"_ivl_70", 7 0, L_0x120078328; 1 drivers
+v0x12ef1fad0_0 .net *"_ivl_72", 0 0, L_0x12ef26360; 1 drivers
+v0x12ef1fb70_0 .net *"_ivl_75", 0 0, L_0x12ef26040; 1 drivers
+v0x12ef1fc10_0 .net *"_ivl_77", 0 0, L_0x12ef265c0; 1 drivers
+L_0x120078370 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0x12ef1fcb0_0 .net/2u *"_ivl_78", 0 0, L_0x120078370; 1 drivers
+L_0x120078010 .functor BUFT 1, C4<00100000>, C4<0>, C4<0>, C4<0>;
+v0x12ef1fd60_0 .net/2u *"_ivl_8", 7 0, L_0x120078010; 1 drivers
+L_0x1200783b8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0x12ef1fe10_0 .net/2u *"_ivl_80", 0 0, L_0x1200783b8; 1 drivers
+L_0x120078400 .functor BUFT 1, C4<0000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0x12ef1fec0_0 .net/2u *"_ivl_84", 27 0, L_0x120078400; 1 drivers
+v0x12ef1ff70_0 .net *"_ivl_86", 31 0, L_0x12ef267f0; 1 drivers
+L_0x120078448 .functor BUFT 1, C4<00100000>, C4<0>, C4<0>, C4<0>;
+v0x12ef20020_0 .net/2u *"_ivl_90", 7 0, L_0x120078448; 1 drivers
+v0x12ef200d0_0 .net *"_ivl_92", 0 0, L_0x12ef26aa0; 1 drivers
+L_0x120078490 .functor BUFT 1, C4<00110000>, C4<0>, C4<0>, C4<0>;
+v0x12ef20170_0 .net/2u *"_ivl_94", 7 0, L_0x120078490; 1 drivers
+v0x12ef20220_0 .net *"_ivl_96", 0 0, L_0x12ef26ce0; 1 drivers
+v0x12ef202c0_0 .net *"_ivl_99", 0 0, L_0x12ef25a40; 1 drivers
+v0x12ef20360_0 .var "add_value", 3 0;
+v0x12ef20410_0 .var "align_mask", 2 0;
+v0x12ef204c0_0 .net "aligned_addr", 31 0, L_0x12ef24c40; 1 drivers
+v0x12ef20570_0 .net "aligned_addr_l", 2 0, L_0x12ef24a50; 1 drivers
+v0x12ef20620_0 .var/i "array_ptr", 31 0;
+v0x12ef206d0_0 .var "banner_done", 0 0;
+v0x12ef20770_0 .var "boundary", 2 0;
+v0x12ef20820_0 .net "bstrb_mask", 63 0, L_0x12ef29e80; 1 drivers
+v0x12ef208d0_0 .var "cmd_reg", 7 0;
+v0x12ef20980_0 .var "comm_word_num", 4 0;
+v0x12ef20a30 .array "comm_words_hex", 79 0, 7 0;
+v0x12ef20ad0_0 .var "data_compare", 63 0;
+v0x12ef20b80_0 .net "data_err", 0 0, L_0x12ef2ab80; 1 drivers
+v0x12ef20c20_0 .var/i "data_err_cnt", 31 0;
+v0x12ef20cd0_0 .var "data_reg", 63 0;
+v0x12ef20d80_0 .var "err_resp", 1 0;
+v0x12ef20e30_0 .var "err_resp_reg", 1 0;
+v0x12ef20ee0 .array "file_array", 5000 0, 31 0;
+v0x12ef20f80_0 .var "file_array_tmp", 31 0;
+v0x12ef21030_0 .var "haddr_reg", 31 0;
+v0x12ef210e0_0 .var "htrans_reg", 1 0;
+v0x12ef21190_0 .var "hwdata_reg", 63 0;
+v0x12ef21240_0 .var "hwrite_reg", 0 0;
+v0x12ef212e0_0 .net "i_haddr", 31 0, L_0x12ef26ef0; 1 drivers
+v0x12ef21390_0 .var "i_hbstrb", 7 0;
+v0x12ef21440_0 .var "i_htrans", 1 0;
+v0x12ef214f0_0 .net "i_hwdata", 63 0, L_0x12ef2ae60; 1 drivers
+v0x12ef215a0_0 .net "i_hwrite", 0 0, L_0x12ef285e0; 1 drivers
+v0x12ef21640_0 .net "incr_addr", 31 0, L_0x12ef269a0; 1 drivers
+v0x12ef216f0_0 .net "mask", 63 0, L_0x12ef2a590; 1 drivers
+v0x12ef217a0_0 .var "mask_reg", 63 0;
+v0x12ef21850_0 .var "next_poll_count", 31 0;
+v0x12ef21900_0 .var "next_poll_state", 1 0;
+v0x12ef219b0_0 .net "non_zero", 0 0, L_0x12ef26670; 1 drivers
+v0x12ef21a50_0 .var "poll_count", 31 0;
+v0x12ef21b00_0 .var/i "poll_err_cnt", 31 0;
+v0x12ef21bb0_0 .var "poll_state", 1 0;
+v0x12ef21c60_0 .net "rd_next", 0 0, L_0x12ef279b0; 1 drivers
+v0x12ef21d00_0 .var "size_reg", 2 0;
+v0x12ef21db0_0 .var "skip_seq", 0 0;
+v0x12ef21e50_0 .var/i "slave_resp_cnt", 31 0;
+v0x12ef21f00_0 .var "stim_end", 0 0;
+v0x12ef21fa0_0 .var "stim_end_data", 0 0;
+v0x12ef22040_0 .var "stim_end_data_reg", 0 0;
+v0x12ef220e0_0 .var/i "stim_line_num", 31 0;
+v0x12ef22190_0 .var/i "stim_line_reg", 31 0;
+v0x12ef22240_0 .var "timeout", 31 0;
+v0x12ef222f0_0 .var "timeout_reg", 31 0;
+v0x12ef223a0_0 .var "unalign", 0 0;
+v0x12ef22440_0 .var "use_bstrb_flag", 0 0;
+v0x12ef224e0_0 .var "vec_addr", 31 0;
+v0x12ef22590_0 .var "vec_bstrb", 7 0;
+v0x12ef22640_0 .var "vec_burst", 2 0;
+v0x12ef226f0_0 .var "vec_cmd", 7 0;
+v0x12ef227a0_0 .var "vec_data", 63 0;
+v0x12ef22850_0 .var "vec_data_mask", 63 0;
+v0x12ef22900_0 .var "vec_dir", 0 0;
+v0x12ef229a0_0 .var "vec_lock", 0 0;
+v0x12ef22a40_0 .var "vec_prot", 5 0;
+v0x12ef22af0_0 .var "vec_size", 2 0;
+v0x12ef22ba0_0 .var "wait_rdy", 0 0;
+v0x12ef22c40_0 .var "wrapped_addr", 31 0;
+E_0x12ef17940/0 .event edge, v0x12ef22240_0, v0x12ef21a50_0, v0x12ef20b80_0, v0x12ef226f0_0;
+E_0x12ef17940/1 .event edge, v0x12ef21bb0_0;
+E_0x12ef17940 .event/or E_0x12ef17940/0, E_0x12ef17940/1;
+E_0x12ef179b0/0 .event edge, v0x12ef21240_0, v0x12ef210e0_0, v0x12ef217a0_0, v0x12ef16ef0_0;
+E_0x12ef179b0/1 .event edge, v0x12ef1a900_0, v0x12ef20cd0_0;
+E_0x12ef179b0 .event/or E_0x12ef179b0/0, E_0x12ef179b0/1;
+E_0x12ef17a10 .event edge, v0x12ef22590_0, v0x12ef22440_0, v0x12ef22af0_0, L_0x12ef2b2b0;
+E_0x12ef17a80/0 .event edge, v0x12ef21900_0, v0x12ef16fa0_0, v0x12ef1a900_0, v0x12ef20e30_0;
+E_0x12ef17a80/1 .event edge, v0x12ef226f0_0;
+E_0x12ef17a80 .event/or E_0x12ef17a80/0, E_0x12ef17a80/1;
+E_0x12ef17ae0 .event edge, v0x12ef204c0_0, v0x12ef21640_0, v0x12ef20770_0;
+E_0x12ef17b40 .event edge, v0x12ef22640_0, v0x12ef22af0_0;
+E_0x12ef17b70 .event edge, v0x12ef219b0_0, v0x12ef22af0_0;
+E_0x12ef17b10 .event edge, v0x12ef22af0_0;
+E_0x12ef17c00 .event posedge, v0x12ef16d90_0;
+L_0x12ef24990 .part v0x12ef21030_0, 0, 3;
+L_0x12ef24b40 .part v0x12ef21030_0, 3, 29;
+L_0x12ef24c40 .concat [ 3 29 0 0], L_0x12ef24a50, L_0x12ef24b40;
+L_0x12ef24d80 .cmp/eeq 8, v0x12ef226f0_0, L_0x120078010;
+L_0x12ef24ea0 .cmp/eeq 8, v0x12ef208d0_0, L_0x120078058;
+L_0x12ef250e0 .cmp/eeq 8, v0x12ef226f0_0, L_0x1200780a0;
+L_0x12ef25200 .cmp/eeq 8, v0x12ef208d0_0, L_0x1200780e8;
+L_0x12ef255a0 .cmp/eeq 8, v0x12ef226f0_0, L_0x120078130;
+L_0x12ef25680 .cmp/eeq 8, v0x12ef208d0_0, L_0x120078178;
+L_0x12ef259a0 .cmp/eeq 8, v0x12ef226f0_0, L_0x1200781c0;
+L_0x12ef25ac0 .cmp/eeq 8, v0x12ef208d0_0, L_0x120078208;
+L_0x12ef25ec0 .cmp/eeq 8, v0x12ef226f0_0, L_0x120078250;
+L_0x12ef25f60 .cmp/eeq 8, v0x12ef208d0_0, L_0x120078298;
+L_0x12ef26280 .cmp/eeq 8, v0x12ef226f0_0, L_0x1200782e0;
+L_0x12ef26360 .cmp/eeq 8, v0x12ef208d0_0, L_0x120078328;
+L_0x12ef26670 .functor MUXZ 1, L_0x1200783b8, L_0x120078370, L_0x12ef265c0, C4<>;
+L_0x12ef267f0 .concat [ 4 28 0 0], v0x12ef20360_0, L_0x120078400;
+L_0x12ef269a0 .arith/sum 32, L_0x12ef24c40, L_0x12ef267f0;
+L_0x12ef26aa0 .cmp/eeq 8, v0x12ef226f0_0, L_0x120078448;
+L_0x12ef26ce0 .cmp/eeq 8, v0x12ef226f0_0, L_0x120078490;
+L_0x12ef26ef0 .functor MUXZ 32, v0x12ef224e0_0, v0x12ef22c40_0, L_0x12ef25a40, C4<>;
+L_0x12ef270c0 .cmp/eeq 2, v0x12ef21900_0, L_0x1200784d8;
+L_0x12ef271a0 .cmp/eeq 1, o0x120040520, L_0x120078520;
+L_0x12ef26f90 .cmp/eeq 1, v0x12ef22ba0_0, L_0x120078568;
+L_0x12ef273a0 .cmp/eeq 8, v0x12ef226f0_0, L_0x1200785b0;
+L_0x12ef27280 .cmp/eeq 8, v0x12ef226f0_0, L_0x1200785f8;
+L_0x12ef279b0 .functor MUXZ 1, L_0x120078688, L_0x120078640, L_0x12ef27940, C4<>;
+L_0x12ef27c80 .cmp/eeq 8, v0x12ef226f0_0, L_0x1200786d0;
+L_0x12ef27d20 .cmp/eeq 8, v0x12ef226f0_0, L_0x120078718;
+L_0x12ef27f40 .cmp/eeq 8, v0x12ef226f0_0, L_0x120078760;
+L_0x12ef27fe0 .cmp/eeq 8, v0x12ef226f0_0, L_0x1200787a8;
+L_0x12ef27dc0 .cmp/eeq 1, v0x12ef22900_0, L_0x1200787f0;
+L_0x12ef28430 .functor MUXZ 1, L_0x120078880, L_0x120078838, L_0x12ef283c0, C4<>;
+L_0x12ef285e0 .functor MUXZ 1, L_0x12ef28430, v0x12ef21240_0, L_0x12ef27eb0, C4<>;
+L_0x12ef28aa0 .part v0x12ef21390_0, 0, 1;
+L_0x12ef26bd0 .functor MUXZ 8, L_0x120078910, L_0x1200788c8, L_0x12ef28aa0, C4<>;
+L_0x12ef29070 .part v0x12ef21390_0, 1, 1;
+L_0x12ef28d50 .functor MUXZ 8, L_0x1200789a0, L_0x120078958, L_0x12ef29070, C4<>;
+L_0x12ef29240 .part v0x12ef21390_0, 2, 1;
+L_0x12ef29110 .functor MUXZ 8, L_0x120078a30, L_0x1200789e8, L_0x12ef29240, C4<>;
+L_0x12ef294a0 .part v0x12ef21390_0, 3, 1;
+L_0x12ef29360 .functor MUXZ 8, L_0x120078ac0, L_0x120078a78, L_0x12ef294a0, C4<>;
+L_0x12ef296d0 .part v0x12ef21390_0, 4, 1;
+L_0x12ef29540 .functor MUXZ 8, L_0x120078b50, L_0x120078b08, L_0x12ef296d0, C4<>;
+L_0x12ef29910 .part v0x12ef21390_0, 5, 1;
+L_0x12ef29770 .functor MUXZ 8, L_0x120078be0, L_0x120078b98, L_0x12ef29910, C4<>;
+L_0x12ef29b60 .part v0x12ef21390_0, 6, 1;
+L_0x12ef299b0 .functor MUXZ 8, L_0x120078c70, L_0x120078c28, L_0x12ef29b60, C4<>;
+LS_0x12ef29e80_0_0 .concat8 [ 8 8 8 8], L_0x12ef26bd0, L_0x12ef28d50, L_0x12ef29110, L_0x12ef29360;
+LS_0x12ef29e80_0_4 .concat8 [ 8 8 8 8], L_0x12ef29540, L_0x12ef29770, L_0x12ef299b0, L_0x12ef29da0;
+L_0x12ef29e80 .concat8 [ 32 32 0 0], LS_0x12ef29e80_0_0, LS_0x12ef29e80_0_4;
+L_0x12ef29d00 .part v0x12ef21390_0, 7, 1;
+L_0x12ef29da0 .functor MUXZ 8, L_0x120078d00, L_0x120078cb8, L_0x12ef29d00, C4<>;
+L_0x12ef2a300 .cmp/eeq 1, v0x12ef22440_0, L_0x120078d48;
+L_0x12ef2a590 .functor MUXZ 64, v0x12ef22850_0, L_0x12ef2a3e0, L_0x12ef2a300, C4<>;
+L_0x12ef2a0a0 .cmp/eeq 1, L_0x12ef285e0, L_0x120078d90;
+L_0x12ef2a180 .cmp/eeq 1, o0x120040520, L_0x120078dd8;
+L_0x12ef2a720 .cmp/eeq 2, v0x12ef21440_0, L_0x120078e20;
+L_0x12ef2aaa0 .cmp/eeq 2, v0x12ef21440_0, L_0x120078e68;
+L_0x12ef2ae60 .functor MUXZ 64, L_0x120078eb0, v0x12ef227a0_0, L_0x12ef2a950, C4<>;
+L_0x12ef2ad50 .cmp/nee 64, v0x12ef20ad0_0, L_0x120078ef8;
+L_0x12ef2ab80 .functor MUXZ 1, L_0x120078f88, L_0x120078f40, L_0x12ef2ad50, C4<>;
+L_0x12ef2b2b0 .part L_0x12ef26ef0, 0, 3;
+S_0x12ef17c90 .scope begin, "p_align_mask_comb" "p_align_mask_comb" 6 977, 6 977 0, S_0x12ef17400;
+ .timescale 0 0;
+S_0x12ef17e60 .scope begin, "p_banner_bhav" "p_banner_bhav" 6 310, 6 310 0, S_0x12ef17400;
+ .timescale 0 0;
+S_0x12ef18030 .scope begin, "p_boundary_value_comb" "p_boundary_value_comb" 6 1050, 6 1050 0, S_0x12ef17400;
+ .timescale 0 0;
+S_0x12ef181f0 .scope begin, "p_bstrb_comb" "p_bstrb_comb" 6 1286, 6 1286 0, S_0x12ef17400;
+ .timescale 0 0;
+S_0x12ef183b0 .scope begin, "p_calc_add_value_comb" "p_calc_add_value_comb" 6 1018, 6 1018 0, S_0x12ef17400;
+ .timescale 0 0;
+S_0x12ef185b0 .scope begin, "p_cmd_read_bhav" "p_cmd_read_bhav" 6 484, 6 484 0, S_0x12ef17400;
+ .timescale 0 0;
+v0x12ef18770_0 .var/i "i", 31 0;
+v0x12ef18800_0 .var "loop_number", 31 0;
+v0x12ef18890_0 .var/i "stim_line_tmp", 31 0;
+v0x12ef18940_0 .var "use_bstrb_tmp", 0 0;
+S_0x12ef189e0 .scope begin, "p_data_compare_comb" "p_data_compare_comb" 6 1402, 6 1402 0, S_0x12ef17400;
+ .timescale 0 0;
+S_0x12ef18ba0 .scope begin, "p_htrans_control_comb" "p_htrans_control_comb" 6 1220, 6 1220 0, S_0x12ef17400;
+ .timescale 0 0;
+S_0x12ef18d60 .scope begin, "p_open_file_bhav" "p_open_file_bhav" 6 296, 6 296 0, S_0x12ef17400;
+ .timescale 0 0;
+S_0x12ef18fa0 .scope begin, "p_poll_state_comb" "p_poll_state_comb" 6 1424, 6 1424 0, S_0x12ef17400;
+ .timescale 0 0;
+S_0x12ef19160 .scope begin, "p_poll_state_seq" "p_poll_state_seq" 6 1474, 6 1474 0, S_0x12ef17400;
+ .timescale 0 0;
+S_0x12ef19320 .scope begin, "p_reg_file_seq" "p_reg_file_seq" 6 908, 6 908 0, S_0x12ef17400;
+ .timescale 0 0;
+S_0x12ef194e0 .scope begin, "p_reg_outputs_seq" "p_reg_outputs_seq" 6 956, 6 956 0, S_0x12ef17400;
+ .timescale 0 0;
+S_0x12ef196a0 .scope begin, "p_reg_wdata_seq" "p_reg_wdata_seq" 6 1388, 6 1388 0, S_0x12ef17400;
+ .timescale 0 0;
+S_0x12ef19860 .scope begin, "p_report_errors_bhav" "p_report_errors_bhav" 6 335, 6 335 0, S_0x12ef17400;
+ .timescale 0 0;
+S_0x12ef19a20 .scope begin, "p_simulation_end" "p_simulation_end" 6 864, 6 864 0, S_0x12ef17400;
+ .timescale 0 0;
+S_0x12ef19be0 .scope begin, "p_stim_end_reg" "p_stim_end_reg" 6 942, 6 942 0, S_0x12ef17400;
+ .timescale 0 0;
+S_0x12ef19ea0 .scope begin, "p_wrapped_addr_comb" "p_wrapped_addr_comb" 6 1114, 6 1114 0, S_0x12ef17400;
+ .timescale 0 0;
+S_0x12ef1a060 .scope task, "tsk_simulation_comment" "tsk_simulation_comment" 6 271, 6 271 0, S_0x12ef17400;
+ .timescale 0 0;
+v0x12ef1a220_0 .var/i "c_index", 31 0;
+TD_cmsdk_ahb_fileread_master32.u_ahb_filereadcore.tsk_simulation_comment ;
+ %vpi_call/w 6 274 "$write", "%d %s ", $time, P_0x12ef17610 {0 0 0};
+ %pushi/vec4 0, 0, 32;
+ %store/vec4 v0x12ef1a220_0, 0, 32;
+T_0.0 ;
+ %load/vec4 v0x12ef1a220_0;
+ %load/vec4 v0x12ef20980_0;
+ %pad/u 32;
+ %muli 4, 0, 32;
+ %cmp/u;
+ %jmp/0xz T_0.1, 5;
+ %ix/getv/s 4, v0x12ef1a220_0;
+ %load/vec4a v0x12ef20a30, 4;
+ %cmpi/ne 0, 0, 8;
+ %jmp/0xz T_0.2, 6;
+ %vpi_call/w 6 283 "$write", "%s", &A<v0x12ef20a30, v0x12ef1a220_0 > {0 0 0};
+T_0.2 ;
+ %load/vec4 v0x12ef1a220_0;
+ %addi 1, 0, 32;
+ %store/vec4 v0x12ef1a220_0, 0, 32;
+ %jmp T_0.0;
+T_0.1 ;
+ %vpi_call/w 6 286 "$display", "\000" {0 0 0};
+ %end;
+ .scope S_0x12ef05380;
+T_1 ;
+ %wait E_0x12ef04f90;
+ %load/vec4 v0x12ef15c70_0;
+ %inv;
+ %flag_set/vec4 8;
+ %jmp/0xz T_1.0, 8;
+ %pushi/vec4 1, 0, 2;
+ %assign/vec4 v0x12ef16470_0, 0;
+ %jmp T_1.1;
+T_1.0 ;
+ %load/vec4 v0x12ef163c0_0;
+ %assign/vec4 v0x12ef16470_0, 0;
+T_1.1 ;
+ %jmp T_1;
+ .thread T_1;
+ .scope S_0x12ef17400;
+T_2 ;
+ %fork t_1, S_0x12ef18d60;
+ %jmp t_0;
+ .scope S_0x12ef18d60;
+t_1 ;
+ %vpi_call/w 6 299 "$display", "%d %s Reading stimulus file %s", $time, P_0x12ef17610, P_0x12ef175d0 {0 0 0};
+ %vpi_call/w 6 300 "$readmemh", P_0x12ef175d0, v0x12ef20ee0 {0 0 0};
+ %end;
+ .scope S_0x12ef17400;
+t_0 %join;
+ %end;
+ .thread T_2;
+ .scope S_0x12ef17400;
+T_3 ;
+ %wait E_0x12ef16910;
+ %fork t_3, S_0x12ef17e60;
+ %jmp t_2;
+ .scope S_0x12ef17e60;
+t_3 ;
+ %load/vec4 v0x12ef1a7d0_0;
+ %cmpi/ne 1, 0, 1;
+ %jmp/0xz T_3.0, 6;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x12ef206d0_0, 0;
+ %jmp T_3.1;
+T_3.0 ;
+ %load/vec4 v0x12ef206d0_0;
+ %cmpi/ne 1, 0, 1;
+ %jmp/0xz T_3.2, 6;
+ %pushi/vec4 1, 0, 1;
+ %assign/vec4 v0x12ef206d0_0, 0;
+ %vpi_call/w 6 317 "$display", "%d %s", $time, P_0x12ef17610 {0 0 0};
+ %vpi_call/w 6 318 "$write", " " {0 0 0};
+ %vpi_call/w 6 319 "$display", " ************************************************" {0 0 0};
+ %vpi_call/w 6 320 "$write", " " {0 0 0};
+ %vpi_call/w 6 321 "$display", " **** ARM AMBA Design Kit File Reader Master" {0 0 0};
+ %vpi_call/w 6 322 "$write", " " {0 0 0};
+ %vpi_call/w 6 323 "$display", " **** (C) ARM Limited 2000-2002" {0 0 0};
+ %vpi_call/w 6 324 "$write", " " {0 0 0};
+ %vpi_call/w 6 325 "$display", " ************************************************" {0 0 0};
+T_3.2 ;
+T_3.1 ;
+ %end;
+ .scope S_0x12ef17400;
+t_2 %join;
+ %jmp T_3;
+ .thread T_3;
+ .scope S_0x12ef17400;
+T_4 ;
+ %wait E_0x12ef16910;
+ %fork t_5, S_0x12ef19860;
+ %jmp t_4;
+ .scope S_0x12ef19860;
+t_5 ;
+ %load/vec4 v0x12ef1a7d0_0;
+ %cmpi/ne 1, 0, 1;
+ %jmp/0xz T_4.0, 6;
+ %pushi/vec4 0, 0, 32;
+ %store/vec4 v0x12ef20c20_0, 0, 32;
+ %pushi/vec4 0, 0, 32;
+ %store/vec4 v0x12ef21e50_0, 0, 32;
+ %pushi/vec4 0, 0, 32;
+ %store/vec4 v0x12ef21b00_0, 0, 32;
+ %jmp T_4.1;
+T_4.0 ;
+ %load/vec4 v0x12ef1a720_0;
+ %pushi/vec4 1, 0, 1;
+ %cmp/e;
+ %flag_get/vec4 6;
+ %load/vec4 v0x12ef21db0_0;
+ %pushi/vec4 1, 0, 1;
+ %cmp/ne;
+ %flag_get/vec4 6;
+ %and;
+ %flag_set/vec4 8;
+ %jmp/0xz T_4.2, 8;
+ %load/vec4 v0x12ef1a900_0;
+ %pushi/vec4 4, 0, 3;
+ %cmp/e;
+ %flag_get/vec4 6;
+ %load/vec4 v0x12ef20e30_0;
+ %pushi/vec4 3, 0, 2;
+ %cmp/ne;
+ %flag_get/vec4 6;
+ %and;
+ %flag_set/vec4 8;
+ %jmp/0xz T_4.4, 8;
+ %vpi_call/w 6 349 "$display", "%d %s #ERROR# Slave responded with an unexpected XFAIL.", $time, P_0x12ef17610 {0 0 0};
+ %vpi_call/w 6 350 "$write", " " {0 0 0};
+ %vpi_call/w 6 351 "$display", " Stimulus Line: %d", v0x12ef22190_0 {0 0 0};
+ %vpi_call/w 6 352 "$write", " " {0 0 0};
+ %vpi_call/w 6 353 "$display", " Address = %h", v0x12ef21030_0 {0 0 0};
+ %load/vec4 v0x12ef21e50_0;
+ %addi 1, 0, 32;
+ %store/vec4 v0x12ef21e50_0, 0, 32;
+ %jmp T_4.5;
+T_4.4 ;
+ %load/vec4 v0x12ef1a900_0;
+ %pushi/vec4 4, 0, 3;
+ %cmp/ne;
+ %flag_get/vec4 6;
+ %load/vec4 v0x12ef20e30_0;
+ %pushi/vec4 3, 0, 2;
+ %cmp/e;
+ %flag_get/vec4 6;
+ %and;
+ %flag_set/vec4 8;
+ %jmp/0xz T_4.6, 8;
+ %vpi_call/w 6 360 "$display", "%d %s #ERROR# Expected XFAIL response was not received from Slave.", $time, P_0x12ef17610 {0 0 0};
+ %vpi_call/w 6 361 "$write", " " {0 0 0};
+ %vpi_call/w 6 362 "$display", " Stimulus Line: %d", v0x12ef22190_0 {0 0 0};
+ %vpi_call/w 6 363 "$write", " " {0 0 0};
+ %vpi_call/w 6 364 "$display", " Address = %h", v0x12ef21030_0 {0 0 0};
+ %load/vec4 v0x12ef21e50_0;
+ %addi 1, 0, 32;
+ %store/vec4 v0x12ef21e50_0, 0, 32;
+ %jmp T_4.7;
+T_4.6 ;
+ %load/vec4 v0x12ef1a900_0;
+ %pushi/vec4 0, 0, 3;
+ %cmp/ne;
+ %flag_get/vec4 6;
+ %load/vec4 v0x12ef20e30_0;
+ %pushi/vec4 0, 0, 2;
+ %cmp/e;
+ %flag_get/vec4 6;
+ %and;
+ %flag_set/vec4 8;
+ %jmp/0xz T_4.8, 8;
+ %vpi_call/w 6 371 "$display", "%d %s #ERROR# Expected Okay response was not received from Slave.", $time, P_0x12ef17610 {0 0 0};
+ %vpi_call/w 6 372 "$write", " " {0 0 0};
+ %vpi_call/w 6 373 "$display", " Stimulus Line: %d", v0x12ef22190_0 {0 0 0};
+ %vpi_call/w 6 374 "$write", " " {0 0 0};
+ %vpi_call/w 6 375 "$display", " Address = %h", v0x12ef21030_0 {0 0 0};
+ %load/vec4 v0x12ef21e50_0;
+ %addi 1, 0, 32;
+ %store/vec4 v0x12ef21e50_0, 0, 32;
+ %jmp T_4.9;
+T_4.8 ;
+ %load/vec4 v0x12ef1a900_0;
+ %pushi/vec4 1, 0, 3;
+ %cmp/ne;
+ %flag_get/vec4 6;
+ %load/vec4 v0x12ef20e30_0;
+ %pushi/vec4 1, 0, 2;
+ %cmp/e;
+ %flag_get/vec4 6;
+ %load/vec4 v0x12ef20e30_0;
+ %pushi/vec4 2, 0, 2;
+ %cmp/e;
+ %flag_get/vec4 6;
+ %or;
+ %and;
+ %flag_set/vec4 8;
+ %jmp/0xz T_4.10, 8;
+ %vpi_call/w 6 383 "$display", "%d %s #ERROR# Expected Error response was not received from Slave.", $time, P_0x12ef17610 {0 0 0};
+ %vpi_call/w 6 384 "$write", " " {0 0 0};
+ %vpi_call/w 6 385 "$display", " Stimulus Line: %d", v0x12ef22190_0 {0 0 0};
+ %vpi_call/w 6 386 "$write", " " {0 0 0};
+ %vpi_call/w 6 387 "$display", " Address = %h", v0x12ef21030_0 {0 0 0};
+ %load/vec4 v0x12ef21e50_0;
+ %addi 1, 0, 32;
+ %store/vec4 v0x12ef21e50_0, 0, 32;
+ %jmp T_4.11;
+T_4.10 ;
+ %load/vec4 v0x12ef20b80_0;
+ %pushi/vec4 1, 0, 1;
+ %cmp/e;
+ %flag_get/vec4 6;
+ %load/vec4 v0x12ef21a50_0;
+ %pushi/vec4 1, 0, 32;
+ %cmp/e;
+ %flag_get/vec4 6;
+ %and;
+ %flag_set/vec4 8;
+ %jmp/0xz T_4.12, 8;
+ %vpi_call/w 6 394 "$display", "%d %s #ERROR# Poll command timed out after %d repeats.", $time, P_0x12ef17610, v0x12ef222f0_0 {0 0 0};
+ %vpi_call/w 6 395 "$write", " " {0 0 0};
+ %vpi_call/w 6 396 "$display", " Stimulus Line: %d", v0x12ef22190_0 {0 0 0};
+ %vpi_call/w 6 397 "$write", " " {0 0 0};
+ %vpi_call/w 6 398 "$display", " Address = %h", v0x12ef21030_0 {0 0 0};
+ %load/vec4 v0x12ef21d00_0;
+ %cmpi/e 3, 0, 3;
+ %jmp/0xz T_4.14, 6;
+ %vpi_call/w 6 403 "$write", " " {0 0 0};
+ %vpi_call/w 6 404 "$display", " Actual data = %h", v0x12ef1a680_0 {0 0 0};
+ %vpi_call/w 6 405 "$write", " " {0 0 0};
+ %vpi_call/w 6 406 "$display", " Expected data = %h", v0x12ef20cd0_0 {0 0 0};
+ %vpi_call/w 6 407 "$write", " " {0 0 0};
+ %vpi_call/w 6 408 "$display", " Mask = %h", v0x12ef217a0_0 {0 0 0};
+ %jmp T_4.15;
+T_4.14 ;
+ %load/vec4 v0x12ef21030_0;
+ %parti/s 1, 2, 3;
+ %cmpi/e 1, 0, 1;
+ %jmp/0xz T_4.16, 6;
+ %vpi_call/w 6 412 "$write", " " {0 0 0};
+ %vpi_call/w 6 413 "$display", " Actual data = %h", &PV<v0x12ef1a680_0, 32, 32> {0 0 0};
+ %vpi_call/w 6 414 "$write", " " {0 0 0};
+ %vpi_call/w 6 415 "$display", " Expected data = %h", &PV<v0x12ef20cd0_0, 32, 32> {0 0 0};
+ %vpi_call/w 6 416 "$write", " " {0 0 0};
+ %vpi_call/w 6 417 "$display", " Mask = %h", &PV<v0x12ef217a0_0, 32, 32> {0 0 0};
+ %jmp T_4.17;
+T_4.16 ;
+ %vpi_call/w 6 421 "$write", " " {0 0 0};
+ %vpi_call/w 6 422 "$display", " Actual data = %h", &PV<v0x12ef1a680_0, 0, 32> {0 0 0};
+ %vpi_call/w 6 423 "$write", " " {0 0 0};
+ %vpi_call/w 6 424 "$display", " Expected data = %h", &PV<v0x12ef20cd0_0, 0, 32> {0 0 0};
+ %vpi_call/w 6 425 "$write", " " {0 0 0};
+ %vpi_call/w 6 426 "$display", " Mask = %h", &PV<v0x12ef217a0_0, 0, 32> {0 0 0};
+T_4.17 ;
+T_4.15 ;
+ %load/vec4 v0x12ef21b00_0;
+ %addi 1, 0, 32;
+ %store/vec4 v0x12ef21b00_0, 0, 32;
+ %jmp T_4.13;
+T_4.12 ;
+ %load/vec4 v0x12ef20b80_0;
+ %pushi/vec4 1, 0, 1;
+ %cmp/e;
+ %flag_get/vec4 6;
+ %load/vec4 v0x12ef21bb0_0;
+ %pushi/vec4 0, 0, 2;
+ %cmp/e;
+ %flag_get/vec4 6;
+ %and;
+ %flag_set/vec4 8;
+ %jmp/0xz T_4.18, 8;
+ %vpi_call/w 6 435 "$display", "%d %s #ERROR# Data received did not match expectation.", $time, P_0x12ef17610 {0 0 0};
+ %vpi_call/w 6 436 "$write", " " {0 0 0};
+ %vpi_call/w 6 437 "$display", " Stimulus Line: %d", v0x12ef22190_0 {0 0 0};
+ %vpi_call/w 6 438 "$write", " " {0 0 0};
+ %vpi_call/w 6 439 "$display", " Address = %h", v0x12ef21030_0 {0 0 0};
+ %load/vec4 v0x12ef21d00_0;
+ %cmpi/e 3, 0, 3;
+ %jmp/0xz T_4.20, 6;
+ %vpi_call/w 6 444 "$write", " " {0 0 0};
+ %vpi_call/w 6 445 "$display", " Actual data = %h", v0x12ef1a680_0 {0 0 0};
+ %vpi_call/w 6 446 "$write", " " {0 0 0};
+ %vpi_call/w 6 447 "$display", " Expected data = %h", v0x12ef20cd0_0 {0 0 0};
+ %vpi_call/w 6 448 "$write", " " {0 0 0};
+ %vpi_call/w 6 449 "$display", " Mask = %h", v0x12ef217a0_0 {0 0 0};
+ %jmp T_4.21;
+T_4.20 ;
+ %load/vec4 v0x12ef21030_0;
+ %parti/s 1, 2, 3;
+ %cmpi/e 1, 0, 1;
+ %jmp/0xz T_4.22, 6;
+ %vpi_call/w 6 453 "$write", " " {0 0 0};
+ %vpi_call/w 6 454 "$display", " Actual data = %h", &PV<v0x12ef1a680_0, 32, 32> {0 0 0};
+ %vpi_call/w 6 455 "$write", " " {0 0 0};
+ %vpi_call/w 6 456 "$display", " Expected data = %h", &PV<v0x12ef20cd0_0, 32, 32> {0 0 0};
+ %vpi_call/w 6 457 "$write", " " {0 0 0};
+ %vpi_call/w 6 458 "$display", " Mask = %h", &PV<v0x12ef217a0_0, 32, 32> {0 0 0};
+ %jmp T_4.23;
+T_4.22 ;
+ %vpi_call/w 6 462 "$write", " " {0 0 0};
+ %vpi_call/w 6 463 "$display", " Actual data = %h", &PV<v0x12ef1a680_0, 0, 32> {0 0 0};
+ %vpi_call/w 6 464 "$write", " " {0 0 0};
+ %vpi_call/w 6 465 "$display", " Expected data = %h", &PV<v0x12ef20cd0_0, 0, 32> {0 0 0};
+ %vpi_call/w 6 466 "$write", " " {0 0 0};
+ %vpi_call/w 6 467 "$display", " Mask = %h", &PV<v0x12ef217a0_0, 0, 32> {0 0 0};
+T_4.23 ;
+T_4.21 ;
+ %load/vec4 v0x12ef20c20_0;
+ %addi 1, 0, 32;
+ %store/vec4 v0x12ef20c20_0, 0, 32;
+T_4.18 ;
+T_4.13 ;
+T_4.11 ;
+T_4.9 ;
+T_4.7 ;
+T_4.5 ;
+T_4.2 ;
+T_4.1 ;
+ %end;
+ .scope S_0x12ef17400;
+t_4 %join;
+ %jmp T_4;
+ .thread T_4;
+ .scope S_0x12ef17400;
+T_5 ;
+ %wait E_0x12ef16910;
+ %fork t_7, S_0x12ef185b0;
+ %jmp t_6;
+ .scope S_0x12ef185b0;
+t_7 ;
+ %load/vec4 v0x12ef1a7d0_0;
+ %cmpi/ne 1, 0, 1;
+ %jmp/0xz T_5.0, 6;
+ %pushi/vec4 64, 0, 8;
+ %assign/vec4 v0x12ef226f0_0, 0;
+ %pushi/vec4 0, 0, 32;
+ %assign/vec4 v0x12ef224e0_0, 0;
+ %pushi/vec4 0, 0, 64;
+ %assign/vec4 v0x12ef227a0_0, 0;
+ %pushi/vec4 4294967295, 0, 32;
+ %concati/vec4 4294967295, 0, 32;
+ %assign/vec4 v0x12ef22850_0, 0;
+ %pushi/vec4 0, 0, 3;
+ %assign/vec4 v0x12ef22af0_0, 0;
+ %pushi/vec4 0, 0, 3;
+ %assign/vec4 v0x12ef22640_0, 0;
+ %pushi/vec4 0, 0, 6;
+ %assign/vec4 v0x12ef22a40_0, 0;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x12ef22900_0, 0;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x12ef229a0_0, 0;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x12ef22ba0_0, 0;
+ %pushi/vec4 0, 0, 8;
+ %assign/vec4 v0x12ef22590_0, 0;
+ %pushi/vec4 1, 0, 1;
+ %assign/vec4 v0x12ef22440_0, 0;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x12ef223a0_0, 0;
+ %pushi/vec4 0, 0, 2;
+ %assign/vec4 v0x12ef20d80_0, 0;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x12ef21db0_0, 0;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x12ef21f00_0, 0;
+ %pushi/vec4 0, 0, 32;
+ %store/vec4 v0x12ef18800_0, 0, 32;
+ %pushi/vec4 0, 0, 32;
+ %assign/vec4 v0x12ef22240_0, 0;
+ %pushi/vec4 0, 0, 32;
+ %assign/vec4 v0x12ef220e0_0, 0;
+ %pushi/vec4 0, 0, 32;
+ %store/vec4 v0x12ef18890_0, 0, 32;
+ %pushi/vec4 0, 0, 32;
+ %store/vec4 v0x12ef20620_0, 0, 32;
+ %pushi/vec4 0, 0, 32;
+ %store/vec4 v0x12ef20f80_0, 0, 32;
+ %jmp T_5.1;
+T_5.0 ;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x12ef21db0_0, 0;
+ %load/vec4 v0x12ef220e0_0;
+ %store/vec4 v0x12ef18890_0, 0, 32;
+ %load/vec4 v0x12ef22440_0;
+ %store/vec4 v0x12ef18940_0, 0, 1;
+ %load/vec4 v0x12ef21c60_0;
+ %cmpi/e 1, 0, 1;
+ %jmp/0xz T_5.2, 6;
+ %load/vec4 v0x12ef1a900_0;
+ %pushi/vec4 1, 0, 3;
+ %cmp/e;
+ %flag_get/vec4 6;
+ %load/vec4 v0x12ef1a720_0;
+ %pushi/vec4 1, 0, 1;
+ %cmp/e;
+ %flag_get/vec4 6;
+ %and;
+ %load/vec4 v0x12ef20e30_0;
+ %pushi/vec4 2, 0, 2;
+ %cmp/e;
+ %flag_get/vec4 6;
+ %and;
+ %load/vec4 v0x12ef226f0_0;
+ %pushi/vec4 32, 0, 8;
+ %cmp/e;
+ %flag_get/vec4 6;
+ %load/vec4 v0x12ef226f0_0;
+ %pushi/vec4 48, 0, 8;
+ %cmp/e;
+ %flag_get/vec4 6;
+ %or;
+ %and;
+ %flag_set/vec4 8;
+ %jmp/0xz T_5.4, 8;
+ %pushi/vec4 1, 0, 1;
+ %assign/vec4 v0x12ef21db0_0, 0;
+ %pushi/vec4 0, 0, 32;
+ %store/vec4 v0x12ef18800_0, 0, 32;
+ %ix/getv/s 4, v0x12ef20620_0;
+ %load/vec4a v0x12ef20ee0, 4;
+ %store/vec4 v0x12ef20f80_0, 0, 32;
+T_5.6 ;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 8, 24, 6;
+ %cmpi/e 32, 0, 8;
+ %flag_mov 8, 6;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 8, 24, 6;
+ %cmpi/e 48, 0, 8;
+ %flag_or 6, 8;
+ %flag_mov 8, 6;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 8, 24, 6;
+ %cmpi/e 96, 0, 8;
+ %flag_or 6, 8;
+ %flag_mov 8, 6;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 8, 24, 6;
+ %cmpi/e 112, 0, 8;
+ %flag_or 6, 8;
+ %jmp/0xz T_5.7, 6;
+ %load/vec4 v0x12ef18890_0;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 6, 0, 2;
+ %pad/u 32;
+ %add;
+ %store/vec4 v0x12ef18890_0, 0, 32;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 8, 24, 6;
+ %cmpi/e 32, 0, 8;
+ %jmp/0xz T_5.8, 6;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 1, 6, 4;
+ %cmpi/e 1, 0, 1;
+ %jmp/0xz T_5.10, 6;
+ %load/vec4 v0x12ef20620_0;
+ %addi 6, 0, 32;
+ %store/vec4 v0x12ef20620_0, 0, 32;
+ %jmp T_5.11;
+T_5.10 ;
+ %load/vec4 v0x12ef20620_0;
+ %addi 5, 0, 32;
+ %store/vec4 v0x12ef20620_0, 0, 32;
+T_5.11 ;
+ %jmp T_5.9;
+T_5.8 ;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 8, 24, 6;
+ %cmpi/e 48, 0, 8;
+ %jmp/0xz T_5.12, 6;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 1, 6, 4;
+ %cmpi/e 1, 0, 1;
+ %jmp/0xz T_5.14, 6;
+ %load/vec4 v0x12ef20620_0;
+ %addi 2, 0, 32;
+ %store/vec4 v0x12ef20620_0, 0, 32;
+ %jmp T_5.15;
+T_5.14 ;
+ %load/vec4 v0x12ef20620_0;
+ %addi 1, 0, 32;
+ %store/vec4 v0x12ef20620_0, 0, 32;
+T_5.15 ;
+ %jmp T_5.13;
+T_5.12 ;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 8, 24, 6;
+ %cmpi/e 96, 0, 8;
+ %jmp/0xz T_5.16, 6;
+ %load/vec4 v0x12ef20620_0;
+ %addi 2, 0, 32;
+ %store/vec4 v0x12ef20620_0, 0, 32;
+ %jmp T_5.17;
+T_5.16 ;
+ %load/vec4 v0x12ef20620_0;
+ %addi 1, 0, 32;
+ %store/vec4 v0x12ef20620_0, 0, 32;
+ %ix/getv/s 4, v0x12ef20620_0;
+ %load/vec4a v0x12ef20ee0, 4;
+ %store/vec4 v0x12ef20f80_0, 0, 32;
+ %load/vec4 v0x12ef20620_0;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 5, 0, 2;
+ %pad/u 32;
+ %add;
+ %store/vec4 v0x12ef20620_0, 0, 32;
+ %load/vec4 v0x12ef20620_0;
+ %addi 1, 0, 32;
+ %store/vec4 v0x12ef20620_0, 0, 32;
+T_5.17 ;
+T_5.13 ;
+T_5.9 ;
+ %ix/getv/s 4, v0x12ef20620_0;
+ %load/vec4a v0x12ef20ee0, 4;
+ %store/vec4 v0x12ef20f80_0, 0, 32;
+ %jmp T_5.6;
+T_5.7 ;
+T_5.4 ;
+ %ix/getv/s 4, v0x12ef20620_0;
+ %load/vec4a v0x12ef20ee0, 4;
+ %store/vec4 v0x12ef20f80_0, 0, 32;
+T_5.18 ;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 8, 24, 6;
+ %pushi/vec4 112, 0, 8;
+ %cmp/e;
+ %flag_get/vec4 6;
+ %load/vec4 v0x12ef18800_0;
+ %pushi/vec4 0, 0, 32;
+ %cmp/e;
+ %flag_get/vec4 6;
+ %and;
+ %flag_set/vec4 8;
+ %jmp/0xz T_5.19, 8;
+ %load/vec4 v0x12ef18890_0;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 6, 0, 2;
+ %pad/u 32;
+ %add;
+ %store/vec4 v0x12ef18890_0, 0, 32;
+ %load/vec4 v0x12ef20620_0;
+ %addi 1, 0, 32;
+ %store/vec4 v0x12ef20620_0, 0, 32;
+ %ix/getv/s 4, v0x12ef20620_0;
+ %load/vec4a v0x12ef20ee0, 4;
+ %store/vec4 v0x12ef20f80_0, 0, 32;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 5, 0, 2;
+ %store/vec4 v0x12ef20980_0, 0, 5;
+ %load/vec4 v0x12ef20620_0;
+ %addi 1, 0, 32;
+ %store/vec4 v0x12ef20620_0, 0, 32;
+ %ix/getv/s 4, v0x12ef20620_0;
+ %load/vec4a v0x12ef20ee0, 4;
+ %store/vec4 v0x12ef20f80_0, 0, 32;
+ %pushi/vec4 0, 0, 32;
+ %store/vec4 v0x12ef18770_0, 0, 32;
+T_5.20 ;
+ %load/vec4 v0x12ef18770_0;
+ %load/vec4 v0x12ef20980_0;
+ %pad/u 32;
+ %cmp/u;
+ %jmp/0xz T_5.21, 5;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 8, 24, 6;
+ %load/vec4 v0x12ef18770_0;
+ %pad/s 65;
+ %muli 4, 0, 65;
+ %addi 0, 0, 65;
+ %ix/vec4/s 4;
+ %store/vec4a v0x12ef20a30, 4, 0;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 8, 16, 6;
+ %load/vec4 v0x12ef18770_0;
+ %pad/s 65;
+ %muli 4, 0, 65;
+ %addi 1, 0, 65;
+ %ix/vec4/s 4;
+ %store/vec4a v0x12ef20a30, 4, 0;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 8, 8, 5;
+ %load/vec4 v0x12ef18770_0;
+ %pad/s 65;
+ %muli 4, 0, 65;
+ %addi 2, 0, 65;
+ %ix/vec4/s 4;
+ %store/vec4a v0x12ef20a30, 4, 0;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 8, 0, 2;
+ %load/vec4 v0x12ef18770_0;
+ %pad/s 65;
+ %muli 4, 0, 65;
+ %addi 3, 0, 65;
+ %ix/vec4/s 4;
+ %store/vec4a v0x12ef20a30, 4, 0;
+ %load/vec4 v0x12ef20620_0;
+ %addi 1, 0, 32;
+ %store/vec4 v0x12ef20620_0, 0, 32;
+ %ix/getv/s 4, v0x12ef20620_0;
+ %load/vec4a v0x12ef20ee0, 4;
+ %store/vec4 v0x12ef20f80_0, 0, 32;
+ %load/vec4 v0x12ef18770_0;
+ %addi 1, 0, 32;
+ %store/vec4 v0x12ef18770_0, 0, 32;
+ %jmp T_5.20;
+T_5.21 ;
+ %fork TD_cmsdk_ahb_fileread_master32.u_ahb_filereadcore.tsk_simulation_comment, S_0x12ef1a060;
+ %join;
+ %jmp T_5.18;
+T_5.19 ;
+ %load/vec4 v0x12ef18800_0;
+ %cmpi/ne 0, 0, 32;
+ %jmp/0xz T_5.22, 6;
+ %load/vec4 v0x12ef18800_0;
+ %subi 1, 0, 32;
+ %store/vec4 v0x12ef18800_0, 0, 32;
+ %jmp T_5.23;
+T_5.22 ;
+ %ix/getv/s 4, v0x12ef20620_0;
+ %load/vec4a v0x12ef20ee0, 4;
+ %store/vec4 v0x12ef20f80_0, 0, 32;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 8, 24, 6;
+ %dup/vec4;
+ %pushi/vec4 0, 0, 8;
+ %cmp/u;
+ %jmp/1 T_5.24, 6;
+ %dup/vec4;
+ %pushi/vec4 16, 0, 8;
+ %cmp/u;
+ %jmp/1 T_5.25, 6;
+ %dup/vec4;
+ %pushi/vec4 32, 0, 8;
+ %cmp/u;
+ %jmp/1 T_5.26, 6;
+ %dup/vec4;
+ %pushi/vec4 48, 0, 8;
+ %cmp/u;
+ %jmp/1 T_5.27, 6;
+ %dup/vec4;
+ %pushi/vec4 64, 0, 8;
+ %cmp/u;
+ %jmp/1 T_5.28, 6;
+ %dup/vec4;
+ %pushi/vec4 80, 0, 8;
+ %cmp/u;
+ %jmp/1 T_5.29, 6;
+ %dup/vec4;
+ %pushi/vec4 96, 0, 8;
+ %cmp/u;
+ %jmp/1 T_5.30, 6;
+ %dup/vec4;
+ %pushi/vec4 128, 0, 8;
+ %cmp/u;
+ %jmp/1 T_5.31, 6;
+ %dup/vec4;
+ %pushi/vec4 255, 255, 8;
+ %cmp/u;
+ %jmp/1 T_5.32, 6;
+ %vpi_call/w 6 843 "$display", "%d %s #ERROR# Unknown command value in file.", $time, P_0x12ef17610 {0 0 0};
+ %vpi_call/w 6 844 "$stop" {0 0 0};
+ %jmp T_5.34;
+T_5.24 ;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 8, 24, 6;
+ %assign/vec4 v0x12ef226f0_0, 0;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 3, 21, 6;
+ %assign/vec4 v0x12ef22af0_0, 0;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 3, 18, 6;
+ %assign/vec4 v0x12ef22640_0, 0;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 6, 12, 5;
+ %assign/vec4 v0x12ef22a40_0, 0;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 1, 11, 5;
+ %assign/vec4 v0x12ef229a0_0, 0;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 2, 8, 5;
+ %assign/vec4 v0x12ef20d80_0, 0;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 1, 7, 4;
+ %assign/vec4 v0x12ef223a0_0, 0;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 1, 6, 4;
+ %store/vec4 v0x12ef18940_0, 0, 1;
+ %load/vec4 v0x12ef18890_0;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 6, 0, 2;
+ %pad/u 32;
+ %add;
+ %store/vec4 v0x12ef18890_0, 0, 32;
+ %load/vec4 v0x12ef20620_0;
+ %addi 1, 0, 32;
+ %store/vec4 v0x12ef20620_0, 0, 32;
+ %ix/getv/s 4, v0x12ef20620_0;
+ %load/vec4a v0x12ef20ee0, 4;
+ %assign/vec4 v0x12ef224e0_0, 0;
+ %load/vec4 v0x12ef20620_0;
+ %addi 1, 0, 32;
+ %store/vec4 v0x12ef20620_0, 0, 32;
+ %ix/getv/s 4, v0x12ef20620_0;
+ %load/vec4a v0x12ef20ee0, 4;
+ %ix/load 4, 32, 0;
+ %ix/load 5, 0, 0;
+ %flag_set/imm 4, 0;
+ %assign/vec4/off/d v0x12ef227a0_0, 4, 5;
+ %load/vec4 v0x12ef20620_0;
+ %addi 1, 0, 32;
+ %store/vec4 v0x12ef20620_0, 0, 32;
+ %ix/getv/s 4, v0x12ef20620_0;
+ %load/vec4a v0x12ef20ee0, 4;
+ %ix/load 4, 0, 0;
+ %ix/load 5, 0, 0;
+ %flag_set/imm 4, 0;
+ %assign/vec4/off/d v0x12ef227a0_0, 4, 5;
+ %load/vec4 v0x12ef20620_0;
+ %addi 1, 0, 32;
+ %store/vec4 v0x12ef20620_0, 0, 32;
+ %load/vec4 v0x12ef18940_0;
+ %cmpi/e 1, 0, 1;
+ %jmp/0xz T_5.35, 6;
+ %ix/getv/s 4, v0x12ef20620_0;
+ %load/vec4a v0x12ef20ee0, 4;
+ %store/vec4 v0x12ef20f80_0, 0, 32;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 8, 0, 2;
+ %assign/vec4 v0x12ef22590_0, 0;
+ %load/vec4 v0x12ef20620_0;
+ %addi 1, 0, 32;
+ %store/vec4 v0x12ef20620_0, 0, 32;
+T_5.35 ;
+ %jmp T_5.34;
+T_5.25 ;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 8, 24, 6;
+ %assign/vec4 v0x12ef226f0_0, 0;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 3, 21, 6;
+ %assign/vec4 v0x12ef22af0_0, 0;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 3, 18, 6;
+ %assign/vec4 v0x12ef22640_0, 0;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 6, 12, 5;
+ %assign/vec4 v0x12ef22a40_0, 0;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 1, 11, 5;
+ %assign/vec4 v0x12ef229a0_0, 0;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 2, 8, 5;
+ %assign/vec4 v0x12ef20d80_0, 0;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 1, 7, 4;
+ %assign/vec4 v0x12ef223a0_0, 0;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 1, 6, 4;
+ %store/vec4 v0x12ef18940_0, 0, 1;
+ %load/vec4 v0x12ef18890_0;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 6, 0, 2;
+ %pad/u 32;
+ %add;
+ %store/vec4 v0x12ef18890_0, 0, 32;
+ %load/vec4 v0x12ef20620_0;
+ %addi 1, 0, 32;
+ %store/vec4 v0x12ef20620_0, 0, 32;
+ %ix/getv/s 4, v0x12ef20620_0;
+ %load/vec4a v0x12ef20ee0, 4;
+ %assign/vec4 v0x12ef224e0_0, 0;
+ %load/vec4 v0x12ef20620_0;
+ %addi 1, 0, 32;
+ %store/vec4 v0x12ef20620_0, 0, 32;
+ %ix/getv/s 4, v0x12ef20620_0;
+ %load/vec4a v0x12ef20ee0, 4;
+ %ix/load 4, 32, 0;
+ %ix/load 5, 0, 0;
+ %flag_set/imm 4, 0;
+ %assign/vec4/off/d v0x12ef227a0_0, 4, 5;
+ %load/vec4 v0x12ef20620_0;
+ %addi 1, 0, 32;
+ %store/vec4 v0x12ef20620_0, 0, 32;
+ %ix/getv/s 4, v0x12ef20620_0;
+ %load/vec4a v0x12ef20ee0, 4;
+ %ix/load 4, 0, 0;
+ %ix/load 5, 0, 0;
+ %flag_set/imm 4, 0;
+ %assign/vec4/off/d v0x12ef227a0_0, 4, 5;
+ %load/vec4 v0x12ef20620_0;
+ %addi 1, 0, 32;
+ %store/vec4 v0x12ef20620_0, 0, 32;
+ %ix/getv/s 4, v0x12ef20620_0;
+ %load/vec4a v0x12ef20ee0, 4;
+ %ix/load 4, 32, 0;
+ %ix/load 5, 0, 0;
+ %flag_set/imm 4, 0;
+ %assign/vec4/off/d v0x12ef22850_0, 4, 5;
+ %load/vec4 v0x12ef20620_0;
+ %addi 1, 0, 32;
+ %store/vec4 v0x12ef20620_0, 0, 32;
+ %ix/getv/s 4, v0x12ef20620_0;
+ %load/vec4a v0x12ef20ee0, 4;
+ %ix/load 4, 0, 0;
+ %ix/load 5, 0, 0;
+ %flag_set/imm 4, 0;
+ %assign/vec4/off/d v0x12ef22850_0, 4, 5;
+ %load/vec4 v0x12ef20620_0;
+ %addi 1, 0, 32;
+ %store/vec4 v0x12ef20620_0, 0, 32;
+ %load/vec4 v0x12ef18940_0;
+ %cmpi/e 1, 0, 1;
+ %jmp/0xz T_5.37, 6;
+ %ix/getv/s 4, v0x12ef20620_0;
+ %load/vec4a v0x12ef20ee0, 4;
+ %store/vec4 v0x12ef20f80_0, 0, 32;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 8, 0, 2;
+ %assign/vec4 v0x12ef22590_0, 0;
+ %load/vec4 v0x12ef20620_0;
+ %addi 1, 0, 32;
+ %store/vec4 v0x12ef20620_0, 0, 32;
+T_5.37 ;
+ %jmp T_5.34;
+T_5.26 ;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 8, 24, 6;
+ %assign/vec4 v0x12ef226f0_0, 0;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 2, 8, 5;
+ %assign/vec4 v0x12ef20d80_0, 0;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 1, 6, 4;
+ %store/vec4 v0x12ef18940_0, 0, 1;
+ %load/vec4 v0x12ef18890_0;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 6, 0, 2;
+ %pad/u 32;
+ %add;
+ %store/vec4 v0x12ef18890_0, 0, 32;
+ %load/vec4 v0x12ef20620_0;
+ %addi 1, 0, 32;
+ %store/vec4 v0x12ef20620_0, 0, 32;
+ %ix/getv/s 4, v0x12ef20620_0;
+ %load/vec4a v0x12ef20ee0, 4;
+ %ix/load 4, 32, 0;
+ %ix/load 5, 0, 0;
+ %flag_set/imm 4, 0;
+ %assign/vec4/off/d v0x12ef227a0_0, 4, 5;
+ %load/vec4 v0x12ef20620_0;
+ %addi 1, 0, 32;
+ %store/vec4 v0x12ef20620_0, 0, 32;
+ %ix/getv/s 4, v0x12ef20620_0;
+ %load/vec4a v0x12ef20ee0, 4;
+ %ix/load 4, 0, 0;
+ %ix/load 5, 0, 0;
+ %flag_set/imm 4, 0;
+ %assign/vec4/off/d v0x12ef227a0_0, 4, 5;
+ %load/vec4 v0x12ef20620_0;
+ %addi 1, 0, 32;
+ %store/vec4 v0x12ef20620_0, 0, 32;
+ %ix/getv/s 4, v0x12ef20620_0;
+ %load/vec4a v0x12ef20ee0, 4;
+ %ix/load 4, 32, 0;
+ %ix/load 5, 0, 0;
+ %flag_set/imm 4, 0;
+ %assign/vec4/off/d v0x12ef22850_0, 4, 5;
+ %load/vec4 v0x12ef20620_0;
+ %addi 1, 0, 32;
+ %store/vec4 v0x12ef20620_0, 0, 32;
+ %ix/getv/s 4, v0x12ef20620_0;
+ %load/vec4a v0x12ef20ee0, 4;
+ %ix/load 4, 0, 0;
+ %ix/load 5, 0, 0;
+ %flag_set/imm 4, 0;
+ %assign/vec4/off/d v0x12ef22850_0, 4, 5;
+ %load/vec4 v0x12ef20620_0;
+ %addi 1, 0, 32;
+ %store/vec4 v0x12ef20620_0, 0, 32;
+ %load/vec4 v0x12ef18940_0;
+ %cmpi/e 1, 0, 1;
+ %jmp/0xz T_5.39, 6;
+ %ix/getv/s 4, v0x12ef20620_0;
+ %load/vec4a v0x12ef20ee0, 4;
+ %store/vec4 v0x12ef20f80_0, 0, 32;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 8, 0, 2;
+ %assign/vec4 v0x12ef22590_0, 0;
+ %load/vec4 v0x12ef20620_0;
+ %addi 1, 0, 32;
+ %store/vec4 v0x12ef20620_0, 0, 32;
+T_5.39 ;
+ %jmp T_5.34;
+T_5.27 ;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 8, 24, 6;
+ %assign/vec4 v0x12ef226f0_0, 0;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 1, 8, 5;
+ %assign/vec4 v0x12ef22ba0_0, 0;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 1, 6, 4;
+ %store/vec4 v0x12ef18940_0, 0, 1;
+ %load/vec4 v0x12ef18890_0;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 6, 0, 2;
+ %pad/u 32;
+ %add;
+ %store/vec4 v0x12ef18890_0, 0, 32;
+ %pushi/vec4 0, 0, 2;
+ %assign/vec4 v0x12ef20d80_0, 0;
+ %load/vec4 v0x12ef20620_0;
+ %addi 1, 0, 32;
+ %store/vec4 v0x12ef20620_0, 0, 32;
+ %load/vec4 v0x12ef18940_0;
+ %cmpi/e 1, 0, 1;
+ %jmp/0xz T_5.41, 6;
+ %ix/getv/s 4, v0x12ef20620_0;
+ %load/vec4a v0x12ef20ee0, 4;
+ %store/vec4 v0x12ef20f80_0, 0, 32;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 8, 0, 2;
+ %assign/vec4 v0x12ef22590_0, 0;
+ %load/vec4 v0x12ef20620_0;
+ %addi 1, 0, 32;
+ %store/vec4 v0x12ef20620_0, 0, 32;
+T_5.41 ;
+ %jmp T_5.34;
+T_5.28 ;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 8, 24, 6;
+ %assign/vec4 v0x12ef226f0_0, 0;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 3, 21, 6;
+ %assign/vec4 v0x12ef22af0_0, 0;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 3, 18, 6;
+ %assign/vec4 v0x12ef22640_0, 0;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 6, 12, 5;
+ %assign/vec4 v0x12ef22a40_0, 0;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 1, 11, 5;
+ %assign/vec4 v0x12ef229a0_0, 0;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 1, 10, 5;
+ %assign/vec4 v0x12ef22900_0, 0;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 1, 8, 5;
+ %assign/vec4 v0x12ef22ba0_0, 0;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 1, 7, 4;
+ %assign/vec4 v0x12ef223a0_0, 0;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 1, 6, 4;
+ %store/vec4 v0x12ef18940_0, 0, 1;
+ %pushi/vec4 0, 0, 2;
+ %assign/vec4 v0x12ef20d80_0, 0;
+ %load/vec4 v0x12ef18890_0;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 6, 0, 2;
+ %pad/u 32;
+ %add;
+ %store/vec4 v0x12ef18890_0, 0, 32;
+ %load/vec4 v0x12ef20620_0;
+ %addi 1, 0, 32;
+ %store/vec4 v0x12ef20620_0, 0, 32;
+ %ix/getv/s 4, v0x12ef20620_0;
+ %load/vec4a v0x12ef20ee0, 4;
+ %assign/vec4 v0x12ef224e0_0, 0;
+ %load/vec4 v0x12ef20620_0;
+ %addi 1, 0, 32;
+ %store/vec4 v0x12ef20620_0, 0, 32;
+ %load/vec4 v0x12ef18940_0;
+ %cmpi/e 1, 0, 1;
+ %jmp/0xz T_5.43, 6;
+ %ix/getv/s 4, v0x12ef20620_0;
+ %load/vec4a v0x12ef20ee0, 4;
+ %store/vec4 v0x12ef20f80_0, 0, 32;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 8, 0, 2;
+ %assign/vec4 v0x12ef22590_0, 0;
+ %load/vec4 v0x12ef20620_0;
+ %addi 1, 0, 32;
+ %store/vec4 v0x12ef20620_0, 0, 32;
+T_5.43 ;
+ %jmp T_5.34;
+T_5.29 ;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 8, 24, 6;
+ %assign/vec4 v0x12ef226f0_0, 0;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 3, 21, 6;
+ %assign/vec4 v0x12ef22af0_0, 0;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 3, 18, 6;
+ %assign/vec4 v0x12ef22640_0, 0;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 6, 12, 5;
+ %assign/vec4 v0x12ef22a40_0, 0;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 1, 7, 4;
+ %assign/vec4 v0x12ef223a0_0, 0;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 1, 6, 4;
+ %store/vec4 v0x12ef18940_0, 0, 1;
+ %load/vec4 v0x12ef18890_0;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 6, 0, 2;
+ %pad/u 32;
+ %add;
+ %store/vec4 v0x12ef18890_0, 0, 32;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x12ef229a0_0, 0;
+ %pushi/vec4 0, 0, 2;
+ %assign/vec4 v0x12ef20d80_0, 0;
+ %load/vec4 v0x12ef20620_0;
+ %addi 1, 0, 32;
+ %store/vec4 v0x12ef20620_0, 0, 32;
+ %ix/getv/s 4, v0x12ef20620_0;
+ %load/vec4a v0x12ef20ee0, 4;
+ %store/vec4 v0x12ef20f80_0, 0, 32;
+ %load/vec4 v0x12ef20f80_0;
+ %assign/vec4 v0x12ef22240_0, 0;
+ %load/vec4 v0x12ef20620_0;
+ %addi 1, 0, 32;
+ %store/vec4 v0x12ef20620_0, 0, 32;
+ %ix/getv/s 4, v0x12ef20620_0;
+ %load/vec4a v0x12ef20ee0, 4;
+ %assign/vec4 v0x12ef224e0_0, 0;
+ %load/vec4 v0x12ef20620_0;
+ %addi 1, 0, 32;
+ %store/vec4 v0x12ef20620_0, 0, 32;
+ %ix/getv/s 4, v0x12ef20620_0;
+ %load/vec4a v0x12ef20ee0, 4;
+ %ix/load 4, 32, 0;
+ %ix/load 5, 0, 0;
+ %flag_set/imm 4, 0;
+ %assign/vec4/off/d v0x12ef227a0_0, 4, 5;
+ %load/vec4 v0x12ef20620_0;
+ %addi 1, 0, 32;
+ %store/vec4 v0x12ef20620_0, 0, 32;
+ %ix/getv/s 4, v0x12ef20620_0;
+ %load/vec4a v0x12ef20ee0, 4;
+ %ix/load 4, 0, 0;
+ %ix/load 5, 0, 0;
+ %flag_set/imm 4, 0;
+ %assign/vec4/off/d v0x12ef227a0_0, 4, 5;
+ %load/vec4 v0x12ef20620_0;
+ %addi 1, 0, 32;
+ %store/vec4 v0x12ef20620_0, 0, 32;
+ %ix/getv/s 4, v0x12ef20620_0;
+ %load/vec4a v0x12ef20ee0, 4;
+ %ix/load 4, 32, 0;
+ %ix/load 5, 0, 0;
+ %flag_set/imm 4, 0;
+ %assign/vec4/off/d v0x12ef22850_0, 4, 5;
+ %load/vec4 v0x12ef20620_0;
+ %addi 1, 0, 32;
+ %store/vec4 v0x12ef20620_0, 0, 32;
+ %ix/getv/s 4, v0x12ef20620_0;
+ %load/vec4a v0x12ef20ee0, 4;
+ %ix/load 4, 0, 0;
+ %ix/load 5, 0, 0;
+ %flag_set/imm 4, 0;
+ %assign/vec4/off/d v0x12ef22850_0, 4, 5;
+ %load/vec4 v0x12ef20620_0;
+ %addi 1, 0, 32;
+ %store/vec4 v0x12ef20620_0, 0, 32;
+ %load/vec4 v0x12ef18940_0;
+ %cmpi/e 1, 0, 1;
+ %jmp/0xz T_5.45, 6;
+ %ix/getv/s 4, v0x12ef20620_0;
+ %load/vec4a v0x12ef20ee0, 4;
+ %store/vec4 v0x12ef20f80_0, 0, 32;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 8, 0, 2;
+ %assign/vec4 v0x12ef22590_0, 0;
+ %load/vec4 v0x12ef20620_0;
+ %addi 1, 0, 32;
+ %store/vec4 v0x12ef20620_0, 0, 32;
+T_5.45 ;
+ %jmp T_5.34;
+T_5.30 ;
+ %load/vec4 v0x12ef18890_0;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 6, 0, 2;
+ %pad/u 32;
+ %add;
+ %store/vec4 v0x12ef18890_0, 0, 32;
+ %load/vec4 v0x12ef20620_0;
+ %addi 1, 0, 32;
+ %store/vec4 v0x12ef20620_0, 0, 32;
+ %ix/getv/s 4, v0x12ef20620_0;
+ %load/vec4a v0x12ef20ee0, 4;
+ %store/vec4 v0x12ef20f80_0, 0, 32;
+ %load/vec4 v0x12ef20f80_0;
+ %subi 1, 0, 32;
+ %store/vec4 v0x12ef18800_0, 0, 32;
+ %load/vec4 v0x12ef20620_0;
+ %addi 1, 0, 32;
+ %store/vec4 v0x12ef20620_0, 0, 32;
+ %jmp T_5.34;
+T_5.31 ;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 8, 24, 6;
+ %assign/vec4 v0x12ef226f0_0, 0;
+ %pushi/vec4 0, 0, 32;
+ %assign/vec4 v0x12ef224e0_0, 0;
+ %pushi/vec4 0, 0, 64;
+ %assign/vec4 v0x12ef227a0_0, 0;
+ %pushi/vec4 4294967295, 0, 32;
+ %concati/vec4 4294967295, 0, 32;
+ %assign/vec4 v0x12ef22850_0, 0;
+ %pushi/vec4 0, 0, 3;
+ %assign/vec4 v0x12ef22af0_0, 0;
+ %pushi/vec4 0, 0, 3;
+ %assign/vec4 v0x12ef22640_0, 0;
+ %pushi/vec4 0, 0, 6;
+ %assign/vec4 v0x12ef22a40_0, 0;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x12ef22900_0, 0;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x12ef229a0_0, 0;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x12ef22ba0_0, 0;
+ %pushi/vec4 0, 0, 8;
+ %assign/vec4 v0x12ef22590_0, 0;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x12ef223a0_0, 0;
+ %pushi/vec4 0, 0, 2;
+ %assign/vec4 v0x12ef20d80_0, 0;
+ %pushi/vec4 1, 0, 1;
+ %store/vec4 v0x12ef18940_0, 0, 1;
+ %load/vec4 v0x12ef18890_0;
+ %load/vec4 v0x12ef20f80_0;
+ %parti/s 6, 0, 2;
+ %pad/u 32;
+ %add;
+ %store/vec4 v0x12ef18890_0, 0, 32;
+ %jmp T_5.34;
+T_5.32 ;
+ %pushi/vec4 64, 0, 8;
+ %assign/vec4 v0x12ef226f0_0, 0;
+ %pushi/vec4 0, 0, 32;
+ %assign/vec4 v0x12ef224e0_0, 0;
+ %pushi/vec4 0, 0, 64;
+ %assign/vec4 v0x12ef227a0_0, 0;
+ %pushi/vec4 4294967295, 0, 32;
+ %concati/vec4 4294967295, 0, 32;
+ %assign/vec4 v0x12ef22850_0, 0;
+ %pushi/vec4 0, 0, 3;
+ %assign/vec4 v0x12ef22af0_0, 0;
+ %pushi/vec4 0, 0, 3;
+ %assign/vec4 v0x12ef22640_0, 0;
+ %pushi/vec4 0, 0, 6;
+ %assign/vec4 v0x12ef22a40_0, 0;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x12ef22900_0, 0;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x12ef229a0_0, 0;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x12ef22ba0_0, 0;
+ %pushi/vec4 0, 0, 8;
+ %assign/vec4 v0x12ef22590_0, 0;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x12ef223a0_0, 0;
+ %pushi/vec4 1, 0, 1;
+ %store/vec4 v0x12ef18940_0, 0, 1;
+ %pushi/vec4 0, 0, 2;
+ %assign/vec4 v0x12ef20d80_0, 0;
+ %pushi/vec4 1, 0, 1;
+ %assign/vec4 v0x12ef21f00_0, 0;
+ %jmp T_5.34;
+T_5.34 ;
+ %pop/vec4 1;
+ %load/vec4 v0x12ef18890_0;
+ %assign/vec4 v0x12ef220e0_0, 0;
+T_5.23 ;
+ %load/vec4 v0x12ef18940_0;
+ %assign/vec4 v0x12ef22440_0, 0;
+T_5.2 ;
+T_5.1 ;
+ %end;
+ .scope S_0x12ef17400;
+t_6 %join;
+ %jmp T_5;
+ .thread T_5;
+ .scope S_0x12ef17400;
+T_6 ;
+ %wait E_0x12ef17c00;
+ %fork t_9, S_0x12ef19a20;
+ %jmp t_8;
+ .scope S_0x12ef19a20;
+t_9 ;
+ %load/vec4 v0x12ef208d0_0;
+ %cmpi/e 128, 0, 8;
+ %flag_mov 8, 6;
+ %load/vec4 v0x12ef21fa0_0;
+ %pushi/vec4 1, 0, 1;
+ %cmp/e;
+ %flag_get/vec4 6;
+ %load/vec4 v0x12ef22040_0;
+ %pushi/vec4 0, 0, 1;
+ %cmp/e;
+ %flag_get/vec4 6;
+ %and;
+ %flag_set/vec4 9;
+ %flag_or 9, 8;
+ %jmp/0xz T_6.0, 9;
+ %vpi_call/w 6 870 "$display", "\000" {0 0 0};
+ %vpi_call/w 6 871 "$write", "%d %s ", $time, P_0x12ef17610 {0 0 0};
+ %load/vec4 v0x12ef208d0_0;
+ %cmpi/e 128, 0, 8;
+ %jmp/0xz T_6.2, 6;
+ %vpi_call/w 6 875 "$display", "Simulation Quit requested." {0 0 0};
+ %jmp T_6.3;
+T_6.2 ;
+ %vpi_call/w 6 878 "$display", "Stimulus completed." {0 0 0};
+T_6.3 ;
+ %vpi_call/w 6 881 "$display", "\000" {0 0 0};
+ %vpi_call/w 6 882 "$display", " ******* SIMULATION SUMMARY *******" {0 0 0};
+ %vpi_call/w 6 883 "$display", " ** Data Mismatches :%d", v0x12ef20c20_0 {0 0 0};
+ %vpi_call/w 6 884 "$display", " ** Response Mismatches :%d", v0x12ef21e50_0 {0 0 0};
+ %vpi_call/w 6 885 "$display", " ** Poll timeouts :%d", v0x12ef21b00_0 {0 0 0};
+ %vpi_call/w 6 886 "$display", " **********************************" {0 0 0};
+ %vpi_call/w 6 887 "$display", "\000" {0 0 0};
+ %load/vec4 v0x12ef208d0_0;
+ %cmpi/e 128, 0, 8;
+ %jmp/0xz T_6.4, 6;
+ %vpi_call/w 6 892 "$display", " Simulation halted." {0 0 0};
+ %vpi_call/w 6 893 "$stop" {0 0 0};
+T_6.4 ;
+T_6.0 ;
+ %end;
+ .scope S_0x12ef17400;
+t_8 %join;
+ %jmp T_6;
+ .thread T_6;
+ .scope S_0x12ef17400;
+T_7 ;
+ %wait E_0x12ef16910;
+ %fork t_11, S_0x12ef19320;
+ %jmp t_10;
+ .scope S_0x12ef19320;
+t_11 ;
+ %load/vec4 v0x12ef1a7d0_0;
+ %cmpi/ne 1, 0, 1;
+ %jmp/0xz T_7.0, 6;
+ %pushi/vec4 0, 0, 8;
+ %assign/vec4 v0x12ef208d0_0, 0;
+ %pushi/vec4 0, 0, 64;
+ %assign/vec4 v0x12ef20cd0_0, 0;
+ %pushi/vec4 0, 0, 64;
+ %assign/vec4 v0x12ef217a0_0, 0;
+ %pushi/vec4 0, 0, 3;
+ %assign/vec4 v0x12ef21d00_0, 0;
+ %pushi/vec4 0, 0, 2;
+ %assign/vec4 v0x12ef20e30_0, 0;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x12ef21fa0_0, 0;
+ %pushi/vec4 0, 0, 32;
+ %assign/vec4 v0x12ef22190_0, 0;
+ %pushi/vec4 0, 0, 32;
+ %assign/vec4 v0x12ef222f0_0, 0;
+ %jmp T_7.1;
+T_7.0 ;
+ %load/vec4 v0x12ef1a720_0;
+ %cmpi/e 1, 0, 1;
+ %jmp/0xz T_7.2, 6;
+ %load/vec4 v0x12ef226f0_0;
+ %assign/vec4 v0x12ef208d0_0, 0;
+ %load/vec4 v0x12ef227a0_0;
+ %assign/vec4 v0x12ef20cd0_0, 0;
+ %load/vec4 v0x12ef216f0_0;
+ %assign/vec4 v0x12ef217a0_0, 0;
+ %load/vec4 v0x12ef22af0_0;
+ %assign/vec4 v0x12ef21d00_0, 0;
+ %load/vec4 v0x12ef20d80_0;
+ %assign/vec4 v0x12ef20e30_0, 0;
+ %load/vec4 v0x12ef21f00_0;
+ %assign/vec4 v0x12ef21fa0_0, 0;
+ %load/vec4 v0x12ef220e0_0;
+ %assign/vec4 v0x12ef22190_0, 0;
+ %load/vec4 v0x12ef22240_0;
+ %assign/vec4 v0x12ef222f0_0, 0;
+T_7.2 ;
+T_7.1 ;
+ %end;
+ .scope S_0x12ef17400;
+t_10 %join;
+ %jmp T_7;
+ .thread T_7;
+ .scope S_0x12ef17400;
+T_8 ;
+ %wait E_0x12ef16910;
+ %fork t_13, S_0x12ef19be0;
+ %jmp t_12;
+ .scope S_0x12ef19be0;
+t_13 ;
+ %load/vec4 v0x12ef1a7d0_0;
+ %cmpi/ne 1, 0, 1;
+ %jmp/0xz T_8.0, 6;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x12ef22040_0, 0;
+ %jmp T_8.1;
+T_8.0 ;
+ %load/vec4 v0x12ef21fa0_0;
+ %assign/vec4 v0x12ef22040_0, 0;
+T_8.1 ;
+ %end;
+ .scope S_0x12ef17400;
+t_12 %join;
+ %jmp T_8;
+ .thread T_8;
+ .scope S_0x12ef17400;
+T_9 ;
+ %wait E_0x12ef16910;
+ %fork t_15, S_0x12ef194e0;
+ %jmp t_14;
+ .scope S_0x12ef194e0;
+t_15 ;
+ %load/vec4 v0x12ef1a7d0_0;
+ %cmpi/ne 1, 0, 1;
+ %jmp/0xz T_9.0, 6;
+ %pushi/vec4 0, 0, 32;
+ %assign/vec4 v0x12ef21030_0, 0;
+ %pushi/vec4 0, 0, 2;
+ %assign/vec4 v0x12ef210e0_0, 0;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x12ef21240_0, 0;
+ %jmp T_9.1;
+T_9.0 ;
+ %load/vec4 v0x12ef1a720_0;
+ %cmpi/e 1, 0, 1;
+ %jmp/0xz T_9.2, 6;
+ %load/vec4 v0x12ef21440_0;
+ %assign/vec4 v0x12ef210e0_0, 0;
+ %load/vec4 v0x12ef212e0_0;
+ %assign/vec4 v0x12ef21030_0, 0;
+ %load/vec4 v0x12ef215a0_0;
+ %assign/vec4 v0x12ef21240_0, 0;
+T_9.2 ;
+T_9.1 ;
+ %end;
+ .scope S_0x12ef17400;
+t_14 %join;
+ %jmp T_9;
+ .thread T_9;
+ .scope S_0x12ef17400;
+T_10 ;
+ %wait E_0x12ef17b10;
+ %fork t_17, S_0x12ef17c90;
+ %jmp t_16;
+ .scope S_0x12ef17c90;
+t_17 ;
+ %load/vec4 v0x12ef22af0_0;
+ %dup/vec4;
+ %pushi/vec4 0, 0, 3;
+ %cmp/u;
+ %jmp/1 T_10.0, 6;
+ %dup/vec4;
+ %pushi/vec4 1, 0, 3;
+ %cmp/u;
+ %jmp/1 T_10.1, 6;
+ %dup/vec4;
+ %pushi/vec4 2, 0, 3;
+ %cmp/u;
+ %jmp/1 T_10.2, 6;
+ %dup/vec4;
+ %pushi/vec4 3, 0, 3;
+ %cmp/u;
+ %jmp/1 T_10.3, 6;
+ %pushi/vec4 7, 0, 3;
+ %store/vec4 v0x12ef20410_0, 0, 3;
+ %jmp T_10.5;
+T_10.0 ;
+ %pushi/vec4 7, 0, 3;
+ %store/vec4 v0x12ef20410_0, 0, 3;
+ %jmp T_10.5;
+T_10.1 ;
+ %pushi/vec4 6, 0, 3;
+ %store/vec4 v0x12ef20410_0, 0, 3;
+ %jmp T_10.5;
+T_10.2 ;
+ %pushi/vec4 4, 0, 3;
+ %store/vec4 v0x12ef20410_0, 0, 3;
+ %jmp T_10.5;
+T_10.3 ;
+ %pushi/vec4 0, 0, 3;
+ %store/vec4 v0x12ef20410_0, 0, 3;
+ %jmp T_10.5;
+T_10.5 ;
+ %pop/vec4 1;
+ %end;
+ .scope S_0x12ef17400;
+t_16 %join;
+ %jmp T_10;
+ .thread T_10, $push;
+ .scope S_0x12ef17400;
+T_11 ;
+ %wait E_0x12ef17b70;
+ %fork t_19, S_0x12ef183b0;
+ %jmp t_18;
+ .scope S_0x12ef183b0;
+t_19 ;
+ %load/vec4 v0x12ef219b0_0;
+ %cmpi/e 1, 0, 1;
+ %jmp/0xz T_11.0, 6;
+ %load/vec4 v0x12ef22af0_0;
+ %dup/vec4;
+ %pushi/vec4 0, 0, 3;
+ %cmp/u;
+ %jmp/1 T_11.2, 6;
+ %dup/vec4;
+ %pushi/vec4 1, 0, 3;
+ %cmp/u;
+ %jmp/1 T_11.3, 6;
+ %dup/vec4;
+ %pushi/vec4 2, 0, 3;
+ %cmp/u;
+ %jmp/1 T_11.4, 6;
+ %dup/vec4;
+ %pushi/vec4 3, 0, 3;
+ %cmp/u;
+ %jmp/1 T_11.5, 6;
+ %pushi/vec4 0, 0, 4;
+ %store/vec4 v0x12ef20360_0, 0, 4;
+ %jmp T_11.7;
+T_11.2 ;
+ %pushi/vec4 1, 0, 4;
+ %store/vec4 v0x12ef20360_0, 0, 4;
+ %jmp T_11.7;
+T_11.3 ;
+ %pushi/vec4 2, 0, 4;
+ %store/vec4 v0x12ef20360_0, 0, 4;
+ %jmp T_11.7;
+T_11.4 ;
+ %pushi/vec4 4, 0, 4;
+ %store/vec4 v0x12ef20360_0, 0, 4;
+ %jmp T_11.7;
+T_11.5 ;
+ %pushi/vec4 8, 0, 4;
+ %store/vec4 v0x12ef20360_0, 0, 4;
+ %jmp T_11.7;
+T_11.7 ;
+ %pop/vec4 1;
+ %jmp T_11.1;
+T_11.0 ;
+ %pushi/vec4 0, 0, 4;
+ %store/vec4 v0x12ef20360_0, 0, 4;
+T_11.1 ;
+ %end;
+ .scope S_0x12ef17400;
+t_18 %join;
+ %jmp T_11;
+ .thread T_11, $push;
+ .scope S_0x12ef17400;
+T_12 ;
+ %wait E_0x12ef17b40;
+ %fork t_21, S_0x12ef18030;
+ %jmp t_20;
+ .scope S_0x12ef18030;
+t_21 ;
+ %load/vec4 v0x12ef22af0_0;
+ %dup/vec4;
+ %pushi/vec4 0, 0, 3;
+ %cmp/u;
+ %jmp/1 T_12.0, 6;
+ %dup/vec4;
+ %pushi/vec4 1, 0, 3;
+ %cmp/u;
+ %jmp/1 T_12.1, 6;
+ %dup/vec4;
+ %pushi/vec4 2, 0, 3;
+ %cmp/u;
+ %jmp/1 T_12.2, 6;
+ %dup/vec4;
+ %pushi/vec4 3, 0, 3;
+ %cmp/u;
+ %jmp/1 T_12.3, 6;
+ %pushi/vec4 0, 0, 3;
+ %store/vec4 v0x12ef20770_0, 0, 3;
+ %jmp T_12.5;
+T_12.0 ;
+ %load/vec4 v0x12ef22640_0;
+ %dup/vec4;
+ %pushi/vec4 2, 0, 3;
+ %cmp/u;
+ %jmp/1 T_12.6, 6;
+ %dup/vec4;
+ %pushi/vec4 4, 0, 3;
+ %cmp/u;
+ %jmp/1 T_12.7, 6;
+ %dup/vec4;
+ %pushi/vec4 6, 0, 3;
+ %cmp/u;
+ %jmp/1 T_12.8, 6;
+ %dup/vec4;
+ %pushi/vec4 0, 0, 3;
+ %cmp/u;
+ %jmp/1 T_12.9, 6;
+ %dup/vec4;
+ %pushi/vec4 1, 0, 3;
+ %cmp/u;
+ %jmp/1 T_12.10, 6;
+ %dup/vec4;
+ %pushi/vec4 3, 0, 3;
+ %cmp/u;
+ %jmp/1 T_12.11, 6;
+ %dup/vec4;
+ %pushi/vec4 5, 0, 3;
+ %cmp/u;
+ %jmp/1 T_12.12, 6;
+ %dup/vec4;
+ %pushi/vec4 7, 0, 3;
+ %cmp/u;
+ %jmp/1 T_12.13, 6;
+ %pushi/vec4 0, 0, 3;
+ %store/vec4 v0x12ef20770_0, 0, 3;
+ %jmp T_12.15;
+T_12.6 ;
+ %pushi/vec4 1, 0, 3;
+ %store/vec4 v0x12ef20770_0, 0, 3;
+ %jmp T_12.15;
+T_12.7 ;
+ %pushi/vec4 2, 0, 3;
+ %store/vec4 v0x12ef20770_0, 0, 3;
+ %jmp T_12.15;
+T_12.8 ;
+ %pushi/vec4 3, 0, 3;
+ %store/vec4 v0x12ef20770_0, 0, 3;
+ %jmp T_12.15;
+T_12.9 ;
+ %pushi/vec4 0, 0, 3;
+ %store/vec4 v0x12ef20770_0, 0, 3;
+ %jmp T_12.15;
+T_12.10 ;
+ %pushi/vec4 0, 0, 3;
+ %store/vec4 v0x12ef20770_0, 0, 3;
+ %jmp T_12.15;
+T_12.11 ;
+ %pushi/vec4 0, 0, 3;
+ %store/vec4 v0x12ef20770_0, 0, 3;
+ %jmp T_12.15;
+T_12.12 ;
+ %pushi/vec4 0, 0, 3;
+ %store/vec4 v0x12ef20770_0, 0, 3;
+ %jmp T_12.15;
+T_12.13 ;
+ %pushi/vec4 0, 0, 3;
+ %store/vec4 v0x12ef20770_0, 0, 3;
+ %jmp T_12.15;
+T_12.15 ;
+ %pop/vec4 1;
+ %jmp T_12.5;
+T_12.1 ;
+ %load/vec4 v0x12ef22640_0;
+ %dup/vec4;
+ %pushi/vec4 2, 0, 3;
+ %cmp/u;
+ %jmp/1 T_12.16, 6;
+ %dup/vec4;
+ %pushi/vec4 4, 0, 3;
+ %cmp/u;
+ %jmp/1 T_12.17, 6;
+ %dup/vec4;
+ %pushi/vec4 6, 0, 3;
+ %cmp/u;
+ %jmp/1 T_12.18, 6;
+ %dup/vec4;
+ %pushi/vec4 0, 0, 3;
+ %cmp/u;
+ %jmp/1 T_12.19, 6;
+ %dup/vec4;
+ %pushi/vec4 1, 0, 3;
+ %cmp/u;
+ %jmp/1 T_12.20, 6;
+ %dup/vec4;
+ %pushi/vec4 3, 0, 3;
+ %cmp/u;
+ %jmp/1 T_12.21, 6;
+ %dup/vec4;
+ %pushi/vec4 5, 0, 3;
+ %cmp/u;
+ %jmp/1 T_12.22, 6;
+ %dup/vec4;
+ %pushi/vec4 7, 0, 3;
+ %cmp/u;
+ %jmp/1 T_12.23, 6;
+ %pushi/vec4 0, 0, 3;
+ %store/vec4 v0x12ef20770_0, 0, 3;
+ %jmp T_12.25;
+T_12.16 ;
+ %pushi/vec4 2, 0, 3;
+ %store/vec4 v0x12ef20770_0, 0, 3;
+ %jmp T_12.25;
+T_12.17 ;
+ %pushi/vec4 3, 0, 3;
+ %store/vec4 v0x12ef20770_0, 0, 3;
+ %jmp T_12.25;
+T_12.18 ;
+ %pushi/vec4 4, 0, 3;
+ %store/vec4 v0x12ef20770_0, 0, 3;
+ %jmp T_12.25;
+T_12.19 ;
+ %pushi/vec4 0, 0, 3;
+ %store/vec4 v0x12ef20770_0, 0, 3;
+ %jmp T_12.25;
+T_12.20 ;
+ %pushi/vec4 0, 0, 3;
+ %store/vec4 v0x12ef20770_0, 0, 3;
+ %jmp T_12.25;
+T_12.21 ;
+ %pushi/vec4 0, 0, 3;
+ %store/vec4 v0x12ef20770_0, 0, 3;
+ %jmp T_12.25;
+T_12.22 ;
+ %pushi/vec4 0, 0, 3;
+ %store/vec4 v0x12ef20770_0, 0, 3;
+ %jmp T_12.25;
+T_12.23 ;
+ %pushi/vec4 0, 0, 3;
+ %store/vec4 v0x12ef20770_0, 0, 3;
+ %jmp T_12.25;
+T_12.25 ;
+ %pop/vec4 1;
+ %jmp T_12.5;
+T_12.2 ;
+ %load/vec4 v0x12ef22640_0;
+ %dup/vec4;
+ %pushi/vec4 2, 0, 3;
+ %cmp/u;
+ %jmp/1 T_12.26, 6;
+ %dup/vec4;
+ %pushi/vec4 4, 0, 3;
+ %cmp/u;
+ %jmp/1 T_12.27, 6;
+ %dup/vec4;
+ %pushi/vec4 6, 0, 3;
+ %cmp/u;
+ %jmp/1 T_12.28, 6;
+ %dup/vec4;
+ %pushi/vec4 0, 0, 3;
+ %cmp/u;
+ %jmp/1 T_12.29, 6;
+ %dup/vec4;
+ %pushi/vec4 1, 0, 3;
+ %cmp/u;
+ %jmp/1 T_12.30, 6;
+ %dup/vec4;
+ %pushi/vec4 3, 0, 3;
+ %cmp/u;
+ %jmp/1 T_12.31, 6;
+ %dup/vec4;
+ %pushi/vec4 5, 0, 3;
+ %cmp/u;
+ %jmp/1 T_12.32, 6;
+ %dup/vec4;
+ %pushi/vec4 7, 0, 3;
+ %cmp/u;
+ %jmp/1 T_12.33, 6;
+ %pushi/vec4 0, 0, 3;
+ %store/vec4 v0x12ef20770_0, 0, 3;
+ %jmp T_12.35;
+T_12.26 ;
+ %pushi/vec4 3, 0, 3;
+ %store/vec4 v0x12ef20770_0, 0, 3;
+ %jmp T_12.35;
+T_12.27 ;
+ %pushi/vec4 4, 0, 3;
+ %store/vec4 v0x12ef20770_0, 0, 3;
+ %jmp T_12.35;
+T_12.28 ;
+ %pushi/vec4 5, 0, 3;
+ %store/vec4 v0x12ef20770_0, 0, 3;
+ %jmp T_12.35;
+T_12.29 ;
+ %pushi/vec4 0, 0, 3;
+ %store/vec4 v0x12ef20770_0, 0, 3;
+ %jmp T_12.35;
+T_12.30 ;
+ %pushi/vec4 0, 0, 3;
+ %store/vec4 v0x12ef20770_0, 0, 3;
+ %jmp T_12.35;
+T_12.31 ;
+ %pushi/vec4 0, 0, 3;
+ %store/vec4 v0x12ef20770_0, 0, 3;
+ %jmp T_12.35;
+T_12.32 ;
+ %pushi/vec4 0, 0, 3;
+ %store/vec4 v0x12ef20770_0, 0, 3;
+ %jmp T_12.35;
+T_12.33 ;
+ %pushi/vec4 0, 0, 3;
+ %store/vec4 v0x12ef20770_0, 0, 3;
+ %jmp T_12.35;
+T_12.35 ;
+ %pop/vec4 1;
+ %jmp T_12.5;
+T_12.3 ;
+ %load/vec4 v0x12ef22640_0;
+ %dup/vec4;
+ %pushi/vec4 2, 0, 3;
+ %cmp/u;
+ %jmp/1 T_12.36, 6;
+ %dup/vec4;
+ %pushi/vec4 4, 0, 3;
+ %cmp/u;
+ %jmp/1 T_12.37, 6;
+ %dup/vec4;
+ %pushi/vec4 6, 0, 3;
+ %cmp/u;
+ %jmp/1 T_12.38, 6;
+ %dup/vec4;
+ %pushi/vec4 0, 0, 3;
+ %cmp/u;
+ %jmp/1 T_12.39, 6;
+ %dup/vec4;
+ %pushi/vec4 1, 0, 3;
+ %cmp/u;
+ %jmp/1 T_12.40, 6;
+ %dup/vec4;
+ %pushi/vec4 3, 0, 3;
+ %cmp/u;
+ %jmp/1 T_12.41, 6;
+ %dup/vec4;
+ %pushi/vec4 5, 0, 3;
+ %cmp/u;
+ %jmp/1 T_12.42, 6;
+ %dup/vec4;
+ %pushi/vec4 7, 0, 3;
+ %cmp/u;
+ %jmp/1 T_12.43, 6;
+ %pushi/vec4 0, 0, 3;
+ %store/vec4 v0x12ef20770_0, 0, 3;
+ %jmp T_12.45;
+T_12.36 ;
+ %pushi/vec4 4, 0, 3;
+ %store/vec4 v0x12ef20770_0, 0, 3;
+ %jmp T_12.45;
+T_12.37 ;
+ %pushi/vec4 5, 0, 3;
+ %store/vec4 v0x12ef20770_0, 0, 3;
+ %jmp T_12.45;
+T_12.38 ;
+ %pushi/vec4 6, 0, 3;
+ %store/vec4 v0x12ef20770_0, 0, 3;
+ %jmp T_12.45;
+T_12.39 ;
+ %pushi/vec4 0, 0, 3;
+ %store/vec4 v0x12ef20770_0, 0, 3;
+ %jmp T_12.45;
+T_12.40 ;
+ %pushi/vec4 0, 0, 3;
+ %store/vec4 v0x12ef20770_0, 0, 3;
+ %jmp T_12.45;
+T_12.41 ;
+ %pushi/vec4 0, 0, 3;
+ %store/vec4 v0x12ef20770_0, 0, 3;
+ %jmp T_12.45;
+T_12.42 ;
+ %pushi/vec4 0, 0, 3;
+ %store/vec4 v0x12ef20770_0, 0, 3;
+ %jmp T_12.45;
+T_12.43 ;
+ %pushi/vec4 0, 0, 3;
+ %store/vec4 v0x12ef20770_0, 0, 3;
+ %jmp T_12.45;
+T_12.45 ;
+ %pop/vec4 1;
+ %jmp T_12.5;
+T_12.5 ;
+ %pop/vec4 1;
+ %end;
+ .scope S_0x12ef17400;
+t_20 %join;
+ %jmp T_12;
+ .thread T_12, $push;
+ .scope S_0x12ef17400;
+T_13 ;
+ %wait E_0x12ef17ae0;
+ %fork t_23, S_0x12ef19ea0;
+ %jmp t_22;
+ .scope S_0x12ef19ea0;
+t_23 ;
+ %load/vec4 v0x12ef20770_0;
+ %dup/vec4;
+ %pushi/vec4 0, 0, 3;
+ %cmp/u;
+ %jmp/1 T_13.0, 6;
+ %dup/vec4;
+ %pushi/vec4 1, 0, 3;
+ %cmp/u;
+ %jmp/1 T_13.1, 6;
+ %dup/vec4;
+ %pushi/vec4 2, 0, 3;
+ %cmp/u;
+ %jmp/1 T_13.2, 6;
+ %dup/vec4;
+ %pushi/vec4 3, 0, 3;
+ %cmp/u;
+ %jmp/1 T_13.3, 6;
+ %dup/vec4;
+ %pushi/vec4 4, 0, 3;
+ %cmp/u;
+ %jmp/1 T_13.4, 6;
+ %dup/vec4;
+ %pushi/vec4 5, 0, 3;
+ %cmp/u;
+ %jmp/1 T_13.5, 6;
+ %dup/vec4;
+ %pushi/vec4 6, 0, 3;
+ %cmp/u;
+ %jmp/1 T_13.6, 6;
+ %pushi/vec4 0, 0, 32;
+ %store/vec4 v0x12ef22c40_0, 0, 32;
+ %jmp T_13.8;
+T_13.0 ;
+ %load/vec4 v0x12ef21640_0;
+ %store/vec4 v0x12ef22c40_0, 0, 32;
+ %jmp T_13.8;
+T_13.1 ;
+ %load/vec4 v0x12ef21640_0;
+ %parti/s 2, 0, 2;
+ %cmpi/e 0, 0, 2;
+ %jmp/0xz T_13.9, 6;
+ %load/vec4 v0x12ef204c0_0;
+ %parti/s 30, 2, 3;
+ %ix/load 4, 2, 0;
+ %flag_set/imm 4, 0;
+ %store/vec4 v0x12ef22c40_0, 4, 30;
+ %pushi/vec4 0, 0, 2;
+ %ix/load 4, 0, 0;
+ %flag_set/imm 4, 0;
+ %store/vec4 v0x12ef22c40_0, 4, 2;
+ %jmp T_13.10;
+T_13.9 ;
+ %load/vec4 v0x12ef21640_0;
+ %store/vec4 v0x12ef22c40_0, 0, 32;
+T_13.10 ;
+ %jmp T_13.8;
+T_13.2 ;
+ %load/vec4 v0x12ef21640_0;
+ %parti/s 3, 0, 2;
+ %cmpi/e 0, 0, 3;
+ %jmp/0xz T_13.11, 6;
+ %load/vec4 v0x12ef204c0_0;
+ %parti/s 29, 3, 3;
+ %ix/load 4, 3, 0;
+ %flag_set/imm 4, 0;
+ %store/vec4 v0x12ef22c40_0, 4, 29;
+ %pushi/vec4 0, 0, 3;
+ %ix/load 4, 0, 0;
+ %flag_set/imm 4, 0;
+ %store/vec4 v0x12ef22c40_0, 4, 3;
+ %jmp T_13.12;
+T_13.11 ;
+ %load/vec4 v0x12ef21640_0;
+ %store/vec4 v0x12ef22c40_0, 0, 32;
+T_13.12 ;
+ %jmp T_13.8;
+T_13.3 ;
+ %load/vec4 v0x12ef21640_0;
+ %parti/s 4, 0, 2;
+ %cmpi/e 0, 0, 4;
+ %jmp/0xz T_13.13, 6;
+ %load/vec4 v0x12ef204c0_0;
+ %parti/s 28, 4, 4;
+ %ix/load 4, 4, 0;
+ %flag_set/imm 4, 0;
+ %store/vec4 v0x12ef22c40_0, 4, 28;
+ %pushi/vec4 0, 0, 4;
+ %ix/load 4, 0, 0;
+ %flag_set/imm 4, 0;
+ %store/vec4 v0x12ef22c40_0, 4, 4;
+ %jmp T_13.14;
+T_13.13 ;
+ %load/vec4 v0x12ef21640_0;
+ %store/vec4 v0x12ef22c40_0, 0, 32;
+T_13.14 ;
+ %jmp T_13.8;
+T_13.4 ;
+ %load/vec4 v0x12ef21640_0;
+ %parti/s 5, 0, 2;
+ %cmpi/e 0, 0, 5;
+ %jmp/0xz T_13.15, 6;
+ %load/vec4 v0x12ef204c0_0;
+ %parti/s 27, 5, 4;
+ %ix/load 4, 5, 0;
+ %flag_set/imm 4, 0;
+ %store/vec4 v0x12ef22c40_0, 4, 27;
+ %pushi/vec4 0, 0, 5;
+ %ix/load 4, 0, 0;
+ %flag_set/imm 4, 0;
+ %store/vec4 v0x12ef22c40_0, 4, 5;
+ %jmp T_13.16;
+T_13.15 ;
+ %load/vec4 v0x12ef21640_0;
+ %store/vec4 v0x12ef22c40_0, 0, 32;
+T_13.16 ;
+ %jmp T_13.8;
+T_13.5 ;
+ %load/vec4 v0x12ef21640_0;
+ %parti/s 6, 0, 2;
+ %cmpi/e 0, 0, 6;
+ %jmp/0xz T_13.17, 6;
+ %load/vec4 v0x12ef204c0_0;
+ %parti/s 26, 6, 4;
+ %ix/load 4, 6, 0;
+ %flag_set/imm 4, 0;
+ %store/vec4 v0x12ef22c40_0, 4, 26;
+ %pushi/vec4 0, 0, 6;
+ %ix/load 4, 0, 0;
+ %flag_set/imm 4, 0;
+ %store/vec4 v0x12ef22c40_0, 4, 6;
+ %jmp T_13.18;
+T_13.17 ;
+ %load/vec4 v0x12ef21640_0;
+ %store/vec4 v0x12ef22c40_0, 0, 32;
+T_13.18 ;
+ %jmp T_13.8;
+T_13.6 ;
+ %load/vec4 v0x12ef21640_0;
+ %parti/s 7, 0, 2;
+ %cmpi/e 0, 0, 7;
+ %jmp/0xz T_13.19, 6;
+ %load/vec4 v0x12ef204c0_0;
+ %parti/s 25, 7, 4;
+ %ix/load 4, 7, 0;
+ %flag_set/imm 4, 0;
+ %store/vec4 v0x12ef22c40_0, 4, 25;
+ %pushi/vec4 0, 0, 7;
+ %ix/load 4, 0, 0;
+ %flag_set/imm 4, 0;
+ %store/vec4 v0x12ef22c40_0, 4, 7;
+ %jmp T_13.20;
+T_13.19 ;
+ %load/vec4 v0x12ef21640_0;
+ %store/vec4 v0x12ef22c40_0, 0, 32;
+T_13.20 ;
+ %jmp T_13.8;
+T_13.8 ;
+ %pop/vec4 1;
+ %end;
+ .scope S_0x12ef17400;
+t_22 %join;
+ %jmp T_13;
+ .thread T_13, $push;
+ .scope S_0x12ef17400;
+T_14 ;
+ %wait E_0x12ef17a80;
+ %fork t_25, S_0x12ef18ba0;
+ %jmp t_24;
+ .scope S_0x12ef18ba0;
+t_25 ;
+ %load/vec4 v0x12ef226f0_0;
+ %cmpi/e 80, 0, 8;
+ %jmp/0xz T_14.0, 6;
+ %load/vec4 v0x12ef21900_0;
+ %cmpi/e 2, 0, 2;
+ %jmp/0xz T_14.2, 6;
+ %pushi/vec4 2, 0, 2;
+ %store/vec4 v0x12ef21440_0, 0, 2;
+ %jmp T_14.3;
+T_14.2 ;
+ %pushi/vec4 0, 0, 2;
+ %store/vec4 v0x12ef21440_0, 0, 2;
+T_14.3 ;
+ %jmp T_14.1;
+T_14.0 ;
+ %load/vec4 v0x12ef1a900_0;
+ %pushi/vec4 1, 0, 3;
+ %cmp/e;
+ %flag_get/vec4 6;
+ %load/vec4 v0x12ef20e30_0;
+ %pushi/vec4 2, 0, 2;
+ %cmp/e;
+ %flag_get/vec4 6;
+ %and;
+ %load/vec4 v0x12ef1a720_0;
+ %pushi/vec4 1, 0, 1;
+ %cmp/e;
+ %flag_get/vec4 6;
+ %and;
+ %load/vec4 v0x12ef226f0_0;
+ %pushi/vec4 32, 0, 8;
+ %cmp/e;
+ %flag_get/vec4 6;
+ %load/vec4 v0x12ef226f0_0;
+ %pushi/vec4 48, 0, 8;
+ %cmp/e;
+ %flag_get/vec4 6;
+ %or;
+ %and;
+ %flag_set/vec4 8;
+ %jmp/0xz T_14.4, 8;
+ %pushi/vec4 0, 0, 2;
+ %store/vec4 v0x12ef21440_0, 0, 2;
+ %jmp T_14.5;
+T_14.4 ;
+ %load/vec4 v0x12ef226f0_0;
+ %dup/vec4;
+ %pushi/vec4 0, 0, 8;
+ %cmp/u;
+ %jmp/1 T_14.6, 6;
+ %dup/vec4;
+ %pushi/vec4 16, 0, 8;
+ %cmp/u;
+ %jmp/1 T_14.7, 6;
+ %dup/vec4;
+ %pushi/vec4 32, 0, 8;
+ %cmp/u;
+ %jmp/1 T_14.8, 6;
+ %dup/vec4;
+ %pushi/vec4 48, 0, 8;
+ %cmp/u;
+ %jmp/1 T_14.9, 6;
+ %dup/vec4;
+ %pushi/vec4 64, 0, 8;
+ %cmp/u;
+ %jmp/1 T_14.10, 6;
+ %dup/vec4;
+ %pushi/vec4 128, 0, 8;
+ %cmp/u;
+ %jmp/1 T_14.11, 6;
+ %pushi/vec4 0, 0, 2;
+ %store/vec4 v0x12ef21440_0, 0, 2;
+ %jmp T_14.13;
+T_14.6 ;
+ %pushi/vec4 2, 0, 2;
+ %store/vec4 v0x12ef21440_0, 0, 2;
+ %jmp T_14.13;
+T_14.7 ;
+ %pushi/vec4 2, 0, 2;
+ %store/vec4 v0x12ef21440_0, 0, 2;
+ %jmp T_14.13;
+T_14.8 ;
+ %pushi/vec4 3, 0, 2;
+ %store/vec4 v0x12ef21440_0, 0, 2;
+ %jmp T_14.13;
+T_14.9 ;
+ %pushi/vec4 1, 0, 2;
+ %store/vec4 v0x12ef21440_0, 0, 2;
+ %jmp T_14.13;
+T_14.10 ;
+ %pushi/vec4 0, 0, 2;
+ %store/vec4 v0x12ef21440_0, 0, 2;
+ %jmp T_14.13;
+T_14.11 ;
+ %pushi/vec4 0, 0, 2;
+ %store/vec4 v0x12ef21440_0, 0, 2;
+ %jmp T_14.13;
+T_14.13 ;
+ %pop/vec4 1;
+T_14.5 ;
+T_14.1 ;
+ %end;
+ .scope S_0x12ef17400;
+t_24 %join;
+ %jmp T_14;
+ .thread T_14, $push;
+ .scope S_0x12ef17400;
+T_15 ;
+ %wait E_0x12ef17a10;
+ %fork t_27, S_0x12ef181f0;
+ %jmp t_26;
+ .scope S_0x12ef181f0;
+t_27 ;
+ %load/vec4 v0x12ef22440_0;
+ %cmpi/e 1, 0, 1;
+ %jmp/0xz T_15.0, 6;
+ %load/vec4 v0x12ef22590_0;
+ %store/vec4 v0x12ef21390_0, 0, 8;
+ %jmp T_15.1;
+T_15.0 ;
+ %load/vec4 v0x12ef22af0_0;
+ %dup/vec4;
+ %pushi/vec4 0, 0, 3;
+ %cmp/u;
+ %jmp/1 T_15.2, 6;
+ %dup/vec4;
+ %pushi/vec4 1, 0, 3;
+ %cmp/u;
+ %jmp/1 T_15.3, 6;
+ %dup/vec4;
+ %pushi/vec4 2, 0, 3;
+ %cmp/u;
+ %jmp/1 T_15.4, 6;
+ %dup/vec4;
+ %pushi/vec4 3, 0, 3;
+ %cmp/u;
+ %jmp/1 T_15.5, 6;
+ %pushi/vec4 0, 0, 8;
+ %store/vec4 v0x12ef21390_0, 0, 8;
+ %jmp T_15.7;
+T_15.2 ;
+ %load/vec4 v0x12ef212e0_0;
+ %parti/s 3, 0, 2;
+ %dup/vec4;
+ %pushi/vec4 0, 0, 3;
+ %cmp/u;
+ %jmp/1 T_15.8, 6;
+ %dup/vec4;
+ %pushi/vec4 1, 0, 3;
+ %cmp/u;
+ %jmp/1 T_15.9, 6;
+ %dup/vec4;
+ %pushi/vec4 2, 0, 3;
+ %cmp/u;
+ %jmp/1 T_15.10, 6;
+ %dup/vec4;
+ %pushi/vec4 3, 0, 3;
+ %cmp/u;
+ %jmp/1 T_15.11, 6;
+ %dup/vec4;
+ %pushi/vec4 4, 0, 3;
+ %cmp/u;
+ %jmp/1 T_15.12, 6;
+ %dup/vec4;
+ %pushi/vec4 5, 0, 3;
+ %cmp/u;
+ %jmp/1 T_15.13, 6;
+ %dup/vec4;
+ %pushi/vec4 6, 0, 3;
+ %cmp/u;
+ %jmp/1 T_15.14, 6;
+ %dup/vec4;
+ %pushi/vec4 7, 0, 3;
+ %cmp/u;
+ %jmp/1 T_15.15, 6;
+ %pushi/vec4 0, 0, 8;
+ %store/vec4 v0x12ef21390_0, 0, 8;
+ %jmp T_15.17;
+T_15.8 ;
+ %pushi/vec4 1, 0, 8;
+ %store/vec4 v0x12ef21390_0, 0, 8;
+ %jmp T_15.17;
+T_15.9 ;
+ %pushi/vec4 2, 0, 8;
+ %store/vec4 v0x12ef21390_0, 0, 8;
+ %jmp T_15.17;
+T_15.10 ;
+ %pushi/vec4 4, 0, 8;
+ %store/vec4 v0x12ef21390_0, 0, 8;
+ %jmp T_15.17;
+T_15.11 ;
+ %pushi/vec4 8, 0, 8;
+ %store/vec4 v0x12ef21390_0, 0, 8;
+ %jmp T_15.17;
+T_15.12 ;
+ %pushi/vec4 16, 0, 8;
+ %store/vec4 v0x12ef21390_0, 0, 8;
+ %jmp T_15.17;
+T_15.13 ;
+ %pushi/vec4 32, 0, 8;
+ %store/vec4 v0x12ef21390_0, 0, 8;
+ %jmp T_15.17;
+T_15.14 ;
+ %pushi/vec4 64, 0, 8;
+ %store/vec4 v0x12ef21390_0, 0, 8;
+ %jmp T_15.17;
+T_15.15 ;
+ %pushi/vec4 128, 0, 8;
+ %store/vec4 v0x12ef21390_0, 0, 8;
+ %jmp T_15.17;
+T_15.17 ;
+ %pop/vec4 1;
+ %jmp T_15.7;
+T_15.3 ;
+ %load/vec4 v0x12ef212e0_0;
+ %parti/s 3, 0, 2;
+ %dup/vec4;
+ %pushi/vec4 0, 0, 3;
+ %cmp/u;
+ %jmp/1 T_15.18, 6;
+ %dup/vec4;
+ %pushi/vec4 2, 0, 3;
+ %cmp/u;
+ %jmp/1 T_15.19, 6;
+ %dup/vec4;
+ %pushi/vec4 4, 0, 3;
+ %cmp/u;
+ %jmp/1 T_15.20, 6;
+ %dup/vec4;
+ %pushi/vec4 6, 0, 3;
+ %cmp/u;
+ %jmp/1 T_15.21, 6;
+ %pushi/vec4 0, 0, 8;
+ %store/vec4 v0x12ef21390_0, 0, 8;
+ %jmp T_15.23;
+T_15.18 ;
+ %pushi/vec4 3, 0, 8;
+ %store/vec4 v0x12ef21390_0, 0, 8;
+ %jmp T_15.23;
+T_15.19 ;
+ %pushi/vec4 12, 0, 8;
+ %store/vec4 v0x12ef21390_0, 0, 8;
+ %jmp T_15.23;
+T_15.20 ;
+ %pushi/vec4 48, 0, 8;
+ %store/vec4 v0x12ef21390_0, 0, 8;
+ %jmp T_15.23;
+T_15.21 ;
+ %pushi/vec4 192, 0, 8;
+ %store/vec4 v0x12ef21390_0, 0, 8;
+ %jmp T_15.23;
+T_15.23 ;
+ %pop/vec4 1;
+ %jmp T_15.7;
+T_15.4 ;
+ %load/vec4 v0x12ef212e0_0;
+ %parti/s 3, 0, 2;
+ %dup/vec4;
+ %pushi/vec4 0, 0, 3;
+ %cmp/u;
+ %jmp/1 T_15.24, 6;
+ %dup/vec4;
+ %pushi/vec4 4, 0, 3;
+ %cmp/u;
+ %jmp/1 T_15.25, 6;
+ %pushi/vec4 0, 0, 8;
+ %store/vec4 v0x12ef21390_0, 0, 8;
+ %jmp T_15.27;
+T_15.24 ;
+ %pushi/vec4 15, 0, 8;
+ %store/vec4 v0x12ef21390_0, 0, 8;
+ %jmp T_15.27;
+T_15.25 ;
+ %pushi/vec4 240, 0, 8;
+ %store/vec4 v0x12ef21390_0, 0, 8;
+ %jmp T_15.27;
+T_15.27 ;
+ %pop/vec4 1;
+ %jmp T_15.7;
+T_15.5 ;
+ %load/vec4 v0x12ef212e0_0;
+ %parti/s 3, 0, 2;
+ %dup/vec4;
+ %pushi/vec4 0, 0, 3;
+ %cmp/u;
+ %jmp/1 T_15.28, 6;
+ %pushi/vec4 0, 0, 8;
+ %store/vec4 v0x12ef21390_0, 0, 8;
+ %jmp T_15.30;
+T_15.28 ;
+ %pushi/vec4 255, 0, 8;
+ %store/vec4 v0x12ef21390_0, 0, 8;
+ %jmp T_15.30;
+T_15.30 ;
+ %pop/vec4 1;
+ %jmp T_15.7;
+T_15.7 ;
+ %pop/vec4 1;
+T_15.1 ;
+ %end;
+ .scope S_0x12ef17400;
+t_26 %join;
+ %jmp T_15;
+ .thread T_15, $push;
+ .scope S_0x12ef17400;
+T_16 ;
+ %wait E_0x12ef16910;
+ %fork t_29, S_0x12ef196a0;
+ %jmp t_28;
+ .scope S_0x12ef196a0;
+t_29 ;
+ %load/vec4 v0x12ef1a7d0_0;
+ %cmpi/ne 1, 0, 1;
+ %jmp/0xz T_16.0, 6;
+ %pushi/vec4 0, 0, 64;
+ %assign/vec4 v0x12ef21190_0, 0;
+ %jmp T_16.1;
+T_16.0 ;
+ %load/vec4 v0x12ef1a720_0;
+ %cmpi/e 1, 0, 1;
+ %jmp/0xz T_16.2, 6;
+ %load/vec4 v0x12ef214f0_0;
+ %assign/vec4 v0x12ef21190_0, 0;
+T_16.2 ;
+T_16.1 ;
+ %end;
+ .scope S_0x12ef17400;
+t_28 %join;
+ %jmp T_16;
+ .thread T_16;
+ .scope S_0x12ef17400;
+T_17 ;
+ %wait E_0x12ef179b0;
+ %fork t_31, S_0x12ef189e0;
+ %jmp t_30;
+ .scope S_0x12ef189e0;
+t_31 ;
+ %load/vec4 v0x12ef21240_0;
+ %pushi/vec4 0, 0, 1;
+ %cmp/e;
+ %flag_get/vec4 6;
+ %load/vec4 v0x12ef1a900_0;
+ %pushi/vec4 0, 0, 3;
+ %cmp/e;
+ %flag_get/vec4 6;
+ %and;
+ %load/vec4 v0x12ef210e0_0;
+ %pushi/vec4 2, 0, 2;
+ %cmp/e;
+ %flag_get/vec4 6;
+ %load/vec4 v0x12ef210e0_0;
+ %pushi/vec4 3, 0, 2;
+ %cmp/e;
+ %flag_get/vec4 6;
+ %or;
+ %and;
+ %flag_set/vec4 8;
+ %jmp/0xz T_17.0, 8;
+ %load/vec4 v0x12ef20cd0_0;
+ %load/vec4 v0x12ef217a0_0;
+ %and;
+ %load/vec4 v0x12ef1a680_0;
+ %load/vec4 v0x12ef217a0_0;
+ %and;
+ %xor;
+ %store/vec4 v0x12ef20ad0_0, 0, 64;
+ %jmp T_17.1;
+T_17.0 ;
+ %pushi/vec4 0, 0, 64;
+ %store/vec4 v0x12ef20ad0_0, 0, 64;
+T_17.1 ;
+ %end;
+ .scope S_0x12ef17400;
+t_30 %join;
+ %jmp T_17;
+ .thread T_17, $push;
+ .scope S_0x12ef17400;
+T_18 ;
+ %wait E_0x12ef17940;
+ %fork t_33, S_0x12ef18fa0;
+ %jmp t_32;
+ .scope S_0x12ef18fa0;
+t_33 ;
+ %load/vec4 v0x12ef21bb0_0;
+ %dup/vec4;
+ %pushi/vec4 0, 0, 2;
+ %cmp/u;
+ %jmp/1 T_18.0, 6;
+ %dup/vec4;
+ %pushi/vec4 2, 0, 2;
+ %cmp/u;
+ %jmp/1 T_18.1, 6;
+ %dup/vec4;
+ %pushi/vec4 1, 0, 2;
+ %cmp/u;
+ %jmp/1 T_18.2, 6;
+ %pushi/vec4 0, 0, 2;
+ %store/vec4 v0x12ef21900_0, 0, 2;
+ %load/vec4 v0x12ef21a50_0;
+ %store/vec4 v0x12ef21850_0, 0, 32;
+ %jmp T_18.4;
+T_18.0 ;
+ %load/vec4 v0x12ef226f0_0;
+ %cmpi/e 80, 0, 8;
+ %jmp/0xz T_18.5, 6;
+ %pushi/vec4 2, 0, 2;
+ %store/vec4 v0x12ef21900_0, 0, 2;
+ %load/vec4 v0x12ef22240_0;
+ %store/vec4 v0x12ef21850_0, 0, 32;
+ %jmp T_18.6;
+T_18.5 ;
+ %pushi/vec4 0, 0, 2;
+ %store/vec4 v0x12ef21900_0, 0, 2;
+ %load/vec4 v0x12ef21a50_0;
+ %store/vec4 v0x12ef21850_0, 0, 32;
+T_18.6 ;
+ %jmp T_18.4;
+T_18.1 ;
+ %load/vec4 v0x12ef20b80_0;
+ %cmpi/e 0, 0, 1;
+ %flag_mov 8, 6;
+ %load/vec4 v0x12ef21a50_0;
+ %cmpi/e 1, 0, 32;
+ %flag_or 6, 8;
+ %jmp/0xz T_18.7, 6;
+ %pushi/vec4 0, 0, 2;
+ %store/vec4 v0x12ef21900_0, 0, 2;
+ %pushi/vec4 0, 0, 32;
+ %store/vec4 v0x12ef21850_0, 0, 32;
+ %jmp T_18.8;
+T_18.7 ;
+ %pushi/vec4 1, 0, 2;
+ %store/vec4 v0x12ef21900_0, 0, 2;
+ %load/vec4 v0x12ef21a50_0;
+ %cmpi/ne 0, 0, 32;
+ %jmp/0xz T_18.9, 6;
+ %load/vec4 v0x12ef21a50_0;
+ %subi 1, 0, 32;
+ %store/vec4 v0x12ef21850_0, 0, 32;
+ %jmp T_18.10;
+T_18.9 ;
+ %load/vec4 v0x12ef21a50_0;
+ %store/vec4 v0x12ef21850_0, 0, 32;
+T_18.10 ;
+T_18.8 ;
+ %jmp T_18.4;
+T_18.2 ;
+ %pushi/vec4 2, 0, 2;
+ %store/vec4 v0x12ef21900_0, 0, 2;
+ %load/vec4 v0x12ef21a50_0;
+ %store/vec4 v0x12ef21850_0, 0, 32;
+ %jmp T_18.4;
+T_18.4 ;
+ %pop/vec4 1;
+ %end;
+ .scope S_0x12ef17400;
+t_32 %join;
+ %jmp T_18;
+ .thread T_18, $push;
+ .scope S_0x12ef17400;
+T_19 ;
+ %wait E_0x12ef16910;
+ %fork t_35, S_0x12ef19160;
+ %jmp t_34;
+ .scope S_0x12ef19160;
+t_35 ;
+ %load/vec4 v0x12ef1a7d0_0;
+ %cmpi/ne 1, 0, 1;
+ %jmp/0xz T_19.0, 6;
+ %pushi/vec4 0, 0, 2;
+ %assign/vec4 v0x12ef21bb0_0, 0;
+ %pushi/vec4 0, 0, 32;
+ %assign/vec4 v0x12ef21a50_0, 0;
+ %jmp T_19.1;
+T_19.0 ;
+ %load/vec4 v0x12ef1a720_0;
+ %cmpi/e 1, 0, 1;
+ %jmp/0xz T_19.2, 6;
+ %load/vec4 v0x12ef21900_0;
+ %assign/vec4 v0x12ef21bb0_0, 0;
+ %load/vec4 v0x12ef21850_0;
+ %assign/vec4 v0x12ef21a50_0, 0;
+T_19.2 ;
+T_19.1 ;
+ %end;
+ .scope S_0x12ef17400;
+t_34 %join;
+ %jmp T_19;
+ .thread T_19;
+ .scope S_0x12ef16630;
+T_20 ;
+ %wait E_0x12ef16910;
+ %fork t_37, S_0x12ef16950;
+ %jmp t_36;
+ .scope S_0x12ef16950;
+t_37 ;
+ %load/vec4 v0x12ef17080_0;
+ %cmpi/e 0, 0, 1;
+ %jmp/0xz T_20.0, 4;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x12ef17280_0, 0;
+ %jmp T_20.1;
+T_20.0 ;
+ %load/vec4 v0x12ef16fa0_0;
+ %cmpi/e 1, 0, 1;
+ %jmp/0xz T_20.2, 4;
+ %load/vec4 v0x12ef16cf0_0;
+ %assign/vec4 v0x12ef17280_0, 0;
+T_20.2 ;
+T_20.1 ;
+ %end;
+ .scope S_0x12ef16630;
+t_36 %join;
+ %jmp T_20;
+ .thread T_20;
+ .scope S_0x12ef16630;
+T_21 ;
+ %wait E_0x12ef168c0;
+ %fork t_39, S_0x12ef16b20;
+ %jmp t_38;
+ .scope S_0x12ef16b20;
+t_39 ;
+ %load/vec4 v0x12ef17280_0;
+ %cmpi/e 0, 0, 1;
+ %jmp/0xz T_21.0, 4;
+ %load/vec4 v0x12ef171d0_0;
+ %parti/s 32, 0, 2;
+ %store/vec4 v0x12ef17120_0, 0, 32;
+ %jmp T_21.1;
+T_21.0 ;
+ %load/vec4 v0x12ef171d0_0;
+ %parti/s 32, 32, 7;
+ %store/vec4 v0x12ef17120_0, 0, 32;
+T_21.1 ;
+ %end;
+ .scope S_0x12ef16630;
+t_38 %join;
+ %jmp T_21;
+ .thread T_21, $push;
+# The file index is used to find the file name in the following table.
+:file_names 7;
+ "N/A";
+ "<interactive>";
+ "-";
+ "/Users/davidmapstone/Documents/SoCLabs/accelerator-wrapper/hdl/verif//cmsdk_ahb_default_slave.v";
+ "/Users/davidmapstone/Documents/SoCLabs/accelerator-wrapper/hdl/verif//cmsdk_ahb_fileread_master32.v";
+ "/Users/davidmapstone/Documents/SoCLabs/accelerator-wrapper/hdl/verif//cmsdk_ahb_fileread_funnel.v";
+ "/Users/davidmapstone/Documents/SoCLabs/accelerator-wrapper/hdl/verif//cmsdk_ahb_filereadcore.v";
diff --git a/sourceme b/sourceme
index 11db5ad7bee3a314061cb45c77907da4935e3914..76b9c89b81d84d841b9da44f22fe22e6fb33ce70 100755
--- a/sourceme
+++ b/sourceme
@@ -15,18 +15,30 @@ if [ -z "$WRAP_ACC_DIR" ]; then
# Set environment Variables for Repository
export WRAP_ACC_DIR="$( cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P )"
- # Add flow directory to Path
- export PATH=$PATH:$WRAP_ACC_DIR/flow
+ if [ -z "$SOC_ENV_SET" ]; then
+ # Add flow directory to Path
+ export PATH=$PATH:$WRAP_ACC_DIR/flow
- # Set Default Simulator
- export SIMULATOR="ivlog"
+ # Set Default Simulator
+ export SIMULATOR="ivlog"
- # Source Top-level sourceme
- for d in $WRAP_ACC_DIR/../* ; do
- if [ -d "$d" ]; then
- if test -f "$d/sourceme"; then
- source $d/sourceme
+ # Set Top-level Directory
+ export SOC_TOP=$WRAP_ACC_DIR
+
+ # Set flag to say this is top level repo
+ export SOC_ENV_SET="True"
+
+ # Source Top-level sourceme
+ for d in $WRAP_ACC_DIR/../* ; do
+ if [ -d "$d" ]; then
+ if test -f "$d/sourceme"; then
+ source $d/sourceme
+ fi
fi
- fi
- done
+ done
+
+ # Clear SOC_ENV_SET Variable
+ unset SOC_ENV_SET
+
+ fi
fi
\ No newline at end of file