From 586383534848fe84a20b915c32bf40843190bbcd Mon Sep 17 00:00:00 2001
From: David Mapstone <david@mapstone.me>
Date: Mon, 20 Mar 2023 16:48:53 +0000
Subject: [PATCH] SOC1-141: Created Basic AHB Packet Deconstructor module and
updated signal names
---
flist/wrapper_ip.flist | 1 +
hdl/src/wrapper_ahb_packet_constructor.sv | 30 ++---
hdl/src/wrapper_ahb_packet_deconstructor.sv | 134 ++++++++++++++++++++
hdl/src/wrapper_data_req.sv | 20 +--
hdl/src/wrapper_packet_construct.sv | 4 +-
5 files changed, 162 insertions(+), 27 deletions(-)
create mode 100644 hdl/src/wrapper_ahb_packet_deconstructor.sv
diff --git a/flist/wrapper_ip.flist b/flist/wrapper_ip.flist
index 3ef4523..865ac08 100644
--- a/flist/wrapper_ip.flist
+++ b/flist/wrapper_ip.flist
@@ -20,6 +20,7 @@
+incdir+$(ACC_WRAPPER_DIR)/hdl/src/
$(ACC_WRAPPER_DIR)/hdl/src/wrapper_ahb_packet_constructor.sv
+$(ACC_WRAPPER_DIR)/hdl/src/wrapper_ahb_packet_deconstructor.sv
$(ACC_WRAPPER_DIR)/hdl/src/wrapper_data_req.sv
$(ACC_WRAPPER_DIR)/hdl/src/wrapper_ahb_reg_interface.sv
diff --git a/hdl/src/wrapper_ahb_packet_constructor.sv b/hdl/src/wrapper_ahb_packet_constructor.sv
index 65d3f83..47546ac 100644
--- a/hdl/src/wrapper_ahb_packet_constructor.sv
+++ b/hdl/src/wrapper_ahb_packet_constructor.sv
@@ -49,8 +49,8 @@ module wrapper_ahb_packet_constructor #(
logic wready;
logic rready;
- // Engine Ready for more Data
- logic engine_ready;
+ // Constructor Ready for more Data
+ logic constructor_ready;
// AHB Interface Instantiation
wrapper_ahb_reg_interface #(
@@ -85,29 +85,29 @@ module wrapper_ahb_packet_constructor #(
// Data Request Signal Generator
wrapper_data_req #(
- ADDRWIDTH, // Only half address map allocated to this device
- 512 // Packet Width
+ ADDRWIDTH, // Only half address map allocated to this device
+ PACKETWIDTH // Packet Width
) u_wrapper_data_req (
- .hclk (hclk),
- .hresetn (hresetn),
+ .hclk (hclk),
+ .hresetn (hresetn),
// AHB Address Phase Signaling
- .hsels (hsels),
- .haddrs (haddrs),
- .htranss (htranss),
- .hreadys (hreadys),
+ .hsels (hsels),
+ .haddrs (haddrs),
+ .htranss (htranss),
+ .hreadys (hreadys),
// Engine Data Ready Signal
- .engine_ready (engine_ready),
+ .constructor_ready (constructor_ready),
// Data Request Signal
- .data_req (data_req)
+ .data_req (data_req)
);
// Valid/Ready Packet Generator
wrapper_packet_construct #(
- ADDRWIDTH, // Only half address map allocated to this device
- 512 // Packet Width
+ ADDRWIDTH, // Only half address map allocated to this device
+ PACKETWIDTH // Packet Width
) u_wrapper_packet_construct (
.hclk (hclk),
.hresetn (hresetn),
@@ -129,6 +129,6 @@ module wrapper_ahb_packet_constructor #(
.packet_data_ready (packet_data_ready),
// Data Request
- .engine_ready (engine_ready)
+ .constructor_ready (constructor_ready)
);
endmodule
\ No newline at end of file
diff --git a/hdl/src/wrapper_ahb_packet_deconstructor.sv b/hdl/src/wrapper_ahb_packet_deconstructor.sv
new file mode 100644
index 0000000..408cee3
--- /dev/null
+++ b/hdl/src/wrapper_ahb_packet_deconstructor.sv
@@ -0,0 +1,134 @@
+//-----------------------------------------------------------------------------
+// SoC Labs AHB Packet Deconstructor
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright 2023, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+module wrapper_ahb_packet_deconstructor #(
+ //parameter for address width
+ parameter ADDRWIDTH=11,
+ parameter PACKETWIDTH=256
+)(
+ input logic hclk, // clock
+ input logic hresetn, // reset
+
+ // AHB Input Port
+ input logic hsels,
+ input logic [ADDRWIDTH-1:0] haddrs,
+ input logic [1:0] htranss,
+ input logic [2:0] hsizes,
+ input logic hwrites,
+ input logic hreadys,
+ input logic [31:0] hwdatas,
+
+ output logic hreadyouts,
+ output logic hresps,
+ output logic [31:0] hrdatas,
+
+ // Valid/Ready Input Port
+ input logic [PACKETWIDTH-1:0] packet_data,
+ input logic packet_data_last,
+ input logic packet_data_valid,
+ output logic packet_data_ready,
+
+ // Data Request Signal
+ output logic data_req
+ );
+
+ // Register Interface Connections
+ logic [ADDRWIDTH-1:0] addr;
+ logic read_en;
+ logic write_en;
+ logic [3:0] byte_strobe;
+ logic [31:0] wdata;
+ logic [31:0] rdata;
+ logic wready;
+ logic rready;
+
+ // Deconstructor Ready for more Data
+ logic deconstructor_ready;
+
+ // AHB Interface Instantiation
+ wrapper_ahb_reg_interface #(
+ ADDRWIDTH
+ ) ahb_reg_interface_inst (
+ .hclk (hclk),
+ .hresetn (hresetn),
+
+ // Input slave port: 32 bit data bus interface
+ .hsels (hsels),
+ .haddrs (haddrs),
+ .htranss (htranss),
+ .hsizes (hsizes),
+ .hwrites (hwrites),
+ .hreadys (hreadys),
+ .hwdatas (hwdatas),
+
+ .hreadyouts (hreadyouts),
+ .hresps (hresps),
+ .hrdatas (hrdatas),
+
+ // Register Output interface
+ .addr (addr),
+ .read_en (read_en),
+ .write_en (write_en),
+ .byte_strobe (byte_strobe),
+ .wdata (wdata),
+ .rdata (rdata),
+ .wready (wready),
+ .rready (rready)
+ );
+
+ // Data Request Signal Generator
+ wrapper_data_req #(
+ ADDRWIDTH, // Only half address map allocated to this device
+ PACKETWIDTH // Packet Width
+ ) u_wrapper_data_req (
+ .hclk (hclk),
+ .hresetn (hresetn),
+
+ // AHB Address Phase Signaling
+ .hsels (hsels),
+ .haddrs (haddrs),
+ .htranss (htranss),
+ .hreadys (hreadys),
+
+ // Constructor Data Ready Signal
+ .constructor_ready (deconstructor_ready),
+
+ // Data Request Signal
+ .data_req (data_req)
+ );
+
+ // Valid/Ready Packet Generator
+ wrapper_packet_deconstruct #(
+ ADDRWIDTH, // Only half address map allocated to this device
+ PACKETWIDTH // Packet Width
+ ) u_wrapper_packet_deconstruct (
+ .hclk (hclk),
+ .hresetn (hresetn),
+
+ // Register interface
+ .addr (addr),
+ .read_en (read_en),
+ .write_en (write_en),
+ .byte_strobe (byte_strobe),
+ .wdata (wdata),
+ .rdata (rdata),
+ .wready (wready),
+ .rready (rready),
+
+ // Valid/Ready Interface
+ .packet_data (packet_data),
+ .packet_data_last (packet_data_last),
+ .packet_data_valid (packet_data_valid),
+ .packet_data_ready (packet_data_ready),
+
+ // Data Request
+ .deconstructor_ready (deconstructor_ready)
+ );
+endmodule
\ No newline at end of file
diff --git a/hdl/src/wrapper_data_req.sv b/hdl/src/wrapper_data_req.sv
index 39801e4..abb5042 100644
--- a/hdl/src/wrapper_data_req.sv
+++ b/hdl/src/wrapper_data_req.sv
@@ -26,8 +26,8 @@ module wrapper_data_req #(
input logic [1:0] htranss,
input logic hreadys,
- // Engine Hungry Signal
- input logic engine_ready,
+ // Constructor/Deconstructor Ready Signal
+ input logic constructor_ready,
// Connection to wrapper
output logic data_req
@@ -44,19 +44,19 @@ assign trans_req = hreadys & hsels & htranss[1];
logic packet_last_word;
assign packet_last_word = &haddrs[PACKETBYTEWIDTH-1:REGDBYTEWIDTH];
-// If engine_ready => data_req EXCEPT if current address is last address
-logic engine_ready_reg;
+// If constructor_ready => data_req EXCEPT if current address is last address
+logic constructor_ready_reg;
logic data_req_latched;
always_ff @(posedge hclk or negedge hresetn) begin
if (~hresetn) begin
- engine_ready_reg <= 1'b0;
+ constructor_ready_reg <= 1'b0;
data_req_latched <= 1'b0;
end else begin
// Buffer engine ready signal to determine state change
- engine_ready_reg <= engine_ready;
+ constructor_ready_reg <= constructor_ready;
// Latch data request signal once seen last address of packet
- if (trans_req && packet_last_word && engine_ready) begin
+ if (trans_req && packet_last_word && constructor_ready) begin
// Latch data request signal
data_req_latched <= 1'b1;
// Unlatch when latched and data phase finished
@@ -68,9 +68,9 @@ always_ff @(posedge hclk or negedge hresetn) begin
end
always_comb begin
- if (~engine_ready_reg) begin
+ if (~constructor_ready_reg) begin
// If engine ready is transitioning from low to high
- data_req = engine_ready;
+ data_req = constructor_ready;
end else begin
// If seeing last word of packet address and valid transfer request
if ((trans_req && packet_last_word) || data_req_latched) begin
@@ -78,7 +78,7 @@ always_comb begin
data_req = 1'b0;
end else begin
// After data phase, take value of engine ready
- data_req = engine_ready;
+ data_req = constructor_ready;
end
end
end
diff --git a/hdl/src/wrapper_packet_construct.sv b/hdl/src/wrapper_packet_construct.sv
index a0fb999..238b5ee 100644
--- a/hdl/src/wrapper_packet_construct.sv
+++ b/hdl/src/wrapper_packet_construct.sv
@@ -33,7 +33,7 @@ module wrapper_packet_construct #(
input logic packet_data_ready,
// Data Input Request
- output logic engine_ready
+ output logic constructor_ready
);
localparam REGDWIDTH = 32; // Register Data Width
@@ -75,7 +75,7 @@ assign packet_addr_last = &packet_addr;
assign prev_packet_addr_last = &prev_packet_addr;
// Engine Ready Assignment
-assign engine_ready = packet_data_ready;
+assign constructor_ready = packet_data_ready;
// Write data out when either:
// - Word is last address of current packet
--
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