From 0c8cc3321eb9d8fc9e65d957d973e49535ac85b5 Mon Sep 17 00:00:00 2001
From: dam1n19 <dam1n19@soton.ac.uk>
Date: Mon, 27 Feb 2023 10:55:43 +0000
Subject: [PATCH] Added Design Filelist and fixed lint errors
---
flist/accelerator-wrapper_src.flist | 25 +++++++++
hdl/src/wrapper_packet_deconstruct.sv | 8 +--
hdl/src/wrapper_sha256_hashing_stream.sv | 67 +++---------------------
3 files changed, 35 insertions(+), 65 deletions(-)
create mode 100644 flist/accelerator-wrapper_src.flist
diff --git a/flist/accelerator-wrapper_src.flist b/flist/accelerator-wrapper_src.flist
new file mode 100644
index 0000000..1ab862a
--- /dev/null
+++ b/flist/accelerator-wrapper_src.flist
@@ -0,0 +1,25 @@
+//-----------------------------------------------------------------------------
+// Accelerator Wrapper Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for Accelerator Wrapper example
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// ============= Accelerator Module search path =============
+-y $DESIGN/accelerator-wrapper/hdl/src/
++incdir+$DESIGN/accelerator-wrapper/hdl/src/
+
+$DESIGN/accelerator-wrapper/hdl/src/wrapper_ahb_interface.sv
+$DESIGN/accelerator-wrapper/hdl/src/wrapper_packet_construct.sv
+$DESIGN/accelerator-wrapper/hdl/src/wrapper_packet_deconstruct.sv
+$DESIGN/accelerator-wrapper/hdl/src/wrapper_sha256_hashing_stream.sv
\ No newline at end of file
diff --git a/hdl/src/wrapper_packet_deconstruct.sv b/hdl/src/wrapper_packet_deconstruct.sv
index e27af44..cb3656d 100644
--- a/hdl/src/wrapper_packet_deconstruct.sv
+++ b/hdl/src/wrapper_packet_deconstruct.sv
@@ -40,6 +40,10 @@ logic [(PACKETWIDTH/32)-1:0][31:0] deconst_buf;
// Create Array to Flag which buffers have been read
logic [(PACKETWIDTH/32)-1:0] deconst_buf_flag;
+// Select which word in buffer to read
+logic [$clog2(PACKETWIDTH/32)-1:0] buf_word_sel;
+assign buf_word_sel = addr[($clog2(PACKETWIDTH/32)-1)+2:2];
+
// Curent Buffer Flag
logic [(PACKETWIDTH/32)-1:0] cur_deconst_buf_flag;
assign cur_deconst_buf_flag = 1'b1 << buf_word_sel;
@@ -48,10 +52,6 @@ assign cur_deconst_buf_flag = 1'b1 << buf_word_sel;
logic deconst_buf_flag_reduced;
assign deconst_buf_flag_reduced = &(deconst_buf_flag | (cur_deconst_buf_flag));
-// Select which word in buffer to read
-logic [$clog2(PACKETWIDTH/32)-1:0] buf_word_sel;
-assign buf_word_sel = addr[($clog2(PACKETWIDTH/32)-1)+2:2];
-
logic deconst_buf_valid;
// Dump data on one of two conditions
// - An address ends [5:0] in 0x3C i.e. [5:2] == 0xF
diff --git a/hdl/src/wrapper_sha256_hashing_stream.sv b/hdl/src/wrapper_sha256_hashing_stream.sv
index bb41e4c..8a2ba98 100644
--- a/hdl/src/wrapper_sha256_hashing_stream.sv
+++ b/hdl/src/wrapper_sha256_hashing_stream.sv
@@ -35,15 +35,14 @@
// each register can be accessed by byte, half word or word.
// The example slave always output ready and OKAY response to the master
//-----------------------------------------------------------------------------
-`timescale 1ns/1ns
-`include "wrapper_packet_construct.sv"
-`include "wrapper_packet_deconstruct.sv"
-`include "wrapper_ahb_interface.sv"
-`include "sha256_hashing_stream.sv"
+// `include "wrapper_packet_construct.sv"
+// `include "wrapper_packet_deconstruct.sv"
+// `include "wrapper_ahb_interface.sv"
+// `include "sha256_hashing_stream.sv"
module wrapper_sha256_hashing_stream #(
- parameter ADDRWIDTH=12 // Peripheral Address Width
- )(
+ parameter ADDRWIDTH=12
+ ) (
input logic HCLK, // Clock
input logic HRESETn, // Reset
@@ -237,58 +236,4 @@ module wrapper_sha256_hashing_stream #(
.packet_data_ready (out_packet_ready)
);
- //-----------------------------------------------------------
- //Module logic end
- //----------------------------------------------------------
-`ifdef ARM_AHB_ASSERT_ON
-
- `include "std_ovl_defines.h"
- // ------------------------------------------------------------
- // Assertions
- // ------------------------------------------------------------
-
- logic ovl_trans_req = HREADYS & HSELS & HTRANSS[1];
-
- // Check the reg_write_en signal generated
- assert_next
- #(`OVL_ERROR, 1,1,0,
- `OVL_ASSERT,
- "Error! register write signal was not generated! "
- )
- u_ovl_ahb_eg_slave_reg_write
- (.clk ( HCLK ),
- .reset_n (HRESETn),
- .start_event ((ovl_trans_req & HWRITES)),
- .test_expr (reg_write_en == 1'b1)
- );
-
-
- // Check the reg_read_en signal generated
- assert_next
- #(`OVL_ERROR, 1,1,0,
- `OVL_ASSERT,
- "Error! register read signal was not generated! "
- )
- u_ovl_ahb_eg_slave_reg_read
- (.clk ( HCLK ),
- .reset_n (HRESETn),
- .start_event ((ovl_trans_req & (~HWRITES))),
- .test_expr (reg_read_en == 1'b1)
- );
-
-
-
- // Check register read and write operation won't assert at the same cycle
- assert_never
- #(`OVL_ERROR,
- `OVL_ASSERT,
- "Error! register read and write active at the same cycle!")
- u_ovl_ahb_eg_slave_rd_wr_illegal
- (.clk(HCLK),
- .reset_n(HRESETn),
- .test_expr((reg_write_en & reg_read_en))
- );
-
-`endif
-
endmodule
\ No newline at end of file
--
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