From 0748aa7d6c1186bf8195557eef230a95d2a7c53c Mon Sep 17 00:00:00 2001 From: dam1n19 <dam1n19@soton.ac.uk> Date: Fri, 30 Jun 2023 10:58:38 +0100 Subject: [PATCH] Redistributed Filelists --- flist/accelerator_wrapper_ip.flist | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 flist/accelerator_wrapper_ip.flist diff --git a/flist/accelerator_wrapper_ip.flist b/flist/accelerator_wrapper_ip.flist new file mode 100644 index 0000000..f41d660 --- /dev/null +++ b/flist/accelerator_wrapper_ip.flist @@ -0,0 +1,28 @@ +//----------------------------------------------------------------------------- +// Accelerator Wrapper Filelist +// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. +// +// Contributors +// +// David Mapstone (d.a.mapstone@soton.ac.uk) +// +// Copyright � 2021-3, SoC Labs (www.soclabs.org) +//----------------------------------------------------------------------------- +//----------------------------------------------------------------------------- +// Abstract : Verilog Command File for Accelerator Wrapper IP +//----------------------------------------------------------------------------- + +// ============= Verilog library extensions =========== ++libext+.v+.vlib + +// ============= Accelerator Module search path ============= +$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_ahb_packet_constructor.sv +$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_ahb_packet_deconstructor.sv +$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_addr_calc.sv +$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_data_req.sv +$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_ahb_reg_interface.sv +$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_packet_construct.sv +$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_packet_deconstruct.sv +$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_req_ctrl_reg.sv +$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_dmac_req.sv +$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_valid_filter.sv -- GitLab