Skip to content
Snippets Groups Projects

Compare revisions

Changes are shown as if the source revision was being merged into the target revision. Learn more about comparing revisions.

Source

Select target project
No results found
Select Git revision
  • at-adipisci-ducimus-qui-nihil
  • atque-corrupti-laboriosam-nobis-explicabo
  • aut-deleniti-est-voluptatum-repellat
  • autem-at-dolore-molestiae-et
  • cumque-occaecati-veniam-qui-sit
  • dolorem-ratione-sed-illum-minima
  • dolores-sit-quos-explicabo-ut
  • doloribus-dolorem-quos-adipisci-et
  • ea-dolor-quia-et-sint
  • et-laudantium-voluptas-quos-pariatur
  • et-recusandae-deleniti-voluptas-consectetur
  • feat_deconstruct_irq_gen
  • inventore-temporibus-ipsum-neque-rerum
  • ipsum-consequatur-et-in-et
  • laudantium-unde-et-iste-et
  • main
  • modi-et-quam-sunt-consequatur
  • nostrum-ut-vel-voluptates-et
  • qui-in-quod-nam-voluptatem
  • quisquam-dolorum-minus-non-ipsam
  • sapiente-et-possimus-neque-est
  • sed-sit-tempore-expedita-possimus
  • voluptatem-quia-fugit-ut-perferendis
23 results

Target

Select target project
  • soclabs/accelerator_wrapper_tech
1 result
Select Git revision
  • at-adipisci-ducimus-qui-nihil
  • atque-corrupti-laboriosam-nobis-explicabo
  • aut-deleniti-est-voluptatum-repellat
  • autem-at-dolore-molestiae-et
  • cumque-occaecati-veniam-qui-sit
  • dolorem-ratione-sed-illum-minima
  • dolores-sit-quos-explicabo-ut
  • doloribus-dolorem-quos-adipisci-et
  • ea-dolor-quia-et-sint
  • et-laudantium-voluptas-quos-pariatur
  • et-recusandae-deleniti-voluptas-consectetur
  • feat_deconstruct_irq_gen
  • inventore-temporibus-ipsum-neque-rerum
  • ipsum-consequatur-et-in-et
  • laudantium-unde-et-iste-et
  • main
  • modi-et-quam-sunt-consequatur
  • nostrum-ut-vel-voluptates-et
  • qui-in-quod-nam-voluptatem
  • quisquam-dolorum-minus-non-ipsam
  • sapiente-et-possimus-neque-est
  • sed-sit-tempore-expedita-possimus
  • voluptatem-quia-fugit-ut-perferendis
23 results
Show changes
Commits on Source (1)
#-----------------------------------------------------------------------------
# SoC Labs icarus verilog simulation script for engine testbench
# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
#
# Contributors
#
# David Mapstone (d.a.mapstone@soton.ac.uk)
#
# Copyright 2022, SoC Labs (www.soclabs.org)
#-----------------------------------------------------------------------------
#!/usr/bin/env bash
mkdir -p $SOC_TOP_DIR/simulate/sim/
iverilog -c $ACC_WRAPPER_DIR/flist/accelerator_wrapper.flist -c $ACC_WRAPPER_DIR/flist/ahb_ip.flist -c $ACC_ENGINE_DIR/flist/*.flist -I $ACC_WRAPPER_DIR/hdl/verif/ -I $ACC_WRAPPER_DIR/hdl/verif/submodules -I $ACC_WRAPPER_DIR/hdl/src/ -I $ACC_ENGINE_DIR/hdl/src/ -g2012 -o $SOC_TOP_DIR/simulate/sim/wrapper_sha256_hashing_stream.vvp $ACC_WRAPPER_DIR/hdl/verif/tb_wrapper_sha256_hashing_stream.sv
cd $SOC_TOP_DIR/simulate/sim/ && vvp wrapper_sha256_hashing_stream.vvp +STIMFILE=$ACC_WRAPPER_DIR/simulate/stimulus/ahb_input_hash_stim.m2d
\ No newline at end of file
socsim @ 55fae46b
Subproject commit 55fae46b24cd1ec6e93347e553ad3d5e88fc0064