Accelerator System Top-Level

This repo is the top-level repository which contains an example accelerator based on the secworks AES engine integrated in SoC Labs provided nanosoc chip design IP in forms of git subrepositories.

The SoC wiring is handled in this repository too, along with design and verification for accelerator wrappers.

Re-creating the top-level design

Set up the environment variables and paths for this prohect:

source set_env.sh

This sets the environment variables related to this project and creates visability to the scripts in the flow directory.

Running the simulation

This design instantiates a custom (AMBA-AHB) wrapper around the AES core to implement a memory-mapped 128-bit AES encrypt/decrypt accelerator that can be used as a software-driven peripheral or a semi-autonomous DMA subystem when 128-bit keys and variable length data payloads can be set up as scatter/gather descriptor chains for background processing.

To run the simulation the 'socsim' command executes the makefile in the 'nanosoc_tech' microcontroller framework. (Edit the simulator target in nanosoc_tech/nanosoc/makefile for the simulator EDA tool used). Then use the

socsim system_aes128 TESTNAME=aes128_tests

This runs the integration test program on the Arm Cortex-M0 processor using the 'system_aes128.sh' script provided in the simulate/socsim directory and the logs are produced in the simulate/sim/system_aes128/logs directory.